GS9001
EDH Coprocessor
GENLINX
TM
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Japan Branch: A-302, Miyamae Village, 2-10-42, Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3247-8838 fax. (03) 3247-8839
Document No. 521 - 38 - 02
DATA SHEET
Control
Logic
Compare
Errored
Field
Counter
Serial Clock
& Data
Device Address
Ancillary
Check
Error Flags
&
Format
CRC
Extraction
Transmit/
Receive
Data In
Clock
Reset
CRC
Calculation
Automatic
Standards
Detection
Data
Out
Interrupt
Transmission
Error Flags
HSync, VBlank,
Ancillary Data, TRS-ID,
TRS Absence Indication
Field Signals/
Standard Indication
Mux
I
C
Interface
2
APPLICATIONS
The GS9001 implements error detection and handling (EDH)
functions according to SMPTE RP165. Interfacing to the
parallel port of either the GS9002/GS9022 serial digital
encoders or GS9000 decoder, the GS9001 provides EDH
insertion and extraction for 4sc NTSC, 4sc
PAL and 4:2:2
component standards up to 18 MHz luminance sampling.
The GS9001 also generates timing signals such as horizontal
sync, vertical blanking, field ID and ancillary data identification.
The ancillary data identification aids the extraction of ancillary
data from the data stream.
The device has an
I
2
C (Inter-Integrated Circuit) serial interface
bus for communication with a microcontroller. The device
can be programmed as an
I
2
C slave transmitter or receiver by
the microcontroller. This interface can be used to read the
complete set of error flags and override the flag status prior to
re-transmission. The device automatically determines the
operating standard which can be overridden through the
I
2
C
interface. Timing signals and transmission error flags are also
available on dedicated outputs.
FEATURES
DESCRIPTION
4sc, 4:2:2 and 360 Mb/s serial digital interfaces
Source and destination equipment
Distribution equipment
Test equipment
Error Detection and Handling (EDH) according to
SMPTE RP165
EDH insertion and extraction in one device
autostandard operation
I
2
C Serial communications interface for access to
error flags and device configuration
available stand alone mode
error flags available on dedicated outputs
field, vertical, horizontal timing signals, ancillary data
indication and TRS indication
video standard and invalid data indication
reserved words readable and writeable
21 bit Errored Fields counter
passthrough mode to bypass EDH packet insertion
true 8-bit compatibility
40 MHz operating frequency
Part Number
Package Temperature
GS9001-CQM
44 PQFP
O
C to 70
C
ORDERING INFORMATION
BLOCK DIAGRAM
Revision Date: February 1996
I
2
C
is a registered Trademark of Philips
2
521 - 38 - 02
ELECTRICAL CHARACTERISTICS DC Parameters @ V
DD
= 5V, V
SS
= 0V, T
A
= 0
o
C - 70
o
C unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units
Supply Voltage
V
S
Operating range
4.75
5.00
5.25
V
Supply Current
I
S
Operating range
-
85
100
mA
TTL Compatible
V
IHmin
T
A
=25
o
C
2.00
-
-
V
CMOS Inputs
V
ILmax
T
A
=25
o
C
-
-
0.80
V
Input Leakage
I
IN
V
IN
=V
DD
or V
SS
-
-
10
A
TTL Compatible
V
OHmin
T
A
=25
o
C
2.40
4.50
-
V
CMOS Outputs
V
OLmax
T
A
=25
o
C
-
0.20
0.40
V
I
OL
T
A
=25
o
C
-
-
-4
mA
I
OH
T
A
=25
o
C
-
-
4
mA
AC Parameters @ V
DD
= 5V, V
SS
= 0V, T
A
= 0
o
C - 70
o
C unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input Clock Frequency
clk
-
-
40
MHz
Input & Output Data Rates
data
-
-
40
Mb/s
Input Data & Clock
Rise Time
t
ir
-
1
-
ns
Setup Time
t
set
T
A
=25
o
C
2
-
-
ns
Hold Time
t
hold
2
-
-
ns
Input Clock to Output data
t
P
C
L
< 30pF
3
5.5
8.5
(1)
ns
Output data rise/fall time
t
or
T
A
=25
o
C
2
3
4
ns
SCL Clock Frequency
SCL
-
100
400
(2)
kHz
(1)
T
A
= 70
c, V
DD
= 4.75V
(2)
Determined by I
2
C bus specification
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE/UNITS
Supply Voltage (V
s
=V
DD
-V
ss
)
7 V
Input Voltage Range (any input)
-0.3 to (V
DD
+0.3) V
DC Input Current (any one input)
10
A
Power Dissipation
800 mW
Operating Temperature Range
0
C to 70
C
Storage Temperature Range
-65
C to +150
C
Lead Temperature (soldering, 10 seconds)
260
C
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
3
521 - 38 - 02
DIN9
(MSB)
(MSB)
(LSB)
(LSB)
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
CLK
GS9001
TOP VIEW
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
DOUT9
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
INTERRUPT
V
DD
V
DD
V
SS
F2/NTSC_PAL
NO TRS
F0/HD1
F1/D1_D2
VBLANK
HSYNC
FL0
ANC_DATA
FL1
FIELD/STD
R/T
A0
A1
SCL
V
SS
S0
S1
RSTN
SDA
Fig. 1 GS9001 EDH Coprocessor Pin Connections
Input S1
Input S0
Output FL1
Output FL0
0
0
EDA
Full Field
EDH
Full Field
0
1
UES
(See Note)
EDH
Active Picture
1
0
EDA
Ancillary
EDH
Ancillary
1
1
IDA
(See Note)
IDH
(See Note)
NOTE:
The UES, IDH and IDA flags that appear on pins FL0 and FL1 as shown in Table 2, represent the sum of each
corresponding flag for active picture, full field and ancillary. UES indication can also be used to identify the absence
of EDH implementation in the upstream equipment.
Table 1. Selection of Field and Video standard signals on F2, F1, F0 pins
Table 2. Selection of Error status flags to display
Input
Output F2
Output F1
Output F0
Field/Std
0
NTSC (0) / PAL (1)
D1 (0) / D2 (1)
*
13.5 MHz Y (0) / 18 MHz Y (1)
1
Field Bit 2 Field Bit 1
Field Bit 0
*
D1: 4:2:2 sampling
D2: 4
sc
sampling
4
521 - 38 - 02
PIN NO.
SYMBOL TYPE DESCRIPTION
1-10
DIN[9..0]
I
Parallel digital video data inputs
11
CLK
I
Parallel clock input.
12
R/T
I
Receive or Transmit mode select. High - CRC extraction, recalculation, comparison, error
indication, re-insertion. Low - CRC calculation, insertion, clears error flags
13
FIELD/STD
I
Field or Standard indication select. High - Field signals on F0, F1, F2. Low - Standard
indication on F0, F1,F2. (Refer to Table 1)
14,15
S0, S1
I
Error flag select inputs. Select type of error flag to output on FL0, FL1. (Refer to Table 2)
16
RSTN
I
Master Reset. Active low input, which provides option to initialise internal circuitry. The
GS9001 contains power on reset circuitry that automatically initialises all internal
states including the
I
2
C Interface.
19,20
A0,A1
I
Device address select pins for
I
2
C interface bus. (Refer to Table 3)
21
SCL
I
Serial Clock for
I
2
C Interface bus. SCL and SDA must be connected to GND if there is no
I
2
C interface connected to the device.
22
SDA
I/O
Serial Data for
I
2
C
Interface bus.
23
INTERRUPT
O
Programmable interrupt for error flag indication. Active low, open drain output. Interrupt
can be made sensitive to specific or all error flags (described in
I
2
C WRITE format
section). Default is sensitive to all error flags. This output stays active until a word is read
from the device.
24-33
DOUT[0..9]
O
Parallel digital video data outputs
34
NO TRS
O
Indicates presence of invalid input data, containing no timing reference signal (TRS).
Active high output which signals absence of seven consecutive valid TRSs in the
incoming data. Returns to low state after seven consecutive valid TRSs occur. A valid
input CLK must be present for this to operate.
35
ANC DATA
O
Ancillary data presence indication. Active high output, indicates data presence from
ANC data header word to checksum word. Can be programmed through the
I
2
C
interface to also indicate presence of TRS-ID (3FF,000,000) blocks. In this mode, output
stays high for 5 words during composite video TRS-ID and 4 words during component
EAV, SAV. In stand alone operation mode without
I
2
C Interface, this feature can be
forced on ANC DATA pin by selecting address 0,1 on A1,A0 pins. (NOTE: SCL and SDA
must be connected to GND when
I
2
C Interface is not used)
36
HSYNC
O
Horizontal sync indication. Active high, extends from EAV to SAV for component video,
indicates TRS-ID location for composite video.
37
V BLANK
O
Vertical blanking interval indication. Active high during this period.
40-42
F0/HD1
O
Field or standard indication pins. Field signals output when FIELD/STD pin is high, Video
F1/D1_D2,
standard when FIELD/STD is low.
F2/NTSC_PAL
43,44
FL1,FL0
O
Error Flag Status. Active high outputs programmed via S0, S1 to indicate various
transmission and hardware related error flags. Output flags stay active for one field.
17,39
V
DD
P
Power Supply. Most positive power supply connection. (+5V)
18,38
V
SS
P
Power Supply. Most negative power supply connection. (GND)
GS9001 PIN DESCRIPTIONS
5
521 - 38 - 02
GS9001 - DETAILED DEVICE DESCRIPTION.
The GS9001 contains all functional blocks required to implement
Error Detection and Handling according to SMPTE RP165. It
also provides Field, Vertical, and Horizontal timing information
as well as Ancillary Data and TRS-ID indication. The device
offers standard independent operation and an
I
2
C serial
communications interface to allow reading/writing of error
flags, device configuration and video standards format. The
device can also be operated in stand alone mode without the
I
2
C interface with error flags available on dedicated output
pins. In all modes, the device latency is four clock cycles.
Automatic Standards Detection
This block analyses the incoming 8 or 10 bit data to determine
whether it is component or composite. In total, six standards
are automatically detected. For composite data conforming to
SMPTE 259M, the Timing Reference Signal and Identification
(TRS-ID) packet contains line and field information used to
detect the format. For component data conforming to SMPTE
125M, the TRS-ID packets for End of Active Video (EAV)and
Start of Active Video (SAV) are used to determine the format.
The TRS information is then used to determine whether the
composite signal is NTSC or PAL, or whether the component
signal has 13.5 MHz or 18 MHz luminance samples.
Noise immunity has also been included, to ensure that
momentary signal interruption does not affect the auto-
standards detection function. This built in noise immunity
results in delayed switching time between standards. Delays
range from as little as eight lines when switching between
component standards to as much as four frames when switching
between PAL and NTSC composite standards. The latter
delay is due to the method used to differentiate PAL and NTSC,
which counts the number of lines per frame and requires four
sequential frames before switching standards. Manual override
of the auto-standard feature is provided via the
I
2
C interface,
for applications where the standards recognition delay is
intolerable. Standards indication is provided on multiplexed
output pins or via the
I
2
C interface.
Control Logic
The control logic coordinates operation and extracts timing
signals such as vertical blanking, horizontal sync, field ID,
ancillary data indication and TRS-ID indication.
The vertical blanking interval signal is active during the digital
vertical blanking period for all signal formats. The horizontal
sync signal is provided as a pulse with a duration of one clock
period for every TRS-ID occurrence in composite video. For
component video, the horizontal sync is a positive going pulse
which starts at EAV and ends at SAV. Three field ID bits (pins
40, 41, 42) indicate the two fields for component video standards,
the four colour fields for composite NTSC or eight colour fields
for composite PAL.
The ancillary data indication allows external circuitry to identify
ancillary data in the data stream for extraction or masking.
The presence of ancillary data is indicated by a logic high that
extends from the Data ID word to the Checksum word of each
ancillary packet. These timing signals are available on
dedicated output pins and through the
I
2
C communications
interface.
The control logic also verifies incoming data validity by checking
the occurrence of consecutive TRS-IDs. If the absence of
seven consecutive TRS-IDs is detected, a "NO TRS" flag is
output on pin 34. This flag is reset once seven consecutive
TRS-IDs occur.
CRC Calculation
A cyclic redundancy check (CRC) is calculated for each video
field according to the CRC-CCITT polynomial X
16
+X
12
+X
5
+1.
Separate CRCs are calculated for active picture and full field
to provide an indication that active video is still intact despite
possible full field errors. This allows the user to distinguish
between different classes of data errors, which yields the best
compromise in error detection for all types of equipment. In
order to provide compatibility between 8 bit and 10 bit systems,
all data words with values between 3FC
H
and 3FF
H
inclusive,
are recoded as 3FF
H
at the input of the polynomial generator.
Start and end points for the CRC calculation are as defined in
RP165 and depend on the standard and check field being
calculated. Calculated CRC words can be read through the
I
2
C interface.
CRC Comparison
The GS9001 can be configured for transmit or receive mode.
In receive mode, the calculated CRC is checked against the
incoming CRC embedded in the error data packet. Any
mismatch will generate status error flags to indicate transmission
related error flags in either active picture, full field or both. The
error flags resulting from CRC mismatch are full field error
detected here (
EDH
) and active picture
EDH
.
Ancillary Checksum Verification
The ancillary data checksums are also verified to ensure data
integrity. Ancillary data is preceded by the Data Header, Data
ID, Block Number and Data Count. The Data Count shows the
number of ancillary words contained in each ancillary data
packet. A checksum is calculated for each incoming ancillary
data packet and compared with the transmitted checksum.
Any difference is reported as an error via the ancillary
EDH
error flag. A separate
ANC EXT
error flag is also provided to
indicate corruption of the EDH data packet.
Error Flags and Formatting
This block performs the functions of error flag reporting and
recoding, EDH data packet construction, programmable
interrupt generation and interface with the
I
2
C communication
block.
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