GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Revision Date: November 2000
Document No. 522 - 47 - 00
PRELIMINARY DATA SHEET
G
S
1
510
FEATURES
SMPTE 292M compliant
standards detection/indication for SMPTE 292M levels
A/B,C,D/E,F,G/H,I,J/K,L/M
NRZI decoding and SMPTE descrambling with
BYPASS option
line CRC calculation, comparison
selectable line based CRC re-Insertion
H, V, F timing reference signal (TRS) extraction
selectable flywheel for noise immune H, V, F extraction
selectable automatic switch line handling
selectable TRS and line number re-insertion
selectable active picture illegal code re-mapping
configurable FIFO LOAD pulse
20 bit 3.3V CMOS input data bus
optimized input interface to GS1545 or GS1540
single +3.3V power supply
5V tolerant I/O
APPLICATIONS
SMPTE 292M Serial Digital Interfaces.
DESCRIPTION
When interfaced to the Gennum GS1545 HDTV Equalizing
Receiver or GS1540 Non-Equalizing Receiver, the GS1510
performs the final conversion to word aligned data. The
device performs NRZI decoding and de-scrambling as per
SMPTE 292M and word-aligns to the incoming data stream.
Line based CRCs are calculated on the incoming data
stream and are compared against the CRCs embedded
within the data stream.
HVF timing information is extracted from the data stream. A
selectable internal HVF flywheel provides superior noise
immunity against TRS signal errors. The device also detects
and indicates the input video signal standard.
The GS1510 can detect and re-map illegal code words
contained within the active portion of the video signal. Prior
to exiting the device, TRS, Line Numbers and CRCs based
on internal calculations may be re-inserted into the data
stream.
BLOCK DIAGRAM
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
GS1510-CQR
128 pin MQFP
0C to 70C
INPUT
BUFFER
DESCRAMBLE
FRAME
PCLK_IN
DATA_IN
[19:0]
WB_NI
BP_DSC
BP_FR
[H:V:F]
LN_ERR
SAV_ERR
EAV_ERR
VD_STD [3:0]
LINE_CRC_ERR [Y:C]
CODE
PROTECT
TRS_INS
LN_INS
CRC_INS
DATA_OUT
[19:10]
(LUMA)
DATA_OUT
[9:0]
(CHROMA)
TRS,
LNUM,
AND CRC
INSERTION
FW_EN/DIS
FAST_LOCK
RESET
TRS_Y/C
F_E/S
MUTE
OEN
3
2
4
3
3
2
2
TRS DETECTION
FLYWHEEL
STANDARD DETECTION
TRS EXTRACTION
CRC CALCULATION
CRC COMPARISON
ILLEGAL CODE REMAPPING
3
FIFO_L
HD-LINX
TM
GS1510
HDTV Serial Digital Deformatter
GENNUM CORPORATION
522 - 47 - 00
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G
S
1
510
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
Supply Voltage
-0.5V to +4.6V
Input Voltage Range (any input)
-0.5V < V
IN
< 5.5V
Operating Temperature Range
0
C
T
A
70
C
Storage Temperature Range
-40
C
T
S
125
C
Lead Temperature (soldering 10 seconds)
260
C
DC ELECTRICAL CHARACTERISTICS
V
DD
= 3.0 to 3.6V, T
A
= 0
C to 70
C, unless otherwise shown
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Positive Supply Voltage
V
DD
3.0
3.3
3.6
V
Supply Current
DD
= 74.25MHz, T
A
= 25C
-
402
480
mA
Input Logic LOW Voltage
V
IL
I
LEAKAGE
< 10A
-
-
0.8
V
Input Logic HIGH Voltage
V
IH
I
LEAKAGE
< 10A
2.1
3.3
5.0
V
Output Logic LOW Voltage
V
OL
V
DD
= 3.0 to 3.6V, I
OL
= 4mA
-
0.2
0.4
V
Output Logic HIGH Voltage
V
OH
V
DD
= 3.0 to 3.6V, I
OH
= -4mA
2.6
-
-
V
AC ELECTRICAL CHARACTERISTICS
V
DD
= 3.0 to 3.6V, T
A
= 0
C to 70
C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Clock Input Frequency
F
HSCI
-
74.25
80
MHz
Also supports 74.25/1.001MHz
Input Data Setup Time
t
SU
2.5
-
-
ns
50% levels
Input Data Hold Time
t
IH
1.5
-
-
ns
50% levels
Input Clock Duty Cycle
40
-
60
%
Output Data Hold Time
t
OH
With 15pF load
2.0
-
-
ns
Output Enable Time
t
OEN
With 15pF load
-
-
8
ns
Output Disable Time
t
ODIS
With 15pF load
-
-
9
ns
Output Data Delay Time
t
OD
With 15pF load
-
-
10
ns
Output Data Rise/Fall Time
t
ROD
/t
FOD
With 15pF load
-
-
2.5
ns
20% to 80% levels
GENNUM CORPORATION
522 - 47 - 00
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S
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510
PIN CONNECTIONS
V
DD
GND
OEN
TN
FIFO_L
LINE_CRC_ERR_Y
LINE_CRC_ERR_C
VD_STD[0]
VD_STD[1]
VD_STD[2]
VD_STD[3]
NC
NC
V
DD
GND
F
V
H
V
DD
GND
RESET
FAST_LOCK
CRC_INS
LN_INS
GND
TRS_INS
TRS_Y/C
WB_NI
BP_DSC
BP_FR
CODE_PROTECT
FW_EN/DIS
MUTE
F_E/S
GND
V
DD
GND
PCLK_IN
LN_ERR
SAV_ERR
EAV_ERR
V
DD
GND
TEST
NC
NC
NC
NC
NC
NC
NC
V
DD
GND
NC
V
DD
GND
NC
NC
NC
NC
NC
NC
NC
V
DD
GND
V
DD
V
DD
GND
GND
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
GND
D
A
T
A_OUT[19]
D
A
T
A_OUT[18]
D
A
T
A_OUT[17]
D
A
T
A_OUT[16]
D
A
T
A_OUT[15]
V
DD
GND
D
A
T
A_OUT[14]
D
A
T
A_OUT[13]
D
A
T
A_OUT[12]
D
A
T
A_OUT[11]
D
A
T
A_OUT[10]
D
A
T
A_OUT[9]
V
DD
GND
D
A
T
A_OUT[8]
D
A
T
A_OUT[7]
V
DD
GND
D
A
T
A_OUT[6]
D
A
T
A_OUT[5]
D
A
T
A_OUT[4]
D
A
T
A_OUT[3]
D
A
T
A_OUT[2]
D
A
T
A_OUT[1]
D
A
T
A_OUT[0]
D
A
T
A_IN[19]
D
A
T
A_IN[18]
D
A
T
A_IN[17]
D
A
T
A_IN[16]
D
A
T
A_IN[15]
D
A
T
A_IN[14]
V
DD
GND
D
A
T
A_IN[13]
D
A
T
A_IN[12]
D
A
T
A_IN[11]
D
A
T
A_IN[10]
V
DD
GND
D
A
T
A_IN[9]
D
A
T
A_IN[8]
D
A
T
A_IN[7]
D
A
T
A_IN[6]
D
A
T
A_IN[5]
D
A
T
A_IN[4]
D
A
T
A_IN[3]
D
A
T
A_IN[2]
D
A
T
A_IN[1]
D
A
T
A_IN[0]
V
DD
GND
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
GS1510
TOP
VIEW
GENNUM CORPORATION
522 - 47 - 00
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510
PIN DESCRIPTIONS
NUMBER
SYMBOL
TIMING
TYPE
DESCRIPTION
1
PCLK_IN
Synchronous
wrt PCLK_IN
Input
Input Clock.
The device uses PCLK_IN for clocking the input
data stream into DATA_IN[19:0]. This clock is generated by
the GS1545 or GS1540
2, 4, 14, 19, 24, 37,
46, 50, 58, 69, 79,
82, 91, 94, 110,
116, 128
GND
Gnd
Ground power supply connections.
3, 20, 25, 38, 47,
51, 59, 68, 78, 81,
90, 93, 109, 115,
127
V
DD
Power
Positive power supply connections.
5
F_E/S
Non-
synchronous
Input
Control Signal Input.
Used to control where the FIFO_L signal
is generated. When F_E/S is high, the GS1510 generates
FIFO_L signal at EAV. When F_E/S is low, the GS1510
generates FIFO_L signal at SAV. See Fig. 4 for timing
information.
6
MUTE
Synchronous
wrt PCLK_IN
Input
Control Signal Input.
Used to enable or disable blanking of
the LUMA (DATA_OUT[19:10]) and CHROMA
(DATA_OUT[9:0]). When MUTE is low, the device sets the
accompanying LUMA and CHROMA data to their appropriate
blanking levels. When MUTE is high, the LUMA and CHROMA
data streams pass through this stage of the device unaltered.
7
FW_EN/DIS
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable the internal
flywheel. When FW_EN/DIS is high, the internal flywheel is
enabled. When FW_EN/DIS is low, the internal fly-wheel is
disabled.
8
CODE_PROTECT
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable re-mapping of
out-of-range words contained in the active portion of the video
signal. When this signal is high, the device re-maps out-of-
range words contained within the active portion of the video
signal into CCIR-601 compliant words. Values between
000-003 are re-mapped to 004. Values between 3FC and 3FF
are re-mapped to 3FB. When this signal is low, out-of-range
words in the active video region pass through the device
unaltered.
9
BP_FR
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable word
boundary framing. When BP_FR is low internal framing is
enabled. When BP_FR is high internal framing is bypassed.
10
BP_DSC
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable the SMPTE
292M descrambler. When BP_DSC is low, the internal SMPTE
292M descrambler is enabled. When BP_DSC is high, the
internal SMPTE 292M de-scrambler is bypassed.
11
WB_NI
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable noise immune
operation of the word boundary framer. When WB_NI is high,
noise-immune word boundary alignment is enabled. The
device switches to a new word boundary only when it has
detected two consecutive identical new TRS positions. When
WB_NI is low, the device re-aligns the word boundary position
at every instance of a TRS.
12
TRS_Y/C
Non-
synchronous
Input
Control Signal Input.
Used to control whether LUMA or
CHROMA TRS IDs are detected and used. When TRS_Y/C is
high, the device detects and uses TRS signals embedded in
the LUMA channel. When TRS_Y/C is low, the device detects
and uses TRS signals embedded in the CHROMA channel.
GENNUM CORPORATION
522 - 47 - 00
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G
S
1
510
13
TRS_INS
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable re-insertion of
the TRS into the data stream. When TRS_INS is high, the
device re-inserts TRS into the incoming data stream based on
the internal calculation. The original TRS packets are set to the
blanking levels. If the flywheel is enabled, TRS calculated by
the flywheel is used for insertion. When TRS_INS is low, the
device will not re-insert TRS even if errors in TRS signals are
detected.
15
LN_INS
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable re-insertion of
the line number into the data stream. When LN_INS is high, the
device re-inserts the line number into the incoming data
stream based on the internal calculation. The original line
number packets are set to the blanking levels. If the flywheel is
enabled, the line number calculated by the flywheel is used for
insertion. When LN_INS is low, the device will not re-insert the
line number.
16
CRC_INS
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable re-insertion of
the CRC into the data stream. When CRC_INS is high, the
device is enabled to re-insert line CRCs based on the internal
calculation. When CRC_INS is low, the device will not re-insert
the CRCs.
17
FAST_LOCK
Synchronous
wrt PCLK_IN
Input
Control Signal Input.
Used to control the flywheel
synchronization when a switch line occurs. When a low to high
transition occurs on the FAST_LOCK signal, the internal
flywheel will immediately re-synchronize to the next valid EAV
or SAV TRS in the incoming data stream. See Fig. 5 for timing
information.
18
RESET
Non-
synchronous
Input
Control Signal Input.
Used to reset the system state registers to
their default 720p parameters. When RESET is high, the fly
wheel, TRS Detection, and ANC Detection operate normally.
When RESET is low, the flywheel, TRS Detection, and ANC
Detection are reset to the 720p parameters after a rising edge
on PCLK_IN. The read and write counters are not affected.
21
H
Synchronous
wrt PCLK_IN
Output
Control Signal Input.
This signal indicates the Horizontal
blanking period of the video signal. Refer to Fig. 2 for timing
information of H relative to DATA_OUT[19:10] and
DATA_OUT[9:0], LUMA and CHROMA respectively.
22
V
Synchronous
wrt PCLK_IN
Output
Control Signal Input.
This signal indicates the Vertical blanking
period of the video signal. Refer to Fig. 2 for timing information
of V relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA
and CHROMA respectively.
23
F
Synchronous
wrt PCLK_IN
Output
Control Signal Input.
This signal indicates the ODD/EVEN field
of the video signal. Refer to Fig. 2 for timing information of F
relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and
CHROMA respectively. When locked and the input signal is of
a progressive scan nature, F stays low at all times.
26,27,71-77,80,
83-89
NC
N/A
N/A
No Connect.
Do not connect these pins.
28, 29, 30, 31
VD_STD[3:0]
Synchronous
wrt PCLK_IN
Output
Control Signal Output.
VD_STD[3:0] indicates which input
video standard the device has detected. The GS1510 will
indicate all of the formats in SMPTE292M (see Table 1) plus it
will indicate an unknown interlace or progressive scan format.
PIN DESCRIPTIONS
NUMBER
SYMBOL
TIMING
TYPE
DESCRIPTION
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