DS07-16301-2E

FUJITSU SEMICONDUCTOR

DATA SHEET

32-bit RISC Microcontroller

CMOS

FR30 Series

MB91101/MB91101A

DESCRIPTION

The MB91101 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family)
core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU
processing for embedded controller applications. To support the vast memory space accessed by the 32-bit
CPU, the MB91101 normally operates in the external bus access mode and executes instructions on the internal
1 Kbyte cache memory and 2 Kbytes RAM for enhanced performance.

The MB91101 is optimized for applications requiring high-performance CPU processing such as navigation
systems, high-performance FAXs and printer controllers.

*: FR Family stands for FUJITSU RISC controller.

FEATURES

FR CPU

· 32-bit RISC, load/store architecture, 5-stage pipeline
· Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
· General purpose registers: 32 bits

· 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
· Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
· Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems

supporting high level languages

· Register interlock functions, efficient assembly language coding
· Branch instructions with delay slots: Reduced overhead time in branch executions

(Continued)

PACKAGE

100-pin Plastic LQFP

(FPT-100P-M05)

100-pin Plastic QFP

(FPT-100P-M06)

MB91101/MB91101A

(Continued)

· Internal multiplier/supported at instruction level

Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles

· Interrupt (push PC and PS): 6 cycles, 16 priority levels

External bus interface

· Clock doubler: Internal 50 MHz, external bus 25 MHz operation
· 25-bit address bus (32 Mbytes memory space)
· 8/16-bit data bus
· Basic external bus cycle: 2 clock cycles
· Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6
· Interface supported for various memory technologies

DRAM interface (area 4 and 5)

· Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area
· Unused data/address pins can be configured us input/output ports
· Little endian mode supported (Select 1 area from area 1 to 5)

DRAM interface

· 2 banks independent control (area 4 and 5)
· Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM
· Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode
· Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles
· DRAM refresh

CBR refresh (interval time configurable by 6-bit timer)
Self-refresh mode

· Supports 8/9/10/12-bit column address width
· 2CAS/1WE, 2WE/1CAS selective

Cache memory

· 1-Kbyte instruction cache memory
· 32 block/way, 4 entry(4 word)/block
· 2 way set associative
· Lock function: For specific program code to be resident in cashe memory

DMA controller (DMAC)

· 8 channels
· Transfer incident/external pins/internal resource interrupt requests
· Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer
· Transfer data length: 8 bits/16 bits/32 bits selective
· NMI/interrupt request enables temporary stop operation

UART

· 3 independent channels
· Full-duplex double buffer
· Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)
· Asynchronous (start-stop system), CLK-synchronized communication selective
· Multi-processor mode
· Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate
· Use external clock can be used as a transfer clock
· Error detection: Parity, frame, overrun

MB91101/MB91101A

(Continued)

10-bit A/D converter (successive approximation conversion type)

· 10-bit resolution, 4 channels
· Successive approximation type: Conversion time of 5.6

s at 25 MHz

· Internal sample and hold circuit
· Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective
· Start: Software/external trigger/internal timer selective

16-bit reload timer

· 3 channels
· Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective

Other interval timers

· 16-bit timer: 3 channels (U-TIMER)
· PWM timer: 4 channels
· Watchdog timer: 1 channel

Bit search module

First bit transition "1" or "0" from MSB can be detected in 1 cycle

Interrupt controller

· External interrupt input: Non-maskable interrupt (NMI), normal interrupt

4 (INT0 to INT3)

· Internal interrupt incident: UART, DMA controller (DMAC), A/D converter, U-TIMER and delayed interrupt

module

· Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps)

Others

· Reset cause: Power-on reset/hardware standby/watchdog timer/software reset/external reset
· Low-power consumption mode: Sleep mode/stop mode
· Clock control

Gear function: Operating clocks for CPU and peripherals are independently selective

Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16)
However, operating frequency for peripherals is less than 25 MHz.

· Packages: LQFP-100 and QFP-100
· CMOS technology (0.35

· Power supply voltage

5 V: CPU power supply 5.0 V

10% (internal regulator)

A/D power supply

2.7 V to 3.6 V

3 V: CPU power supply 2.7 V to 3.6 V (without internal regulator)

A/D power supply

2.7 V to 3.6 V

MB91101/MB91101A

PIN ASSIGNMENT

(FPT-100P-M05)

(Top view)

CS1L/PB5/DREQ2
CS1H/PB6/DACK2
DW1/PB7
V

CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3/EOP1
CS2/PA2
CS1/PA1
CS0
NMI
HST
RST
V

MD0
MD1
MD2
RDY/P80
BGRNT/P81
BRQ/P82
RD
WR0
WR1/P85
D16/P20

2
3
4
5
6

56
55
54
53
52
51

AN3
AN2
AN1
AN0
AV

/AVRL

AVRH
AV

A24/EOP0
A23/P67
A22/P66
V

A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
A16/P60
A15
A14
A13
A12
A11
A10
A09
A08

100

RAS1/PB4/EOP2

DW0/PB3

CS0H/PB2

CS0L/PB1

RAS0/PB0

INT0/PE0

INT1/PE1

INT2/SC1/PE2

INT3/SC2/PE3

DREQ0/PE4

DREQ1/PE5

DACK0/PE6

DACK1/PE7

OCPA0/PF7/ATG

SO2/OCPA2/PF6

SI2/OCPA1/PF5

SO1/TRG3/PF4

SI1/TRG2/PF3

SC0/OCPA3/PF2

SO0/TRG1/PF1

SI0/TRG0/PF0

D17/P21

D18/P22

D19/P23

D20/P24

D21/P25

D22/P26

D23/P27

D24

D25

D26

D27

D28

D29

D30

D31

A00

A01

A02

A03

A04

A05

A06

A07

MB91101/MB91101A

(FPT-100P-M06)

CS0H/PB2

DW0/PB3

RAS1/PB4/EOP2

CS1L/PB5/DREQ2

CS1H/PB6/DACK2

DW1/PB7

CLK/PA6

CS5/PA5

CS4/PA4

CS3/PA3/EOP1

CS2/PA2

CS1/PA1

CS0

NMI

HST

RST

MD0

MD1

MD2

RDY/P80

BGRNT/P81

BRQ/P82

WR0

WR1/P85

D16/P20

D17/P21

D18/P22

SO0/TRG1/PF1
SI0/TRG0/PF0
AN3
AN2
AN1
AN0
AV

/AVRL

AVRH
AV

A24/EOP0
A23/P67
A22/P66
V

A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
A16/P60
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05

100

CS0L/PB1

RAS0/PB0

INT0/PE0

INT1/PE1

INT2/SC1/PE2

INT3/SC2/PE3

DREQ0/PE4

DREQ1/PE5

DACK0/PE6

DACK1/PE7

OCPA0/PF7/ATG

SO2/OCPA2/PF6

SI2/OCPA1/PF5

SO1/TRG3/PF4

SI1/TRG2/PF3

SC0/OCPA3/PF2

D19/P23

D20/P24

D21/P25

D22/P26

D23/P27

D24

D25

D26

D27

D28

D29

D30

D31

A00

A01

A02

A03

A04

(Top view)

MB91101/MB91101A

PIN DESCRIPTION

*1: FPT-100P-M05

(Continued)

*2: FPT-100P-M06

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

25 to 32

28 to 35

D16 to D23

Bit 16 to bit 23 of external data bus

P20 to P27

Can be configured as I/O ports when external data bus width is
set to 8-bit.

33 to 39,

36 to 42,

D24 to D30,
D31

Bit 24 to bit 31 of external data bus

42,

44 to 58

45,

47 to 61

A00,
A01 to A15

Bit 00 to bit 15 of external address bus

59 to 64,

66,

62 to 67,

69,

A16 to A21,
A22,
A23

Bit 16 to bit 23 of external address bus

P60 to P65,
P66,
P67

Can be configured as I/O ports when not used as address bus.

A24

Bit 24 of external address bus

EOP0

Can be configured as DMAC EOP output (ch. 0) when DMAC
EOP output is enabled.

RDY

External ready input
Inputs "0" when bus cycle is being executed and not
completed.

P80

Can be configured as a port when RDY is not used.

BGRNT

External bus release acknowledge output
Outputs "L" level when external bus is released.

P81

Can be configured as a port when BGRNT is not used.

BRQ

External bus release request input
Inputs "1" when release of external bus is required.

P82

Can be configured as a port when BRQ is not used.

Read strobe output pin for external bus

WR0

Write strobe output pin for external bus
Relation between control signals and effective byte locations is
as follows:

Note: WR1 is Hi-Z during resetting.

Attach an external pull-up resister when using at 16-bit
bus width.

WR1

P85

Can be configured as a port when WR1 is not used.

16-bit bus width

8-bit bus width

D15 to D08

WR0

D07 to D00

WR1

(I/O port enabled)

MB91101/MB91101A

*1: FPT-100P-M05

(Continued)

*2: FPT-100P-M06

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

CS0

Chip select 0 output ("L" active)

CS1

Chip select 1 output ("L" active)

PA1

Can be configured as a port when CS1 is not used.

CS2

Chip select 2 output ("L" active)

PA2

Can be configured as a port when CS2 is not used.

CS3

Chip select 3 output ("L" active)

PA3

Can be configured as a port when CS3 and EOP1 are not
used.

EOP1

EOP output pin for DMAC (ch. 1)
This function is available when EOP output for DMAC is
enabled.

CS4

Chip select 4 output ("L" active)

PA4

Can be configured as a port when CS4 is not used.

CS5

Chip select 5 output ("L" active)

PA5

Can be configured as a port when CS5 is not used.

CLK

System clock output
Outputs clock signal of external bus operating frequency.

PA6

Can be configured as a port when CLK is not used.

RAS0

RAS output for DRAM bank 0
Refer to the DRAM interface for details.

PB0

Can be configured as a port when RAS0 is not used.

100

CS0L

CASL output for DRAM bank 0
Refer to the DRAM interface for details.

PB1

Can be configured as a port when CS0L is not used.

CS0H

CASH output for DRAM bank 0
Refer to the DRAM interface for details.

PB2

Can be configured as a port when CS0H is not used.

DW0

WE output for DRAM bank 0 ("L" active)
Refer to the DRAM interface for details.

PB3

Can be configured as a port when DW0 is not used.

100

RAS1

RAS output for DRAM bank 1
Refer to the DRAM interface for details.

PB4

Can be configured as a port when RAS1 and EOP2 are not
used.

EOP2

DMAC EOP output (ch. 2)
This function is available when DMAC EOP output is enabled.

MB91101/MB91101A

*1: FPT-100P-M05

(Continued)

*2: FPT-100P-M06

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

CS1L

CASL output for DRAM bank 1
Refer to the DRAM interface for details.

PB5

Can be configured as a port when CS1L and DREQ2 are not
used.

DREQ2

External transfer request input pin for DMA
This pin is used for input when external trigger is selected to
cause DMAC operation, and it is necessary to disable output for
other functions from this pin unless such output is made
intentionally.

CS1H

CASH output for DRAM bank 1
Refer to the DRAM interface for details.

PB6

Can be configured as a port when CS1H and DACK2 are not
used.

DACK2

External transfer request acknowledge output pin for DMAC (ch.
2)
This function is available when transfer request output for DMAC
is enabled.

DW1

WE output for DRAM bank 1 ("L" active)
Refer to the DRAM interface for details.

PB7

Can be configured as a port when DW1 is not used.

16 to 18

19 to 21

MD0 to MD2

Mode pins 0 to 2
MCU basic operation mode is set by these pins.
Directly connect these pins with V

or V

for use.

Clock (oscillator) input

Clock (oscillator) output

RST

External reset input

HST

Hardware standby input ("L" active)

NMI

NMI (non-maskable interrupt pin) input ("L" active)

95,

98,

INT0,
INT1

External interrupt request input pins
These pins are used for input during corresponding interrupt is
enabled, and it is necessary to disable output for other functions
from these pins unless such output is made intentionally.

PE0,
PE1

Can be configured as a I/O port when INT0, INT1 are not used.

INT2

External interrupt request input pin
This pin is used for input during corresponding interrupt is
enabled, and it is necessary to disable output for other functions
from this pin unless such output is made intentionally.

SC1

Clock I/O pin for UART1
Clock output is available when clock output of UART1 is enabled.

PE2

Can be configured as a I/O port when INT2 and SC1 are not
used.
This function is available when UART1 clock output is disabled.

MB91101/MB91101A

*1: FPT-100P-M05

(Continued)

*2: FPT-100P-M06

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

INT3

External interrupt request input pin
This pin is used for input during corresponding interrupt is enabled,
and it is necessary to disable output for other functions from this
pin unless such output is made intentionally.

SC2

UART2 clock I/O pin
Clock output is available when UART2 clock output is enabled.

PE3

Can be configured as a I/O port when INT3 and SC2 are not used.
This function is available when UART2 clock output is disabled.

87,

90,

DREQ0,
DREQ1

External transfer request input pins for DMA
These pins are used for input when external trigger is selected to
cause DMAC operation, and it is necessary to disable output for
other functions from these pins unless such output is made
intentionally.

PE4,
PE5

Can be configured as a I/O port when DREQ0, DREQ1 are not
used.

DACK0

External transfer request acknowledge output pin for DMAC (ch. 0)
This function is available when transfer request output for DMAC is
enabled.

PE6

Can be configured as a I/O port when DACK0 is not used.
This function is available when transfer request acknowledge
output for DMAC or DACK0 output is disabled.

DACK1

External transfer request acknowledge output pin for DMAC (ch. 1)
This function is available when transfer request output for DMAC is
enabled.

PE7

Can be configured as a I/O port when DACK1 is not used.
This function is available when transfer request output for DMAC or
DACK1 output is disabled.

SI0

UART0 data input pin
This pin is used for input during UART0 is in input operation, and it
is necessary to disable output for other functions from this pin
unless such output is made intentionally.

TRG0

PWM timer external trigger input pin
This pin is used for input during PWM timer external trigger is in
input operation, and it is necessary to disable output for other
functions from this pin unless such output is made intentionally.

PF0

Can be configured as a I/O port when SI0 and TRG0 are not used.

MB91101/MB91101A

*1: FPT-100P-M05

(Continued)

*2: FPT-100P-M06

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

SO0

UART0 data output pin
This function is available when UART0 data output is enabled.

TRG1

PWM timer external trigger input pin
This function is available when serial data output of PF1, UART0
are disabled.

PF1

Can be configured as a I/O port when SO0 and TRG1 are not
used.
This function is available when serial data output of UART0 is
disabled.

SC0

UART0 clock I/O pin
Clock output is available when UART0 clock output is enabled.

OCPA3

PWM timer output pin
This function is available when PWM timer output is enabled.

PF2

Can be configured as a I/O port when SC0 and OCPA3 are not
used.
This function is available when UART0 clock output is disabled.

SI1

UART1 data input pin
This pin is used for input during UART1 is in input operation, and it
is necessary to disable output for other functions from this pin
unless such output is made intentionally.

TRG2

PF3

Can be configured as a I/O port when SI1 and TRG2 are not used.

SO1

UART1 data output pin
This function is available when UART1 data output is enabled.

TRG3

PWM timer external trigger input pin
This function is available when PF4, UART1 data outputs are
disabled.

PF4

Can be configured as a I/O port when SO1 and TRG3 are not
used.
This function is available when UART1 data output is disabled.

SI2

UART2 data input pin
This pin is used for input during UART2 is in input operation, and it
is necessary to disable output for other functions from this pin
unless such output is made intentionally.

OCPA1

PWM timer output pin
This function is available when PWM timer output is enabled.

PF5

Can be configured as a I/O port when SI2 and OCPA1 are not
used.

MB91101/MB91101A

(Continued)

*1: FPT-100P-M05
*2: FPT-100P-M06

Note: In most of the above pins, I/O port and resource I/O are multiplexed e.g. P82 and BRQ. In case of conflict

between output of I/O port and resource I/O, priority is always given to the output of resource I/O.

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

SO2

UART2 data output pin
This function is available when UART2 data output is enabled.

OCPA2

PWM timer output pin
This function is available when PWM timer output is enabled.

PF6

Can be configured as a I/O port when SO2 and OCPA2 are not
used.
This function is available when UART2 data output is disabled.

OCPA0

PWM timer output pin
This function is available when PWM timer output is enabled.

PF7

Can be configured as a I/O port when OCPA0 and ATG are not
used.
This function is available when PWM timer output is disabled.

ATG

External trigger input pin for A/D converter
This pin is used for input when external trigger is selected to
cause A/D converter operation, and it is necessary to disable
output for other functions from this pin unless such output is
made intentionally.

72 to 75

75 to 78

AN0 to AN3

Analog input pins of A/D converter
This function is available when AIC register is set to specify
analog input mode.

Power supply pin (V

) for A/D converter

AVRH

Reference voltage input (high) for A/D converter
Make sure to turn on and off this pin with potential of AVRH or
more applied to V

/ AVRL

Power supply pin (V

) for A/D converter and reference voltage

input pin (low)

43,

46,

5 V power supply pin (V

) for digital circuit

Always two pins must be connected to the power supply
(connect to 3 V power supply when operating at 3 V).

Bypass capacitor pin for internal capacitor.
Also connect this pin to 3 V power supply when operating at
3 V.

15,
40,
65,

18,
43,
68,

Earth level (V

) for digital circuit

MB91101/MB91101A

DRAM CONTROL PIN

Pin name

Data bus 16-bit mode

Data bus 8-bit mode

Remarks

2CAS/1WR mode

1CAS/2WR mode

RAS0

Area 4 RAS

Correspondence of "L"
"H" to lower address 1
bit (A0) in data bus 16-
bit mode
"L": "0"
"H": "1"
CASL: CAS which A0

corresponds to
"0" area

CASH: CAS which A0

corresponds to
"1" area

WEL: WE which A0

corresponds to
"0" area

WEH: WE which A0

corresponds to
"1" area

RAS1

Area 5 RAS

CS0L

Area 4 CASL

Area 4 CAS

CS0H

Area 4 CASH

Area 4 WEL

Area 4 CAS

CS1L

Area 5 CASL

Area 5 CAS

CS1H

Area 5 CASH

Area 5 WEL

Area 5 CAS

CW0

Area 4 WE

Area 4 WEH

Area 4 WE

DW1

Area 5 WE

Area 5 WEH

Area 5 WE

MB91101/MB91101A

(Continued)

Type

Circuit

Remarks

· CMOS level output
· CMOS level

Hysteresis input
Without standby control

· CMOS level output
· TTL level input

With standby control

· CMOS level input/output

With standby control

· Large current drive

· CMOS level output

P-ch

N-ch

Digital input

Digital output

P-ch

N-ch

TTL

Standby control signal

Digital input

Digital output

P-ch

N-ch

Standby control signal

Digital input

Digital output

P-ch

N-ch

Digital output

MB91101/MB91101A

HANDLING DEVICES

Preventing Latchup

In CMOS ICs, applying voltage higher than V

or lower than V

to input/output pin or applying voltage over

rating across V

and V

may cause latchup.

This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the
device. Make sure to prevent the voltage from exceeding the maximum rating.

Take care that the analog power supply (AV

, AVR) and the analog input do not exceed the digital power

supply (V

) when the analog power supply turned on or off.

Treatment of Unused Pins

Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.

External Reset Input

It takes at least 5 machine cycle to input "L" level to the RST pin and to ensure inner reset operation properly.

Remarks for External Clock Operation

When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to
X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops
at "H" output in stop mode).

And can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than.

Open

MB91101

Using an external clock (normal)

Note: Can not be used stop mode (oscillation stop mode).

Using an external clock (can be used at 12.5 MHz and less than.)

(5 V power supply only)

· Using an external clock

MB91101/MB91101A

Power Supply Pins

When there are several V

and V

pins, each of them is equipotentially connected to its counterpart inside

of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions,
to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and
to observe the total output current standard, connect all V

and V

pins to the power supply or GND.

It is preferred to connect V

and V

of MB91101 to power supply with minimal impedance possible.

It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1

F between V

and V

at a position as close as possible to MB91101.

MB91101 has an internal regulator. When using with 5 V power supply, supply 5 V to V

5 pin and make sure

to connect about 0.1

F bypass capacitor to V

3 pin for regulator. And another 3 V power supply is needed

for the A/D convertor. When using with 3 V power supply, connect both V

5 pin and V

3 pin to the 3 V power

supply.

Crystal Oscillator Circuit

Noises around X0 and X1 pins may cause malfunctions of MB91101. In designing the PC board, layout X0,
X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible.

It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for
stable operation.

Turning-on Sequence of A/D Converter Power Supply and Analog Input

Make sure to turn on the digital power supply (V

) before turning on the A/D converter (AV

, AVRH) and

applying voltage to analog input (AN0 to AN3).

Make sure to turn off digital power supply after power supply to A/D converters and analog inputs have been
switched off. (There are no such limitations in turning on power supplies. Analog and digital power supplies
may be turned on simultaneously.) Make sure that AVRH never exceeds AV

when turning on/off power

supplies.

Treatment of N.C. Pins

Make sure to leave N.C. pins open.

· Connecting to a power supply

AVRH

5 V

GND

[Using with 5 V power supply]

AVRH

3 V

GND

[Using with 3 V power supply]

About
0.1

MB91101/MB91101A

Fluctuation of Power Supply Voltage

Warranty range for normal operation against fluctuation of power supply voltage V

is as given in rating.

However, sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. It is
recommended to make every effort to stabilize the power supply voltage to IC. It is also recommended that by
controlling power supply as a reference of stabilizing, V

ripple fluctuation (P-P value) at the commercial

frequency (50 Hz to 60 Hz) should be less than 10% of the standard V

value and the transient regulation

should be less than 0.1 V/ms at instantaneous deviation like turning off the power supply.

10. Mode Setting Pins (MD0 to MD2)

Connect mode setting pins (MD0 to MD2) directly to V

or V

Arrange each mode setting pin and V

or V

patterns on the printed circuit board as close as possible and

make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.

11. Internal DC Regulator

Internal DC regulator stops in stop mode. When the regulator stops owing to the increase of inner leakage
current (ICCH) in stop mode, malfunction caused by noise or any troubles about power supply in normal
operation, the internal 3 V power supply voltage may decrease less than the warranty range for normal operation.
So when using the internal regulator and stop mode with 5 V power supply, never fail to support externally so
that 3 V power supply voltage might not decrease. However, even in such a case, the internal regulator can be
restarted by inputting the reset procedure. (In this case, set the reset to "L" level within the oscillation stabilizing
waiting time.)

12. Turning on the Power Supply

When turning on the power supply, never fail to start from setting the RST pin to "L" level. And after the power
supply voltage goes to V

level, at least after ensuring the time for 5 machine cycle, then set to "H" level.

13. Pin Condition at Turning on the Power Supply

The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on
the power supply and then starting oscillation and then the operation of the internal regulator becomes stable.
So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5
MHz. Take care that the pin condition may be output condition at initial unstable condition.
(With the MB91101A, however, initalization can be achieved in less than about 42 ms after turning on the
internal power supply by maintaining the RST pin at "L" level.)

3.6 k

6.8 k

0.1

approx.

5 V

· Using STOP mode with 5 V power supply

MB91101/MB91101A

14. Source Oscillation Input at Turning on the Power Supply

At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing
waiting.

15. Hardware Stand-by at Turning on the Power Supply

When turning on the power supply with the HST pin being set to "L" level, the hardware doesn't stand by.
However the HST pin becomes available after the reset cancellation, the HST pin must once be back to "H" level.

16. Power on Reset

Make sure to make power on reset at turning on the power supply or returning on the power supply when the
power supply voltage is below the warranty range for normal operation.

MB91101/MB91101A

BLOCK DIAGRAM

AN0 to AN3
AV

/AVRL

AVRH

Bit search module

Instruction cache (1 Kbyte)

D-bus (32 bits)

I-bus (16 bits)

C-bus (32 bits)

R-bus (16 bits)

Clock control unit
(Watchdog timer)

Interrupt control unit

10-bit A/D converter

(4 ch.)

Reload timer (3 ch.)

Port

Bus converter (32 bits

16 bits)

DRAM controller

Port 0 to port B

UART (3 ch.)

(Baud rate timer)

Bus controller

DMA controller (DMAC)

(8 ch.)

Bus converter

(Harvard

Princeton)

RAM (2 Kbytes)

PWM timer (4 ch.)

FR CPU

X0
X1
RST
HST

DREQ0 to
DREQ2
DACK0 to
DACK2
EOP0 to
EOP2

D16 to D31
A00 to A24
RD
WR0, WR1
RDY
CLK
CS0 to CS5
BRQ
BGRNT

SI0 to SI2
SO0 to SO2
SC0 to SC2

OCPA0 to OCPA3
TRG0 to TRG3

INT0 to INT3
NMI

ATG

4
4

RAS0
RAS1
CS0L
CS0H
CS1L
CS1H
DW0
DW1

3
3

MD0 to MD2, P20 to P27, P60 to P67,
P80 to P82, P85, PA1 to PA6,
PB0 to PB7, PE0 to PE7, PF0 to PF7,
V

3, V

5, V

Other pins

Note: Pins are display for functions (Actually some pins are multiplexer).

When using REALOS, time control should be done by using external interrupt or inner timer.

MB91101/MB91101A

CPU CORE

Memory Space

The FR family has a logical address space of 4 Gbytes (2

bytes) and the CPU linearly accesses the memory

space.

· Direct addressing area

The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an
address can be specified in a direct operand of a code.

Direct areas consists of the following areas dependent on accessible data sizes.

Byte data access: 000

to 0FF

Half word data access: 000

to 1FF

Word data access: 000

to 3FF

· Memory space

I/O area

Access inhibited

External area

Direct addressing area

See "

I/O MAP"

0000 0000

0000 0400

0000 0800

0001 0000

FFFF FFFF

External ROM/external bus mode

Embedded RAM

0000 1800

0000 1000

Address

MB91101/MB91101A

Registers

The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose
registers on memory.

· Dedicated registers

Program counter (PC):

32-bit length, indicates the location of the instruction to be executed.

Program status (PS):

32-bit length, register for storing register pointer or condition codes

Table base register (TBR):

Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap)
processing.

Return pointer (RP):

Holds address to resume operation after returning from a subroutine.

System stack pointer (SSP): Indicates system stack space.
User's stack pointer (USP): Indicates user's stack space.
Multiplication/division result register (MDH/MDL): 32-bit length, register for multiplication/division

· Program status (PS)

The PS register is for holding program status and consists of a condition code register (CCR), a system condition
code register (SCR) and a interrupt level mask register (ILM).

TBR

SSP

USP

MDH

MDL

Initial value

Program counter

Program status

Table base register

Return pointer

System stack pointer

User's stack pointer

Multiplication/division result register

XXXX XXXX

Indeterminate

000F

FC00

XXXX XXXX

Indeterminate

0000

XXXX XXXX

Indeterminate

XXXX XXXX

Indeterminate

XXXX XXXX

Indeterminate

32 bits

ILM4 ILM3 ILM2 ILM1

ILM0

31 to 21 20

ILM

SCR

CCR

MB91101/MB91101A

· Condition code register (CCR)

S-flag:

Specifies a stack pointer used as R15.

I-flag:

Controls user interrupt request enable/disable.

N-flag:

Indicates sign bit when division result is assumed to be in the 2's complement format.

Z-flag:

Indicates whether or not the result of division was "0".

V-flag:

Assumes the operand used in calculation in the 2's complement format and indicates whether
or not overflow has occurred.

C-flag:

Indicates if a carry or borrow from the MSB has occurred.

· System condition code register (SCR)

T-flag:

Specifies whether or not to enable step trace trap.

· Interrupt level mask register (ILM)

ILM4 to ILM0: Register for holding interrupt level mask value. The value held by this register is used as a

level mask. When an interrupt request issued to the CPU is higher than the level held by ILM,
the interrupt request is accepted.

ILM4

ILM3

ILM2

ILM1

ILM0

Interrupt level

High-low

High

:
:

Low

MB91101/MB91101A

GENERAL-PURPOSE REGISTERS

R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator
and a memory access pointer (field for indicating address).

Of the above 16 registers, following registers have special functions. To support the special functions, part of
the instruction set has been sophisticated to have enhanced functions.

R13: Virtual accumulator (AC)
R14: Frame pointer (FP)
R15: Stack pointer (SP)

Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000

(SSP value).

· Register bank structure

R12

R13

R14

R15

AC (accumulator)

FP (frame pointer)

SP (stack pointer)

32 bits

:
:

Initial value

XXXX XXXX

:
:
:
:
:
:
:
:
:
:
:

XXXX XXXX

0 0 0 0 0 0 0 0

MB91101/MB91101A

SETTING MODE

Pin

· Mode setting pins and modes

* : MB91101 does not support single-chip mode.

Registers

· Mode setting registers (MODR) and modes

· Bus mode setting bits and functions

Note: Because of without internal ROM, MB91101 allows "10

" setting value only.

Mode setting

pins

Mode name

Reset vector

access area

External data

bus width

Bus mode

MD2 MD1 MD0

External vector mode 0

External

8 bits

External ROM/external bus
mode

External vector mode 1

External

16 bits

Inhibited

Internal vector mode

Internal

(Mode register)

Single-chip mode*

Inhibited

Functions

Note

Single-chip mode

Internal ROM/external bus mode

External ROM/external bus mode

Inhibited

Address

0000 07FF

Bus mode setting bit

W : Write only
X : Indeterminate
* : Always write "0" except for M1 and M0.

Initial value

XXXX XXXX

Access

MB91101/MB91101A

I/O MAP

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

0000

(Vacancy)

0001

PDR2

Port 2 data register

R/W

X X X X X X X X

0002

0004

(Vacancy)

0005

PDR6

Port 6 data register

R/W

X X X X X X X X

0006

(Vacancy)

0007

0008

PDRB

Port B data register

R/W

X X X X X X X X

0009

PDRA

Port A data register

R/W

X X X X X X

000A

(Vacancy)

000B

PDR8

Port 8 data register

R/W

X X X X

000C

0011

(Vacancy)

0012

PDRE

Port E data register

R/W

X X X X X X X X

0013

PDRF

Port F data register

R/W

X X X X X X X X

0014

001B

(Vacancy)

001C

SSR0

Serial status register 0

R/W

0 0 0 0 1 0 0

001D

SIDR0/SODR0

Serial input register 0/serial output register 0

R/W

X X X X X X X X

001E

SCR0

Serial control register 0

R/W

0 0 0 0 0 1 0 0

001F

SMR0

Serial mode register 0

R/W

0 0 0 0 0

0020

SSR1

Serial status register 1

R/W

0 0 0 0 1 0 0

0021

SIDR1/SODR1

Serial input register 1/serial output register 1

R/W

X X X X X X X X

0022

SCR1

Serial control register 1

R/W

0 0 0 0 0 1 0 0

0023

SMR2

Serial mode register 1

R/W

0 0 0 0 0

0024

SSR2

Serial status register 2

R/W

0 0 0 0 1 0 0

0025

SIDR2/SODR2

Serial input register 2/serial output register 2

R/W

X X X X X X X X

0026

SCR2

Serial control register 2

R/W

0 0 0 0 0 1 0 0

0027

SMR2

Serial mode register 2

R/W

0 0 0 0 0

MB91101/MB91101A

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

0028

TMRLR0

16-bit reload register ch. 0

X X X X X X X X

0029

X X X X X X X X

002A

TMR0

16-bit timer register ch. 0

X X X X X X X X

002B

X X X X X X X X

002C

(Vacancy)

002D

002E

TMCSR0

16-bit reload timer control status register
ch. 0

R/W

0 0 0 0

002F

0 0 0 0 0 0 0 0

0030

TMRLR1

16-bit reload register ch. 1

X X X X X X X X

0031

X X X X X X X X

0032

TMR1

16-bit timer register ch. 1

X X X X X X X X

0033

X X X X X X X X

0034

(Vacancy)

0035

0036

TMCSR1

16-bit reload timer control status register
ch. 1

R/W

0 0 0 0

0037

0 0 0 0 0 0 0 0

0038

ADCR

A/D converter data register

X X

0039

X X X X X X X X

003A

ADCS

A/D converter control status register

R/W

0 0 0 0 0 0 0 0

003B

0 0 0 0 0 0 0 0

003C

TMRLR2

16-bit reload register ch. 2

X X X X X X X X

003D

X X X X X X X X

003E

TMR2

16-bit timer register ch. 2

X X X X X X X X

003F

X X X X X X X X

0040

(Vacancy)

0041

0042

TMCSR2

16-bit reload timer control status register
ch. 2

R/W

0 0 0 0

0043

0 0 0 0 0 0 0 0

0044

0077

(Vacancy)

MB91101/MB91101A

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

0078

UTIM0/UTIMR0

U-TIMER register ch. 0/reload register ch. 0

R/W

0 0 0 0 0 0 0 0

0079

0 0 0 0 0 0 0 0

007A

(Vacancy)

007B

UTIMC0

U-TIMER control register ch. 0

R/W

0 0 0 0 0 1

007C

UTIM1/UTIMR1

U-TIMER register ch. 1/reload register ch. 1

R/W

0 0 0 0 0 0 0 0

007D

0 0 0 0 0 0 0 0

007E

(Vacancy)

007F

UTIMC1

U-TIMER control register ch. 1

R/W

0 0 0 0 0 1

0080

UTIM2/UTIMR2

U-TIMER register ch. 2/reload register ch. 0

R/W

0 0 0 0 0 0 0 0

0081

0 0 0 0 0 0 0 0

0082

(Vacancy)

0083

UTIMC2

U-TIMER control register ch. 2

R/W

0 0 0 0 0 1

0084

0093

(Vacancy)

0094

EIRR

External interrupt cause register

R/W

0 0 0 0 0 0 0 0

0095

ENIR

Interrupt enable register

R/W

0 0 0 0 0 0 0 0

0096

0098

(Vacancy)

0099

ELVR

External interrupt request level setting
register

R/W

0 0 0 0 0 0 0 0

009A

00D1

(Vacancy)

00D2

DDRE

Port E data direction register

0 0 0 0 0 0 0 0

00D3

DDRF

Port F data direction register

0 0 0 0 0 0 0 0

00D4

00DB

(Vacancy)

00DC

GCN1

General control register 1

R/W

0 0 1 1 0 0 1 0

00DD

0 0 0 1 0 0 0 0

00DE

(Vacancy)

00DF

GCN2

General control register 2

R/W

0 0 0 0 0 0 0 0

MB91101/MB91101A

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

00E0

PTMR0

Ch. 0 timer register

1 1 1 1 1 1 1 1

00E1

1 1 1 1 1 1 1 1

00E2

PCSR0

Ch. 0 cycle setting register

X X X X X X X X

00E3

X X X X X X X X

00E4

PDUT0

Ch. 0 duty setting register

X X X X X X X X

00E5

X X X X X X X X

00E6

PCNH0

Ch. 0 control status register H

R/W

0 0 0 0 0 0 0

00E7

PCNL0

Ch. 0 control status register L

R/W

0 0 0 0 0 0 0 0

00E8

PTMR1

Ch. 1 timer register

1 1 1 1 1 1 1 1

00E9

1 1 1 1 1 1 1 1

00EA

PCSR1

Ch. 1 cycle setting register

X X X X X X X X

00EB

X X X X X X X X

00EC

PDUT1

Ch. 1 duty setting register

X X X X X X X X

00ED

X X X X X X X X

00EE

PCNH1

Ch. 1 control status register H

R/W

0 0 0 0 0 0 0

00EF

PCNL1

Ch. 1 control status register L

R/W

0 0 0 0 0 0 0 0

00F0

PTMR2

Ch. 2 timer register

1 1 1 1 1 1 1 1

00F1

1 1 1 1 1 1 1 1

00F2

PCSR2

Ch. 2 cycle setting register

X X X X X X X X

00F3

X X X X X X X X

00F4

PDUT2

Ch. 2 duty setting register

X X X X X X X X

00F5

X X X X X X X X

00F6

PCNH2

Ch. 2 control status register H

R/W

0 0 0 0 0 0 0

00F7

PCNL2

Ch. 2 control status register L

R/W

0 0 0 0 0 0 0 0

00F8

PTMR3

Ch. 3 timer register

1 1 1 1 1 1 1 1

00F9

1 1 1 1 1 1 1 1

00FA

PCSR3

Ch. 3 cycle setting register

X X X X X X X X

00FB

X X X X X X X X

00FC

PDUT3

Ch. 3 duty setting register

X X X X X X X X

00FD

X X X X X X X X

00FE

PCNH3

Ch. 3 control status register H

R/W

0 0 0 0 0 0 0

00FF

PCNL3

Ch. 3 control status register L

R/W

0 0 0 0 0 0 0 0

MB91101/MB91101A

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

0100

01FF

(Vacancy)

0200

DPDP

DMAC parameter descriptor pointer

R/W

X X X X X X X X

0201

X X X X X X X X

0202

X X X X X X X X

0203

X 0 0 0 0 0 0 0

0204

DACSR

DMAC control status register

R/W

0 0 0 0 0 0 0 0

0205

0 0 0 0 0 0 0 0

0206

0 0 0 0 0 0 0 0

0207

0 0 0 0 0 0 0 0

0208

DATCR

DMAC pin control register

R/W

X X X X X X X X

0209

X X X X 0 0 0 0

020A

X X X X 0 0 0 0

020B

X X X X 0 0 0 0

020C

03E3

(Vacancy)

03E4

ICHCR

Instruction cache control register

R/W

03E5

03E6

03E7

0 0 0 0 0 0

03E8

03EF

(Vacancy)

03F0

BSD0

Bit search module 0-detection data register

X X X X X X X X

03F1

X X X X X X X X

03F2

X X X X X X X X

03F3

X X X X X X X X

03F4

BSD1

Bit search module 1-detection data register

R/W

X X X X X X X X

03F5

X X X X X X X X

03F6

X X X X X X X X

03F7

X X X X X X X X

MB91101/MB91101A

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

03F8

BSDC

Bit search module transition-detection data
register

X X X X X X X X

03F9

X X X X X X X X

03FA

X X X X X X X X

03FB

X X X X X X X X

03FC

BSRR

Bit search module detection result register

X X X X X X X X

03FD

X X X X X X X X

03FE

X X X X X X X X

03FF

X X X X X X X X

0400

ICR00

Interrupt control register 0

R/W

1 1 1 1 1

0401

ICR01

Interrupt control register 1

R/W

1 1 1 1 1

0402

ICR02

Interrupt control register 2

R/W

1 1 1 1 1

0403

ICR03

Interrupt control register 3

R/W

1 1 1 1 1

0404

ICR04

Interrupt control register 4

R/W

1 1 1 1 1

0405

ICR05

Interrupt control register 5

R/W

1 1 1 1 1

0406

ICR06

Interrupt control register 6

R/W

1 1 1 1 1

0407

ICR07

Interrupt control register 7

R/W

1 1 1 1 1

0408

ICR08

Interrupt control register 8

R/W

1 1 1 1 1

0409

ICR09

Interrupt control register 9

R/W

1 1 1 1 1

040A

ICR10

Interrupt control register 10

R/W

1 1 1 1 1

040B

ICR11

Interrupt control register 11

R/W

1 1 1 1 1

040C

ICR12

Interrupt control register 12

R/W

1 1 1 1 1

040D

ICR13

Interrupt control register 13

R/W

1 1 1 1 1

040E

ICR14

Interrupt control register 14

R/W

1 1 1 1 1

040F

ICR15

Interrupt control register 15

R/W

1 1 1 1 1

0410

ICR16

Interrupt control register 16

R/W

1 1 1 1 1

0411

ICR17

Interrupt control register 17

R/W

1 1 1 1 1

0412

ICR18

Interrupt control register 18

R/W

1 1 1 1 1

0413

ICR19

Interrupt control register 19

R/W

1 1 1 1 1

0414

ICR20

Interrupt control register 20

R/W

1 1 1 1 1

0415

ICR21

Interrupt control register 21

R/W

1 1 1 1 1

0416

ICR22

Interrupt control register 22

R/W

1 1 1 1 1

MB91101/MB91101A

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

0417

ICR23

Interrupt control register 23

R/W

1 1 1 1 1

0418

ICR24

Interrupt control register 24

R/W

1 1 1 1 1

0419

ICR25

Interrupt control register 25

R/W

1 1 1 1 1

041A

ICR26

Interrupt control register 26

R/W

1 1 1 1 1

041B

ICR27

Interrupt control register 27

R/W

1 1 1 1 1

041C

ICR28

Interrupt control register 28

R/W

1 1 1 1 1

041D

ICR29

Interrupt control register 29

R/W

1 1 1 1 1

041E

ICR30

Interrupt control register 30

R/W

1 1 1 1 1

041F

ICR31

Interrupt control register 31

R/W

1 1 1 1 1

042F

ICR47

Interrupt control register 47

R/W

1 1 1 1 1

0430

DICR

Delayed interrupt control register

R/W

0431

HRCL

Hold request cancel request level setting
register

R/W

1 1 1 1 1

0432

047F

(Vacancy)

0480

RSRR/WTCR

Reset cause register/
watchdog peripheral control register

R/W

1X X X X 0 0

0481

STCR

Standby control register

R/W

0 0 0 1 1 1

0482

PDRR

DMA controller request squelch register

R/W

0 0 0 0

0483

CTBR

Timebase timer clear register

X X X X X X X X

0484

GCR

Gear control register

R/W

1 1 0 0 1 1 1

0485

WPR

Watchdog reset occurrence postpone
register

X X X X X X X X

0486

(Vacancy)

0487

0488

PCTR

PLL control register

R/W

0 0 0

0489

0600

(Vacancy)

0601

DDR2

Port 2 data direction register

0 0 0 0 0 0 0 0

0602

0604

(Vacancy)

0605

DDR6

Port 6 data direction register

0 0 0 0 0 0 0 0

0606

(Vacancy)

0607

MB91101/MB91101A

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

0608

DDRB

Port B data direction register

0 0 0 0 0 0 0 0

0609

DDRA

Port A data direction register

0 0 0 0 0 0

060A

(Vacancy)

060B

DDR8

Port 8 data direction register

0 0 0 0

060C

ASR1

Area select register 1

0 0 0 0 0 0 0 0

060D

0 0 0 0 0 0 0 1

060E

AMR1

Area mask register 1

0 0 0 0 0 0 0 0

060F

0 0 0 0 0 0 0 0

0610

ASR2

Area select register 2

0 0 0 0 0 0 0 0

0611

0 0 0 0 0 0 1 0

0612

AMR2

Area mask register 2

0 0 0 0 0 0 0 0

0613

0 0 0 0 0 0 0 0

0614

ASR3

Area select register 3

0 0 0 0 0 0 0 0

0615

0 0 0 0 0 0 1 1

0616

AMR3

Area mask register 3

0 0 0 0 0 0 0 0

0617

0 0 0 0 0 0 0 0

0618

ASR4

Area select register 4

0 0 0 0 0 0 0 0

0619

0 0 0 0 0 1 0 0

061A

AMR4

Area mask register 4

0 0 0 0 0 0 0 0

061B

0 0 0 0 0 0 0 0

061C

ASR5

Area select register 5

0 0 0 0 0 0 0 0

061D

0 0 0 0 0 1 0 1

061E

AMR5

Area mask register 5

0 0 0 0 0 0 0 0

061F

0 0 0 0 0 0 0 0

0620

AMD0

Area mode register 0

R/W

0 0 1 1 1

0621

AMD1

Area mode register 1

R/W

0 0 0 0 0 0

0622

AMD32

Area mode register 32

R/W

0 0 0 0 0 0 0 0

0623

AMD4

Area mode register 4

R/W

0 0 0 0 0 0

0624

AMD5

Area mode register 5

R/W

0 0 0 0 0 0

0625

DSCR

DRAM signal control register

0 0 0 0 0 0 0 0

0626

RFCR

Refresh control register

R/W

X X X X X X

0627

0 0 0 0 0

MB91101/MB91101A

(Continued)

Note: Do not use (vacancy).

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

0628

EPCR0

External pin control register 0

1 1 0 0

0629

1 1 1 1 1 1 1

062A

(Vacancy)

062B

EPCR1

External pin control register 1

1 1 1 1 1 1 1 1

062C

DMCR4

DRAM control register 4

R/W

0 0 0 0 0 0 0 0

062D

0 0 0 0 0 0 0

062E

DMCR5

DRAM control register 5

R/W

0 0 0 0 0 0 0 0

062F

0 0 0 0 0 0 0

0630

07FD

(Vacancy)

07FE

LER

Little endian register

0 0 0

07FF

MODR

Mode register

X X X X X X X X

MB91101/MB91101A

INTERRUPT CAUSES, INTERRUPT VECTORS
AND INTERRUPT CONTROL REGISTER ALLOCATIONS

(Continued)

Interrupt causes

Interrupt number

Interrupt level

TBR default

address

Decimal

Hexadecimal

Register

Offset

Reset

3FC

000FFFFC

Reserved for system

3F8

000FFFF8

Reserved for system

3F4

000FFFF4

Reserved for system

3F0

000FFFF0

Reserved for system

3EC

000FFFEC

Reserved for system

3E8

000FFFE8

Reserved for system

3E4

000FFFE4

Reserved for system

3E0

000FFFE0

Reserved for system

3DC

000FFFDC

Reserved for system

3D8

000FFFD8

Reserved for system

3D4

000FFFD4

Reserved for system

3D0

000FFFD0

Reserved for system

3CC

000FFFCC

Reserved for system

3C8

000FFFC8

Exception for undefined instruction

3C4

000FFFC4

NMI request

fixed

3C0

000FFFC0

External interrupt 0

ICR00

3BC

000FFFBC

External interrupt 1

ICR01

3B8

000FFFB8

External interrupt 2

ICR02

3B4

000FFFB4

External interrupt 3

ICR03

3B0

000FFFB0

UART0 receive complete

ICR04

3AC

000FFFAC

UART1 receive complete

ICR05

3A8

000FFFA8

UART2 receive complete

ICR06

3A4

000FFFA4

UART0 transmit complete

ICR07

3A0

000FFFA0

UART1 transmit complete

ICR08

39C

000FFF9C

UART2 transmit complete

ICR09

398

000FFF98

DMAC0 (complete, error)

ICR10

394

000FFF94

DMAC1 (complete, error)

ICR11

390

000FFF90

DMAC2 (complete, error)

ICR12

38C

000FFF8C

DMAC3 (complete, error)

ICR13

388

000FFF88

DMAC4 (complete, error)

ICR14

384

000FFF84

DMAC5 (complete, error)

ICR15

380

000FFF80

MB91101/MB91101A

(Continued)

Interrupt causes

Interrupt number

Interrupt level

TBR default

address

Decimal

Hexadecimal

Register

Offset

DMAC6 (complete, error)

ICR16

37C

000FFF7C

DMAC7 (complete, error)

ICR17

378

000FFF78

A/D converter (successive
approximation conversion type)

ICR18

374

000FFF74

16-bit reload timer 0

ICR19

370

000FFF70

16-bit reload timer 1

ICR20

36C

000FFF6C

16-bit reload timer 2

ICR21

368

000FFF68

PWM 0

ICR22

364

000FFF64

PWM 1

ICR23

360

000FFF60

PWM 2

ICR24

35C

000FFF5C

PWM 3

ICR25

358

000FFF58

U-TIMER 0

ICR26

354

000FFF54

U-TIMER 1

ICR27

350

000FFF50

U-TIMER 2

ICR28

34C

000FFF4C

Reserved for system

ICR29

348

000FFF48

Reserved for system

ICR30

344

000FFF44

Reserved for system

ICR31

340

000FFF40

Reserved for system

ICR32

33C

000FFF3C

Reserved for system

ICR33

338

000FFF38

Reserved for system

ICR34

334

000FFF34

Reserved for system

ICR35

330

000FFF30

Reserved for system

ICR36

32C

000FFF2C

Reserved for system

ICR37

328

000FFF28

Reserved for system

ICR38

324

000FFF24

Reserved for system

ICR39

320

000FFF20

Reserved for system

ICR40

31C

000FFF1C

Reserved for system

ICR41

318

000FFF18

Reserved for system

ICR42

314

000FFF14

Reserved for system

ICR43

310

000FFF10

Reserved for system

ICR44

30C

000FFF0C

Reserved for system

ICR45

308

000FFF08

Reserved for system

ICR46

304

000FFF04

Delayed interrupt cause bit

ICR47

300

000FFF00

MB91101/MB91101A

PERIPHERAL RESOURCES

I/O Ports

There are 2 types of I/O port register structure; port data register (PDR0 to PDRF) and data direction register
(DDR0 to DDRF), where bits PDR0 to PDRF and bits DDR0 to DDRF corresponds respectively. Each bit on
the register corresponds to an external pin. In port registers input/output register of the port configures input/
output function of the port, while corresponding bit (pin) configures input/output function in data direction
registers. Bit "0" specifies input and "1" specifies output.

· For input (DDR = "0") setting;

PDR reading operation: reads level of corresponding external pin.
PDR writing operation: writes set value to PDR.

· For output (DDR = "1") setting;

PDR reading operation: reads PDR value.
PDR writing operation: outputs PDR value to corresponding external pin.

· Block diagram

PDR

DDR

(Port data register)

(Data direction register)

Resource output enable

Resource output

PDR read

Resource input

Data bus

MB91101/MB91101A

( )
W

· Port data register

· Data direction register

bit 7

bit 0

000001

000005

00000B

000009

000008

000012

000013

X X X X X X X X

- - X - - X X X

- X X X X X X -

X X X X X X X X

Address

Initial value

: Access
: Readable and writable
: Indeterminate

(R/W)

PDR2

PDR6

PDR8

PDRA

PDRB

PDRE

PDRF

( )

R/W

bit 7

bit 0

000601

000605

00060B

000609

000608

0000D2

0000D3

0 0 0 0 0 0 0 0

- - 0 - - 0 0 0

- 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

Address

Initial value

: Access
: Write only
: Unused

(W)

DDR2

DDR6

DDR8

DDRA

DDRB

DDRE

DDRF

MB91101/MB91101A

DMA Controller (DMAC)

The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)
transfer.

DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to
enhanced performance of the system.

· 8 channels
· Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer
· Transfer all through the area
· Max. 65536 of transfer cycles
· Interrupt function right after the transfer
· Selectable for address transfer increase/decrease by the software
· External transfer request input pin, external transfer request accept output pin, external transfer complete

output pin three pins for each

· Block diagram

Sequencer

Edge/level

detection circuit

Inner resource
Transfer request

DREQ0 to DREQ2

DACK0 to DACK2

EOP0 to EOP2

Interrupt request

Data buffer

Switcher

DPDP

DACSR

DATCR

Data bus

Mode

BLK DEC

INC / DEC

BLK

DMACT

SADR

DADR

MB91101/MB91101A

· Registers (DMAC internal registers)

· Registers (DMA descriptor)

bit 31

bit 0

00000200

00000201

00000202

00000203

00000204

00000205

00000206

00000207

00000208

00000209

0000020A

0000020B

X X X X X X X X

X 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

X X X X X X X X

X X X X 0 0 0 0

Address

Initial value

: Access
: Readable and writable
: Indeterminate

DPDP

( )

R/W

bit 16

DACSR

DATCR

(R/W)

bit 31

bit 0

DPDP + 0

DPDP + 0C

DPDP + 54

DMA

ch.0

Descriptor

DMA

ch.1

Descriptor

DMA

ch.7

Descriptor

Address

MB91101/MB91101A

UART

The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK
synchronous communication, and it has the following features.

The MB91101 consists of 3 channels of UART.

· Full double double buffer
· Both a synchronous (start-stop system) communication and CLK synchronous communication are available.
· Supporting multi-processor mode
· Perfect programmable baud rate

Any baud rate can be set by internal timer (refer to section "4. U-TIMER").

· Any baud rate can be set by external clock.
· Error checking function (parity, framing and overrun)
· Transfer signal: NRZ code
· Enable DMA transfer/start by interrupt.

MB91101/MB91101A

· Block diagram

Control signals

From external clock

SI
(receive data)

Clock select

circuit

Receive interrupt
(to CPU)

Transmit interrupt
(to CPU)

Receive control circuit

Start bit detect

circuit

Receive bit counter

Receive parity

counter

Transmit control circuit

Transmit start

circuit

Transmit bit counter

Transmit parity

counter

Receive status

judge circuit

Receive shifter

Receive
complete

Transmit shifter

Transmit
start

Receive error
generate signal
for DMA
(to DMAC)

SIDR

SODR

R-bus

SMR
register

MD1
MD0

CS0

SCKE
SOE

SCR
register

SSR
register

Control signals

Transmit clock

Receive clock

SO (transmit data)

PEN
P
SBL
CL
A/D
REC
RXE
TXE

PE
ORE
FRE
RDRF
TDRE

RIE
TIE

SC (clock)

From U-TIMER

MB91101/MB91101A

· Register configuration

bit 15

bit 0

0000001E

00000022

00000026

0000001F

00000023

00000027

0000001C

00000020

00000024

0000001D

00000021

00000002

(R/W)

Address

Initial value

SCR0

SCR1

SCR2

SSR0

SSR1

SSR2

SMR0

SMR1

SMR2

SIDR0/SODR0

SIDR1/SIDR1

SIDR2/SIDR2

bit 8

0 0 0 0 0 1 0 0

0 0 - - 0 - 0 0

0 0 0 0 1 - 0 0

X X X X X X X X

: Access
: Readable and writable
: Unused
: Indeterminate

( )

R/W

MB91101/MB91101A

U-TIMER (16-bit Timer for UART Baud Rate Generation)

The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and
reload value of U-TIMER allows flexible setting of baud rate.

The U-TIMER operates as an interval timer by using interrupt issued on counter underflow.

The MB91101 has 3 channel U-TIMER embedded on the chip. An interval of up to 2

can be counted.

· Block diagram

· Register configuration

UTIMR (reload register)

bit 15

bit 0

UTIM ( U-TIMER register)

bit 15

bit 0

Clock

Underflow

To UART

(Peripheral clock)

Control

f.f.

Load

bit 15

bit 0

00000078

00000079

0000007C

0000007D

00000080

00000081

0000007B

0000007F

00000083

(R/W)

Address

Initial value

0 0 0 0 0 0 0 0

0 - - 0 0 0 0 1

UTIM0/UTIMR0

UTIM1/UTIMR1

UTIM2/UTIMR2

UTIMC0

UTIMC1

UTIMC2

: Access
: Readable and writable
: Unused

( )

R/W

MB91101/MB91101A

PWM Timer

The PWM timer can output high accurate PWM waves efficiently.

MB91101 has inner 4-channel PWM timers, and has the following features.

· Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for scyde setting, a 16-

bit compare resister with a buffer for duty setting, and a pin controller.

· The count clock of a 16-bit down counter can be selected from the following four inner clocks.

Inner clock

/4,

/16,

/64

· The counter value can be initialized "FFFF

" by the resetting or the counter borrow.

· PWM output (each channel)
· Resister description

· Block diagram (general construction)

16-bit reload timer

ch.0

16-bit reload timer

ch.1

General control

TRG input

PWM timer ch.0

TRG input

PWM timer ch.1

TRG input

PWM timer ch.2

TRG input

PWM timer ch.3

General control

(cause selection)

External TRG0 to TRG3

PWM0

PWM1

PWM2

PWM3

MB91101/MB91101A

· Register configuration

bit 15

bit 0

000000DC

000000DD

000000DF

000000E0

000000E1

000000E2

000000E3

000000E4

000000E5

000000E6

000000E7

000000E8

000000E9

000000EA

000000EB

000000EC

000000ED

000000EE

000000EF

000000F0

000000F1

000000F2

000000F3

000000F4

000000F5

000000F6

000000F7

000000F8

000000F9

000000FA

000000FB

000000FC

000000FD

000000FE

000000FF

(R/W)

(R)

(W)

(R/W)

(R)

(W)

(R/W)

(R)

(W)

(R/W)

(R)

(W)

(R/W)

Address

Initial value

bit 8

0 0 1 1 0 0 1 0

0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

X X X X X X X X

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

X X X X X X X X

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

X X X X X X X X

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

X X X X X X X X

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

: Access
: Readable and writable
: Read only
: Write only
: Unused
: Indeterminate

( )

R/W

PCNH0

PCNL0

GCN2

PCNH1

PCNL1

PCNH2

PCNL2

PCNH3

PCNL3

GCN1

PTMR0

PCSR0

PDUT0

PTMR1

PCSR1

PDUT1

PTMR2

PCSR2

PDUT2

PTMR3

PCSR3

PDUT3

MB91101/MB91101A

16-bit Reload Timer

The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating
internal count clock and control registers.

Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock).

The DMA transfer can be started by the interruption.

The MB91101 consists of 3 channels of the 16-bit reload timer.

· Block diagram

16-bit reload register

16-bit down counter UF

Clock selector

Reload

RELD

OUTE

OUTL

INTE

CNTE

TRG

OUT
CTL.

CSL1

CSL0

MOD2

MOD1

MOD0

IN CTL.

Internal clock

Prescaler
clear

EXCK

GATE

Retrigger

IRQ

PWM (ch.0, ch.1)
A/D (ch.2)

R-bus

MB91101/MB91101A

· Register configuration

bit 15

bit 0

0000002E

0000002F

00000036

00000037

00000042

00000043

0000002A

0000002B

00000032

00000033

0000003E

0000003F

00000028

00000029

00000030

00000031

0000003C

0000003D

- - - - 0 0 0 0

0 0 0 0 0 0 0 0

- - - -

0 0 0 0

0 0 0 0 0 0 0 0

- - - - 0 0 0 0

0 0 0 0 0 0 0 0

X X X X X X X X

Address

Initial value

: Access
: Readable and writable
: Read only
: Write only
: Unused
: Indeterminate

(R/W)

(R)

(W)

TMCSR0

TMCSR1

TMCSR2

TMR0

TMR1

TMR2

TMRLR0

TMRLR1

TMRLR2

( )

R/W

MB91101/MB91101A

Bit Search Module

The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and
returns locations of the transitions.

· Block diagram

· Register configuration

Input latch

Single-detection data recovery

Bit search circuit

Search result

Address
decoder

Detection

mode

D-bus

000003F0

000003F1

000003F2

000003F3

000003F4

000003F5

000003F6

000003F7

000003F8

000003F9

000003FA

000003FB

000003FC

000003FE

000003FD

000003FF

bit 31

bit 0

XXXXXXXX

Address

Initial value

(W)

bit 16

: Access
: Readable and writable
: Read only
: Write only
: Indeterminate

( )

R/W

BSD0

BSD1

BSDC

BSRR

MB91101/MB91101A

10-bit A/D Converter (Successive Approximation Conversion Type)

The A/D converter is the module which converts an analog input voltage to a digital value, and it has following
features.

· Minimum converting time: 5.6

s/ch. (system clock: 25 MHz)

· Inner sample and hold circuit
· Resolution: 10 bits
· Analog input can be selected from 4 channels by program.

Single convert mode: 1 channel is selected and converted.
Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable.
Continuous convert mode: Converting the specified channel repeatedly.
Stop convert mode: After converting one channel then stop and wait till next activation synchronising at

the beginning of conversion can be peformed.

· DMA transfer operation is available by interruption.
· Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer

(rising edge).

· Block diagram

Successive approximation

Internal voltage generator

AVR

MPX

Comparator

AN0

AN1

AN2

AN3

Sample & hold circuit

Data register (ADCR)

A/D control register (ADCS)

Prescaler

Operating clock

ATG

Trigger start

TIM0
(internal connection)
(16-bit reload timer ch.2)

Timer start

(Peripheral clock)

R-bus

Input circuit

Decoder

MB91101/MB91101A

Interrupt Controller

The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.

· Block diagram

R-bus

LEVEL0*

INT0*

Priority judgment

NMI

NMI processing

RI00

RI47

(DLYIRQ)

·
·
·

·
·

DLYI*

Level judgment

ICR00

ICR47

Vector judgment

Level

vector

generation

HLDREQ

cancel

request

LEVEL4 to

HLDCAN*

VCT0*

VCT5 to

*1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section "11. Delayed Interrupt

Module" for detail).

*2: INT0 is a wake-up signal to clock control block in the sleep or stop status.

*3: HLDCAN is a bus release request signal for bus masters other than CPU.

*4: LEVEL5 to LEVEL0 are interrupt level outputs.

*5: VCT5 to VCT0 are interrupt vector outputs.

MB91101/MB91101A

· Register configuration

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

bit 7

bit 0

00000400

00000401

00000402

00000403

00000404

00000405

00000406

00000407

00000408

00000409

0000040A

0000040B

0000040C

0000040D

0000040E

0000040F

00000410

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

Address

Initial value

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR47

HRCL

DICR

bit 7

bit 0

00000411

00000412

00000413

00000414

00000415

00000416

00000417

00000418

00000419

0000041A

0000041B

0000041C

0000041D

0000041E

0000041F

0000042F

00000431

00000430

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - - - - - 0

(R/W)

Address

Initial value

: Access
: Redable and writable
: Unused

( )

R/W

MB91101/MB91101A

10. External Interrupt/NMI Control Block

The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0
to INT3 pins.

Detecting levels can be selected from "H", "L", rising edge and falling edge (not for NMI pin).

· Block diagram

· Register configuration

Interrupt enable register

Interrupt cause register

Request level setting register

Gate

Cause F/F

Edge detection circuit

Interrupt

request

INT0 to INT3
NMI

R-bus

bit 15

bit 0

00000000

Address

Initial value

ENIR

ELVR

(R/W)

bit 8

EIRR

00000095

00000094

00000099

: Access
: Redable and writable

( )

R/W

MB91101/MB91101A

12. Clock Generation (Low-power consumption mechanism)

The clock control block is a module which undertakes the following functions.

· CPU clock generation (including gear function)
· Peripheral clock generation (including gear function)
· Reset generation and cause hold
· Standby function (including hardware standby)
· DMA request prohibit
· PLL (multiplier circuit) embedded

· Block diagram

Gear control register (GCR)

[Gear control block]

PCTR register

CPU gear

Peripheral

gear

Oscillator

circuit

X0
X1

1/2

PLL

Internal clock

generation

circuit

CPU clock

Internal bus clock

External bus clock
Peripheral
DMA clock
Internal
peripheral clock

[Stop/sleep control block]

Internal
interrupt request
Internal reset

Standby control
register (STCR)

STOP state

SLEEP state

CPU hold request

Internal reset

Reset

generation

F/F

CPU hold enable

HST pin

DMA
request

Power on sel

RST pin

DMA request prohibit

[DMA prohibit circuit]

Reset cause register (RSRR)

Timebase timer

Count clock

Watchdog reset

postpone register

[Watchdog control block]

Timebase timer clear

Watchdog reset generation

postpone register (WPR)

R-bus

Selection

circuit

[Reset cause circuit]

Status

transition

control circuit

MB91101/MB91101A

13. External Bus Interface

The external bus interface controls the interface between the device and the external memory and also the
external I/O, and has the following features.

· 25-bit (32 Mbytes) address output
· 6 independent banks owing to the chip select function.

Can be set to anywhere on the logical address space for minimum unit 64 Kbytes.
Total 32 Mbytes

6 area setting is available by the address pin and the chip select pin.

· 8/16-bit bus width setting are available for every chip select area.
· Programmable automatic memory wait (max. for 7 cycles) can be inserted.
· DRAM interface support

Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F)

Single CAS DRAM
Hyper DRAM

2 banks independent control (RAS, CAS, etc. control signals)
DRAM select is available from 2CAS/1WE and 1CAS/2WE.
Hi-speed page mode supported
CBR/self refresh supported
Programmable wave form

· Unused address/data pin can be used for I/O port.
· Little endian mode supported
· Clock doubler: Internal bus 50 MHz, external bus 25 MHz

MB91101/MB91101A

· Register configuration

bit 31

bit 0

(W)

Address

Initial value

bit 16

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 1

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 1

0 0 0 0 0 0 0 0

: Access
: Redable and writable
: Write only
: Unused
: Indeterminate

( )

R/W

ASR1

AMR1

ASR2

AMR2

ASR3

AMR3

ASR4

AMR4

ASR5

AMR5

AMD0

AMD1

AMD32

AMD4

AMD5

DSCR

RFCR

EPCR0

DMCR4

DMCR5

LER

MODR

- - X X X X X X

0 0 - - - 0 0 0

- - - - 1 1 0 0

- 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 -

- - - - - 0 0 0

X X X X X X X X

- - - 0 0 1 1 1

0 - - 0 0 0 0 0

0 0 0 0 0 0 0 0

0 - - 0 0 0 0 0

0 0 0 0 0 0 0 0

(R/W)

(W)

(R/W)

(W)

(R/W)

(W)

0000060C

0000060D

0000060E

0000060F

00000610

00000611

00000612

00000613

00000614

00000615

00000616

00000617

00000618

00000619

0000061A

0000061B

0000061C

0000061D

0000061E

0000061F

00000626

00000627

00000628

00000629

0000062B

0000062C

0000062D

0000062E

0000062F

000007FE

000007FF

00000620

00000621

00000622

00000623

00000624

00000625

EPCR1

MB91101/MB91101A

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

= AV

= 0.0 V)

*1: V

5 must not be less than V

0.3 V.

*2: Make sure that the voltage does not exceed V

5 + 0.3 V, such as when turning on the device.

*3: Maximum output current is a peak current value measured at a corresponding pin.
*4: Average output current is an average current for a 100 ms period at a corresponding pin.
*5: Average total output current is an average current for a 100 ms period for all corresponding pins.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter

Symbol

Value

Unit

Remarks

Min.

Max.

Power supply
voltage

At 5 V power supply

0.3

+ 6.5

At 3 V power supply

3 0.3

+ 6.5

0.3

+ 3.6

Analog supply voltage

0.3

+ 3.6

Analog reference voltage

AVRH

0.3

+ 3.6

Analog pin input voltage

0.3

+ 0.3

Input voltage

0.3

+ 0.3

Output voltage

0.3

+ 0.3

"L" level maximum output current

"L" level average output current

OLAV

"L" level maximum total output current

100

"L" level average total output current

OLAV

"H" level maximum output current

"H" level average output current

OHAV

"H" level maximum total output current

"H" level average total output current

OHAV

Power consumption

500

Operating temperature

+70

Storage temperature

Tstg

+150

MB91101/MB91101A

Recommended Operating Conditions

(1) At 5 V operation (4.5 V to 5.5 V)

= AV

= 0.0 V)

*1: At V

5, the RAM state holding is not warranted in stop mode.

*2: V

3 is used for the bypass capacitor pin.

*3: Use the ceramic capacitor or the capacitor whose frequency characteristic is equivalent to that of the ceramic

capacitor.
And select the larger capacity smoothing condenser to connect to the power supply (V

5) than C

(2) At 3 V operation (2.7 V to 3.6 V)

= AV

= 0.0 V)

* : Connect to V

5 for the power supply pin.

Parameter

Symbol

Value

Unit

Remarks

Min.

Max.

Power supply voltage

4.5

5.5

Normal operation

Retaining the RAM state in
stop mode

Analog supply voltage

+ 2.7

+ 3.6

Analog reference voltage

AVRH

0.3

Operating temperature

+70

Smoothing capacitor

0.1

1.0

3 pin *2

Parameter

Symbol

Value

Unit

Remarks

Min.

Max.

Power supply voltage

2.7

3.6

Normal operation

2.7

3.6

Retaining the RAM state in
stop mode

2.7

3.6

Analog power supply voltage

+ 2.7

+ 3.6

Analog reference voltage

AVRH

Operating temperature

+70

AVRH

5 V

GND

Using with 5 V power supply

AVRH

3 V

GND

Using with 3 V power supply

About
0.1

· Connecting to a power supply

MB91101/MB91101A

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device's electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.

5.5

4.5

CPP

(MHz)

12.5

(MHz)

Internal clock

Supply voltage

Max. internal clock frequency setting

0.625

3.6
3.3
3.0
2.7

Normal operation warranty range (T

= 0

C to +70

Net masked area are f

CPP

(V)

12.5

PLL system (4 multiplication)

CPP

(MHz)

Source oscillating input clock

External clock

Self-oscillation

Notes:

When using PLL, the external clock must be used between 10.0 MHz to 12.5 MHz.

PLL oscillation stabilizing period > 100

The setting of internal clock must be within above ranges.

3.0 V

0.3 V

3.3 V

0.3 V

Power supply at 5 V

Power supply at 3 V

Divide-by-2 system

CPU

Peripheral

CPP

MB91101/MB91101A

DC Characteristics

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

* : V

3 = 3.3

0.2 V (internal regulator output voltage) when using 5 V power supply, V

3 = power supply voltage

when using 3 V power supply (internal regulator unused)

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

"H" level input
voltage

Input pin except
for hysteresis
input

0.65

5 + 0.3

IHS

HST, NMI, RST,
PA1 to PA6,
PB0 to PB7,
PE0 to PE7,
PF0 to PF7

0.8

5 + 0.3

Hysteresis
input *

"L" level input
voltage

Input other than
following
symbols

0.3

0.25

ILS

HST, NMI, RST,
PA1 to PA6,
PB0 to PB7,
PE0 to PE7,
PF0 to PF7

0.3

0.2

Hysteresis
input *

"H" level output
voltage

D16 to D31,
A00 to A24,
P6 to PF

5 = 4.5 V

= 4.0 mA

0.5

"L" level output
voltage

D16 to D31,
A00 to A24,
P6 to PF

5 = 4.5 V

= 4.0 mA

0.4

Input leakage
current
(Hi-Z output
leakage current)

D00 to D31,
A00 to A23,
P8 to PF

5 = 5.5 V

0.45 V < V

< V

Pull-up
resistance

PULL

RST

5 = 5.5 V

= 0.45 V

100

Power supply
current

= 12.5 MHz

5 = 5.5 V

100

(4 multiplication)

Operation at
50 MHz

CCS

= 12.5 MHz

5 = 5.5 V

mA Sleep mode

CCH

= +25

5 = 5.5 V

100

A Stop mode

Input
capacitance

Except for
V

5, V

, AV

, V

MB91101/MB91101A

AC Characteristics

Measurement Conditions

· V

= 5.0 V

10%

· V

= 2.7 V to 3.6 V

· Load conditions

Parameter

Symbol

Value

Unit

Remarks

Min.

Typ.

Max.

"H" level input voltage

2.4

"L" level input voltage

0.8

"H" level output voltage

2.4

"L" level output voltage

0.8

Parameter

Symbol

Value

Unit

Remarks

Min.

Typ.

Max.

"H" level input voltage

1/2

"L" level input voltage

1/2

"H" level output voltage

1/2

"L" level output voltage

1/2

0.0 V

Input

Output

0.0 V

Input

Output

C = 50 pF

Output pin

= 5.0V ± 10%)

MB91101/MB91101A

(1) Clock Timing Rating

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

*1: Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock

multiplication system.

*2: These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and

a 1/8 gear.

*3: Values when using the doubler and CPU operation at 50 MHz.

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Clock frequency

X0, X1

When using PLL

12.5

MHz

X0, X1

Self-oscillation
(divide-by-2 input)

MHz

X0, X1

External clock
(divide-by-2 input)

MHz

Clock cycle time

X0, X1

When using PLL

100

X0, X1

100

Frequency shift ratio
(when locked)

When using PLL

Input clock pulse width

X0, X1

Input to X0
only, when
using 5 V
power supply

X0, X1

Input to X0,
X1

Input clock rising/falling time

X0, X1

+ t

)

Internal operating clock
frequency

CPU system

0.625*

MHz

CPB

Bus system

0.625*

25*

MHz

CPP

Peripheral system

0.625*

MHz

Internal operating clock
cycle time

CPU system

1600*

CPB

Bus system

40*

1600*

CPP

Peripheral system

1600*

f =

100 (%)

Center frequency f

MB91101/MB91101A

(2) Clock Output Timing

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

, t

CPB

(internal operating clock cycle time): Refer to "(1) Clock Timing Rating."

*1: t

CYC

is a frequency for 1 clock cycle including a gear cycle.

Use the doubler when CPU frequency is above 25 MHz.

*2: Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8,
respectively.

Min. : (1 n/2)

CYC

Max. : (1 n/2)

CYC

+ 10

Select a gear cycle of

1 when using the doubler.

*3: Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8,
respectively.

Min. : n/2

CYC

Max. : n/2

CYC

+ 10

Select a gear cycle of

1 when using the doubler.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

Cycle time

CYC

CLK

CYC

CLK

Using the
doubler

CPB

CLK

CHCL

CLK

1/2

CYC

10 1/2

CYC

+ 10

CLK

CLCH

CLK

1/2

CYC

10 1/2

CYC

+ 10

CLK

CYC

CHCL

CLCH

MB91101/MB91101A

The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR
(gear control register) is as follows:

However, in this chart source oscillation input means X0 input clock.

CCK1/0: "00"

Source oscillation input
(when using the doublure)

Source oscillation input

(1) PLL system
(CHC bit of GCR set to "0")

(2) 2 dividing system
(CHC bit of GCR set to "1")

(a) Gear

1 CLK pin

CCK1/0: "00"

(b) Gear

1/2 CLK pin

CCK1/0: "01"

1/4 CLK pin

CCK1/0: "10"

(d) Gear

1/8 CLK pin

CCK1/0: "11"

CYC

(a) Gear

1 CLK pin

MB91101/MB91101A

· Discreet type

( ): C

and C

internally connected 3 contacts type.

Oscillation frequency

[MHz]

Model

Load capacitance

= C

[pF]

Power supply voltage

5 [V]

5.00 to 6.30

CSA

2.9 to 5.5

CST

MGW

(30)

CSA

MG093

2.7 to 5.5

CST

MGW093

(30)

6.31 to 10.0

CSA

MTZ

2.9 to 5.5

CST

MTW

(30)

CSA

MTZ093

2.7 to 5.5

CST

MTW093

(30)

10.1 to 13.0

CSA

MTZ

3.0 to 5.5

CST

MTW

(30)

CSA

MTZ093

2.9 to 5.5

CST

MTW093

(30)

13.01 to 15.00

CSA

MXZ040

3.2 to 5.5

CST

MXW0C3

(15)

Recommended circuit (2 contacts)

Recommended circuit (3 contacts)

, C

internally

connected.

* : Murata Mfg. Co., Ltd.

· Ceramic oscillator applications

MB91101/MB91101A

(3) Reset/Hardware Standby Input Ratings

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

(internal operating clock cycle time): Refer to "(1) Clock Timing Rating."

Parameter

Symbol Pin name Condition

Value

Unit

Remarks

Min.

Max.

Reset input time

RSTL

RST

Hardware standby input time

HSTL

HST

RST
HST

0.2 V

RSTL

, t

HSTL

MB91101/MB91101A

(4) Power on Supply Specifications (Power-on Reset)

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

(clock cycle time): Refer to "(1) Clock Timing Rating."

* : V

< 0.2 V before the power supply rising

Parameter

Symbol Pin name

Condition

Value

Unit

Remarks

Min.

Max.

Power supply rising time

= 5.0 V

= 3.0/

3.3 V

Power supply shut off time

OFF

Repeated
operations

Oscillation stabilizing time

OSC

+ 100

0.2 V

0.9

A voltage rising rate of 50 mV/ms or
less is recommended.

Sudden change in supply voltage during operation may initiate a power-on sequence.
To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid
fluctuations in the supply voltage.

Note:

RSTL

: Reset input time

OFF

RST

(Oscillation stabilizing time)

Note: Set RST pin to "L" level when turning on the device, at least the described above duration after the

supply voltage reaches Vcc is necessary before turning the RST to "H" level.

OSC

RSTL

+ (t

)

42 ms approx. 336 ms approx. (@12.5 MHz)

Stabilizing time *

*: Reset can't be done during regulator stabilizing time.

Regulator

MB91101/MB91101A

(5) Normal Bus Access Read/write Operation

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

CYC

(a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing."

*1: When bus timing is delayed by automatic wait insertion or RDY input, add (t

CYC

extended cycle number for

delay) to this rating.

*2: Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8,
respectively.

Equation: (2 n/2)

CYC

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

CS0 to CS5 delay time

CHCSL

CLK,
CS0 to CS5

CHCSH

CLK,
CS0 to CS5

Address delay time

CHAV

CLK,
A24 to A00

Data delay time

CHDV

CLK,
D31 to D16

RD delay time

CLRL

CLK, RD

CLRH

CLK, RD

WR0, WR1 delay time

CLWL

CLK,
WR0, WR1

CLWH

CLK,
WR0, WR1

Valid address

valid data

input time

AVDV

A24 to A00,
D31 to D16

3/2

CYC

*1
*2

valid data input time t

RLDV

RD,
D31 to D16

CYC

Data set up

time

DSRH

RD,
D31 to D16

data hold time

RHDX

RD,
D31 to D16

MB91101/MB91101A

(6) Ready Input Timing

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RDY set up time

CLK

RDYS

RDY, CLK

CLK

RDY hold time

RDYH

RDY, CLK

CLK

RDYH

RDY
When wait(s)
is inserted.

RDY
When no wait
is inserted.

CYC

RDYS

MB91101/MB91101A

(7) Hold Timing

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

CYC

(a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing."

Note: There is a delay time of more than 1 cycle from BRQ input to BGRNT change.

Parameter

Symbol Pin name Condition

Value

Unit

Remarks

Min.

Max.

BGRNT delay time

CHBGL

CLK,
BGRNT

CHBGH

CLK,
BGRNT

Pin floating

BGRNT

time

XHAL

BGRNT

CYC

+ 10

BGRNT

pin valid time

HAHV

BGRNT

CYC

+ 10

CLK

CHBGL

Each pin

High impedance

CHBGH

BRQ

BGRNT

CYC

XHAL

HAHV

MB91101/MB91101A

(8) Normal DRAM Mode Read/Write Cycle

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

CYC

(a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing."

CAS: CS0L to CS1H pins are for CAS signal outputs.
DW: DW0, DW1 and CS0H to CS1H are used for WE outputs.

*1: When Q1 cycle or Q4 cycle is extended for 1 cycle, add t

CYC

time to this rating.

*2: Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8,
respectively.

Equation: (3 n/2)

CYC

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH

CLK, RAS

CHRAL

CLK, RAS

CAS delay time

CLCASL

CLK, CAS

CLCASH

CLK, CAS

ROW address delay time

CHRAV

CLK,
A24 to A00

COLUMN address delay
time

CHCAV

CLK,
A24 to A00

DW delay time

CHDWL

CLK, DW

CHDWH

CLK, DW

Output data delay time

CHDV1

CLK,
D31 to D16

RAS

valid data input

time

RLDV

RAS,
D31 to D16

5/2

CYC

*1
*2

CAS

valid data input

time

CLDV

CAS,
D31 to D16

CYC

CAS

data hold time

CADH

CAS,
D31 to D16

MB91101/MB91101A

(9) Normal DRAM Mode Fast Page Read/Write Cycle

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

CYC

(a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing."

CAS: CS0L to CS1H pins are for CAS signal outputs.
DW: DW0, DW1 and CS0H to CS1H are used for WE outputs.

* : When Q4 cycle is extended for 1 cycle, add t

CYC

time to this rating.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH

CLK, RAS

CAS delay time

CLCASL

CLK, CAS

CLCASH

CLK, CAS

COLUMN address delay
time

CHCAV

CLK,
A24 to A00

DW delay time

CHDWH

CLK, DW

Output data delay time

CHDV1

CLK,
D31 to D16

CAS

valid data input

time

CLDV

CAS,
D31 to D16

CYC

CAS

data hold time

CADH

CAS,
D31 to D16

MB91101/MB91101A

(10) Single DRAM Timing

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

CYC

(a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing."

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH2

CLK, RAS

CHRAL2

CLK, RAS

CAS delay time

CHCASL2

CLK, CAS

n/2

CYC

CHCASH2

CLK, CAS

ROW address delay time

CHRAV2

CLK,
A24 to A00

COLUMN address delay
time

CHCAV2

CLK,
A24 to A00

DW delay time

CHDWL2

CLK, DW

CHDWH2

CLK, DW

Output data delay time

CHDV2

CLK,
D31 to D16

CAS

Valid data input

time

CLDV2

CAS,
D31 to D16

(1 n/2)

CYC

CAS

data hold time

CADH2

CLK,
D31 to D16

MB91101/MB91101A

Q4S

CYC

CHCASL2

CHCASH2

CLRAH2

CHRAL2

CHRAV2

CHDWL2

CHDWH2

CHDV2

CADH2

CLDV2

CHCAV2

ROW address

CLK

RAS

CAS

A24 to A00

D31 to D16

COLUMN-0

COLUMN-1

COLUMN-2

Read-0

Read-1

Read-2

Write-0

Write-2

Write-1

*1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle.
*2: indicates the timing when the bus cycle begins from the high spead page mode.

MB91101/MB91101A

(11) Hyper DRAM Timing

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

CYC

(a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing."

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH3

CLK, RAS

CHRAL3

CLK, RAS

CAS delay time

CHCASL3

CLK, CAS

n/2

CYC

CHCASH3

CLK, CAS

ROW address delay time

CHRAV3

CLK,
A24 to A00

COLUMN address delay
time

CHCAV3

CLK,
A24 to A00

RD delay time

CHRL3

CLK, RD

CHRH3

CLK, RD

CLRL3

CLK, RD

DW delay time

CHDWL3

CLK, DW

CHDWH3

CLK, DW

Output data delay time

CHDV3

CLK,
D31 to D16

CAS

valid data input

time

CLDV3

CAS,
D31 to D16

CYC

CAS

data hold time

CADH3

CLK,
D31 to D16

MB91101/MB91101A

Q4H

CYC

CHCASL3

CHCASH3

CLRAH3

CHRAL3

CHRAV3

CHCAV3

ROW address

CLK

RAS

CAS

A24 to A00

D31 to D16

COLUMN-0

COLUMN-1

COLUMN-2

CHDWL3

CHDWH3

CHDV3

CHRL3

CHRH3

CADH3

CLDV3

Read-0

Read-1

CLRL3

CHDV3

Write-0

Write-2

Write-1

*1: Q4H indicates Q4HR (Read) of Single DRAM cycle or Q4HW (Write) cycle.
*2: indicates the timing when the bus cycle begins from the high spead page mode.

MB91101/MB91101A

(12) CBR Refresh

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

CAS: CS0L to CS1H pins are for CAS signal outputs.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH

CLK, RAS

CHRAL

CLK, RAS

CAS delay time

CLCASL

CLK, CAS

CLCASH

CLK, CAS

CLCASH

CLK

RAS

CAS

CLRAH

CHRAL

CLCASL

CYC

MB91101/MB91101A

(13) Self Refresh

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

CAS: CS0L to CS1H pins are for CAS signal outputs.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH

CLK, RAS

CHRAL

CLK, RAS

CAS delay time

CLCASL

CLK, CAS

CLCASH

CLK, CAS

CLK

RAS

CAS

CHRAL

CLCASL

CLRAH

SR2

SR3

CLCASH

CYC

SR1

MB91101/MB91101A

(14) UART Timing

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

CYCP

: A cycle time of peripheral system clock

Notes: This rating is for AC characteristics in CLK synchronous mode.

Parameter

Symbol Pin name Condition

Value

Unit

Remarks

Min.

Max.

Serial clock cycle time

SCYC

Internal
shift clock
mode

CYCP

SCLK

SCLCH

CYCP

10 4

CYCP

+10

SCLK

SCHCL

CYCP

10 4

CYCP

+10

SCLK

SOUT delay time

SLOV

Valid SIN

SCLK

IVSH

100

SCLK

valid SIN hold

time

SHIX

Serial clock "H" pulse width

SHSL

External
shift clock
mode

CYCP

Serial clock "L" pulse width

SLSH

CYCP

SCLK

SOUT delay time

SLOV

150

Valid SIN

SCLK

IVSH

SCLK

valid SIN hold

time

SHIX

SCLK

SOUT

SIN

SCLK

SOUT

SIN

SCYC

SCLCH

SCHCL

SLOV

IVSH

SHIX

SHSL

SLSH

SLOV

IVSH

SHIX

· Internal shift clock mode

· External shift clock mode

MB91101/MB91101A

(15) Trigger System Input Timing

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

CYCP

: A cycle time of peripheral system clock

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

A/D start trigger input time

TRGH

TRGL

ATG

CYCP

PWM external trigger input
time

TRGH

TRGL

TRG0 to TRG3

CYCP

ATG
TRG0 to TRG3

TRGH

TRGL

MB91101/MB91101A

(16) DMA Controller Timing

5 = 5.0 V

10%, V

= AV

= 0.0 V, T

= 0

C to +70

5 = V

3 = 2.7 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

CYC

(a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing."

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

DREQ input pulse width t

DRWH

DREQ0 to DREQ2

CYC

DACK delay time
(Normal bus)
(Normal DRAM)

CLDL

CLK,
DACK0 to DACK2

CLDH

CLK,
DACK0 to DACK2

EOP delay time
(Normal bus)
(Normal DRAM)

CLEL

CLK,
EOP0 to EOP2

CLEH

CLK,
EOP0 to EOP2

DACK delay time
(Single DRAM)
(Hyper DRAM)

CHDL

CLK,
DACK0 to DACK2

n/2

CYC

CHDH

CLK,
DACK0 to DACK2

EOP delay time
(Single DRAM)
(Hyper DRAM)

CHEL

CLK,
EOP0 to EOP2

n/2

CYC

CHEH

CLK,
EOP0 to EOP2

CLK

DREQ0 to DREQ2

DACK0 to DACK2
EOP0 to EOP2
(Normal bus)
(Normal DRAM)

DACK0 to DACK2
EOP0 to EOP2
(Single DRAM)
(Hyper DRAM)

CYC

DRWH

CLDL

CLEL

CHDL

CHEL

CLDH

CLEH

CHDH

MB91101/MB91101A

A/D Converter Block Electrical Characteristics

(AV

= 2.7 V to 3.6 V, AV

= 0.0 V, AVRH = 2.7 V, T

= 0

C to +70

*1: AV

= 2.7 V 3.6 V

*2: Current value for A/D converters not in operation, CPU stop mode (V

= AV

= AVRH = 3.6 V)

Notes: · As the absolute value of AVRH decreases, relative error increases.

· Output impedance of external circuit of analog input under following conditions;

Output impedance of external circuit < 10 k

If output impedance of external circuit is too high, analog voltage sampling time may be too short for
accurate sampling (sampling time is 5.6

s for a machine clock of 25 MHz).

Parameter

Symbol

Pin name

Value

Unit

Min.

Typ.

Max.

Resolution

bit

Total error

4.0

LSB

Linearity error

3.5

LSB

Differentiation linearity error

2.0

LSB

Zero transition voltage

AN0 to AN3

1.5

+0.5

+2.5

LSB

Full-scale transition voltage

FST

AN0 to AN3

AVRH 4.5 AVRH 1.5 AVRH + 0.5 LSB

Conversion time

5.6 *

Analog port input current

AIN

AN0 to AN3

0.1

Analog input voltage

AIN

AN0 to AN3

AVRH

Reference voltage

AVRH

Power supply current

5 *

Reference voltage supply current

AVRH

200

AVRH

5 *

Conversion variance between channels

AN0 to AN3

LSB

ON1

0.2 k

ON2

1.4 k

ON3

1.4 k

ON4

0.2 k

16.6 pF

4.0 pF

ON2

ON3

ON4

Analog input

Note: Listed values are for reference purposes only.

Comparator

Sample and hold circuit

· Analog input circuit model plan

MB91101/MB91101A

A/D Converter Glossary

· Resolution

The smallest change in analog voltage detected by A/D converter.

· Linearity error

A deviation of actual conversion characteristic from a line connecting the zero-traction point (between "00 0000
0000"

"00 0000 0001") to the full-scale transition point (between "11 1111 1110"

"11 1111 1111").

· Differential linearity error

A deviation of a step voltage for changing the LSB of output code from ideal input voltage.

(Continued)

3FF

3FE

3FD

004

003

002

001

AVRL

AVRH

Linearity error

Analog input

Actual conversion
characteristic

{1 LSB

(N 1) + V

}

Actual conversion
characteristic

Ideal characteristic

1 LSB =

[V]

FST

1022

Linearity error of

digital output N =

{1 LSB

(N 1) + V

}

1 LSB

: A voltage for causing transition of digital output from (000)

to (001)

(measured value)

FST

(measured
value)

(measured value)

AVRL

AVRH

Differential linearity error

Analog input

N+1

Actual characteristic

Ideal characteristic

Actual conversion characteristic

(measured value)

(N + 1)T

(measured value)

[LSB]

Differential linearity error

of digital output N =

(N + 1)T

1 LSB

[LSB]

FST

: A voltage for causing transition of digital output from (3FE)

to (3FF)

: A voltage for causing transition of digital output from (N 1)

to N

Digital output

MB91101/MB91101A

(Continued)

· Total error

A difference between actual value and theoretical value. The overall error includes zero-transition error, full-
scale transition error and linearity error.

: A voltage for causing transition of digital output from (N 1) to N

3FF

3FE

3FD

004

003

002

001

AVRL

AVRH

Total error

Analog input

Actual conversion
characteristic

1.5 LSB'

{1 LSB'

(N 1)

+ 0.5 LSB'}

(measured value)

Actual conversion
characteristic

Ideal characteristic

0.5 LSB'

(ideal value) = AVRL + 0.5 LSB'

[LSB]

(ideal value) = AVRL 1.5 LSB' [V]

[V]

FST

Total error of digital output N =

{1 LSB'

(N 1) + 0.5 LSB'}

1 LSB'

Digital output

1 LSB' (ideal value) =

[V]

AVRH AVRL

1024

MB91101/MB91101A

REFERENCE DATA

Operating frequency vs. I

characteristics

vs. I

characteristics

)

3.6 V

3.3 V

3.0 V

2.7 V

(mA)

)

4.5 V to 5.5 V

(mA)

f (MHz)

Internal DC - DC regulator is not used (V

= 3 V)

Internal DC - DC regulator is used (V

= 5 V)

Operating conditions : Source oscillation 12.5 MHz (crystal), PLL is used (50 M, 25 M, 12.5 M)
Gear : CPU = 1/1, Peripherals = 1/1
(Doubler is used for 50MHz, Gear peripherals = 1/2)

(V)

3.3

3.0

2.7

3.6

5.0

4.5

5.5

(mA)

Icc (mA)

Gear : 1/1

Gear : 1/2

Gear : 1/4

Gear : 1/8

Gear : 1/8
(PLL : off)

Gear : 1/1

Gear : 1/2

Gear : 1/4

Gear : 1/8

Gear : 1/8
(PLL : off)

Internal DC - DC regulator is not used (V

= 3 V)

Internal DC - DC regulator is used (V

= 5 V)

Operating conditions : Source oscillation 12.5 MHz (crystal), divide-by-2 input, PLL : ON
Gear : CPU = Peripherals

MB91101/MB91101A

INSTRUCTIONS (165 INSTRUCTIONS)

How to Read Instruction Set Summary

(1) Names of instructions

Instructions marked with * are not included in CPU specifications. These are extended instruction codes
added/extended at assembly language levels.

(2) Addressing modes specified as operands are listed in symbols.

Refer to "2. Addressing mode symbols" for further information.

(3) Instruction types

(4) Hexa-decimal expressions of instructions

(5) The number of machine cycles needed for execution

a: Memory access cycle and it has possibility of delay by Ready function.

b: Memory access cycle and it has possibility of delay by Ready function.

If an object register in a LD operation is referenced by an immediately following instruction, the interlock
function is activated and number of cycles needed for execution increases.

c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or

if the instruction belongs to instruction format A group, the interlock function is activated and number of
cycles needed for execution increases by 1 to make the total number of 2 cycles needed.

d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number

of cycles needed for execution increases by 1 to make the total number of 2 cycles needed.

For a, b, c and d, minimum execution cycle is 1.

(6) Change in flag sign

· Flag change

C : Change
: No change
0 : Clear
1 : Set

· Flag meanings

N : Negative flag
Z : Zero flag
V : Over flag
C : Carry flag

(7) Operation carried out by instruction

Mnemonic

Type

CYC

NZVC

Operation

Remarks

ADD

Rj,

* ADD

#s5,

,
,

A6
A4

,
,

1
1

,
,

CCCC
CCCC

,
,

Ri + Rj

Ri + s5

,
,

(1)

(2)

(3)

(4)

(5)

(6)

(7)

MB91101/MB91101A

Addressing Mode Symbols

: Register direct (R0 to R15, AC, FP, SP)

R13

: Register direct (R13, AC)

: Register direct (Program status register)

: Register direct (TBR, RP, SSP, USP, MDH, MDL)

CRi

: Register direct (CR0 to CR15)

CRj

: Register direct (CR0 to CR15)

#i8

: Unsigned 8-bit immediate (128 to 255)

Note: 128 to 1 are interpreted as 128 to 255

#i20

: Unsigned 20-bit immediate (0X80000 to 0XFFFFF)

Note: 0X7FFFF to 1 are interpreted as 0X7FFFF to 0XFFFFF

#i32

: Unsigned 32-bit immediate (0X80000000 to 0XFFFFFFFF)

Note: 0X80000000 to 1 are interpreted as 0X80000000 to 0XFFFFFFFF

#s5

: Signed 5-bit immediate (16 to 15)

#s10

: Signed 10-bit immediate (512 to 508, multiple of 4 only)

#u4

: Unsigned 4-bit immediate (0 to 15)

#u5

: Unsigned 5-bit immediate (0 to 31)

#u8

: Unsigned 8-bit immediate (0 to 255)

#u10

: Unsigned 10-bit immediate (0 to 1020, multiple of 4 only)

@dir8

: Unsigned 8-bit direct address (0 to 0XFF)

@dir9

: Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)

@dir10

: Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only)

label9

: Signed 9-bit branch address (0X100 to 0XFC, multiple of 2 only)

label12

: Signed 12-bit branch address (0X800 to 0X7FC, multiple of 2 only)

label20

: Signed 20-bit branch address (0X80000 to 0X7FFFF)

label32

: Signed 32-bit branch address (0X80000000 to 0X7FFFFFFF)

@Ri

: Register indirect (R0 to R15, AC, FP, SP)

@Rj

: Register indirect (R0 to R15, AC, FP, SP)

@(R13, Rj)

: Register relative indirect (Rj: R0 to R15, AC, FP, SP)

@(R14, disp10) : Register relative indirect (disp10: 0X200 to 0X1FC, multiple of 4 only)
@(R14, disp9) : Register relative indirect (disp9: 0X100 to 0XFE, multiple of 2 only)
@(R14, disp8) : Register relative indirect (disp8: 0X80 to 0X7F)
@(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only)
@Ri+

: Register indirect with post-increment (R0 to R15, AC, FP, SP)

@R13+

: Register indirect with post-increment (R13, AC)

@SP+

: Stack pop

@SP

: Stack push

(reglist)

: Register list

MB91101/MB91101A

100

Detailed Description of Instructions

· Add/subtract operation instructions (10 instructions)

· Compare operation instructions (3 instructions)

· Logical operation instructions (12 instructions)

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

ADD

Rj, Ri

* ADD

#s5, Ri

ADD

#i4, Ri

ADD2

#i4, Ri

C
C

A6
A4

A4
A5

1
1

C C C C
C C C C

Ri + Rj

Ri + s5

Ri + extu (i4)

MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension

ADDC

Rj, Ri

C C C C Ri + Rj + c

Add operation with
sign

ADDN

Rj, Ri

* ADDN

#s5, Ri

ADDN

#i4, Ri

ADDN2

#i4, Ri

C
C

A2
A0

A0
A1

1
1

Ri + Rj

Ri + s5

Ri + extu (i4)

MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension

SUB

Rj, Ri

C C C C Ri Rj

SUBC

Rj, Ri

C C C C Ri Rj c

Subtract operation with
carry

SUBN

Rj, Ri

Ri Rj

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

CMP

Rj, Ri

* CMP

#s5, Ri

CMP

#i4, Ri

CMP2

#i4, Ri

C
C

A8
A9

1
1

C C C C
C C C C

Ri Rj
Ri s5

Ri + extu (i4)
Ri + extu (i4)

MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

AND

Rj, Ri

AND

Rj, @Ri

ANDH

Rj, @Ri

ANDB

Rj, @Ri

A
A
A
A

82
84
85
86

1 + 2a
1 + 2a
1 + 2a

C C
C C
C C
C C

Ri & = Rj
(Ri) & = Rj
(Ri) & = Rj
(Ri) & = Rj

Word
Word
Half word
Byte

Rj, Ri

Rj, @Ri

ORH

Rj, @Ri

ORB

Rj, @Ri

A
A
A
A

92
94
95
96

1 + 2a
1 + 2a
1 + 2a

C C
C C
C C
C C

Ri | = Rj
(Ri) | = Rj
(Ri) | = Rj
(Ri) | = Rj

Word
Word
Half word
Byte

EOR

Rj, Ri

EOR

Rj, @Ri

EORH

Rj, @Ri

EORB

Rj, @Ri

A
A
A
A

9C
9D

1 + 2a
1 + 2a
1 + 2a

C C
C C
C C
C C

Ri ^ = Rj
(Ri) ^ = Rj
(Ri) ^ = Rj
(Ri) ^ = Rj

Word
Word
Half word
Byte

101

MB91101/MB91101A

· Bit manipulation arithmetic instructions (8 instructions)

*1: Assembler generates BANDL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates

BANDH if "u8&0xF0" leaves an active bit. Depending on the value in the "u8" format, both BANDL and BANDH
may be generated.

*2: Assembler generates BORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates

BORH if "u8&0xF0" leaves an active bit.

*3: Assembler generates BEORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates

BEORH if "u8&0xF0" leaves an active bit.

· Add/subtract operation instructions (10 instructions)

*1: DIVOS, DIV1

32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes.

*2: DIVOU and DIV1

32 are generated. A total instruction code length of 66 bytes.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

BANDL

#u4, @Ri
(u4: 0 to 0F

)

BANDH

#u4, @Ri
(u4: 0 to 0F

)

* BAND

#u8, @Ri

1 + 2a

(Ri) & = (F0

+ u4)

(Ri) & = ((u4<<4) + 0F

)

(Ri) & = u8

Manipulate lower 4 bits

Manipulate upper 4 bits

BORL

#u4, @Ri
(u4: 0 to 0F

)

BORH

#u4, @Ri
(u4: 0 to 0F

)

* BOR

#u8, @Ri

1 + 2a

(Ri) | = u4

(Ri) | = (u4<<4)

(Ri) | = u8

Manipulate lower 4 bits

Manipulate upper 4 bits

BEORL

#u4, @Ri
(u4: 0 to 0F

)

BEORH

#u4, @Ri
(u4: 0 to 0F

)

* BEOR

#u8, @Ri

1 + 2a

(Ri) ^ = u4

(Ri) ^ = (u4<<4)

(Ri) ^ = u8

Manipulate lower 4 bits

Manipulate upper 4 bits

BTSTL

#u4, @Ri
(u4: 0 to 0F

)

BTSTH

#u4, @Ri
(u4: 0 to 0F

)

2 + a

0 C

C C

(Ri) & u4

(Ri) & (u4<<4)

Test lower 4 bits

Test upper 4 bits

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

MUL

Rj, Ri

MULU

Rj, Ri

MULH

Rj, Ri

MULUH

Rj, Ri

A
A
A
A

5
5
3
3

C C C
C C C
C C
C C

MDH, MDL

MDL

32-bit

32-bit = 64-bit

Unsigned
16-bit

16-bit = 32-bit

Unsigned

DIVOS

DIVOU

DIV1

DIV2

DIV3
DIV4S
* DIV

* DIVU

E
E
E
E
E
E

97 4
97 5
97 6
97 7

9F 6
9F 7

1
1
d
1
1
1

C C
C C

C C

C C

MDL/Ri

MDL,

MDL%Ri

MDH

MDL/Ri

MDL,

MDL%Ri

MDH

Step calculation
32-bit/32-bit = 32-bit

Unsigned

MB91101/MB91101A

102

· Shift arithmetic instructions (9 instructions)

· Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer

instruction) (3 instructions)

*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection.

If an immediate value contains relative value or external reference, assembler selects i32.

· Memory load instructions (13 instructions)

Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler

description from disp8 to disp10 are as follows:

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

LSL

Rj, Ri

* LSL

#u5, Ri

LSL

#u4, Ri

LSL2

#u4, Ri

C
C

B6
B4
B4
B5

1
1
1
1

C C C
C C C
C C C
C C C

Ri<<Rj

Ri<<u5

Ri<<u4

Ri<<(u4 + 16)

Logical shift

LSR

Rj, Ri

* LSR

#u5, Ri

LSR

#u4, Ri

LSR2

#u4, Ri

C
C

B2
B0
B0
B1

1
1
1
1

C C C
C C C
C C C
C C C

Ri>>Rj

Ri>>u5

Ri>>u4

Ri>>(u4 + 16)

Logical shift

ASR

Rj, Ri

* ASR

#u5, Ri

ASR

#u4, Ri

ASR2

#u4, Ri

C
C

B8
B8
B9

1
1
1
1

C C C
C C C
C C C
C C C

Ri>>Rj

Ri>>u5

Ri>>u4

Ri>>(u4 + 16)

Logical shift

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

LDI: 32

#i32, Ri

LDI: 20

#i20, Ri

LDI: 8

#i8, Ri

* LDI

# {i8 | i20 | i32}, Ri

9F 8

3
2

i32

i20

{i8 | i20 | i32}

Upper 12 bits are zero-
extended
Upper 24 bits are zero-
extended

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

@Rj, Ri

@(R13, Rj), Ri

@(R14, disp10), Ri

@(R15, udisp6), Ri

@R15 +, Ri

@R15 +, Rs

@R15 +, PS

A
A
B

E
E

04
00
20
03

07 0
07 8

07 9

b
b
b
b
b
b

1 + a + b

C C C C

(Rj)

(R13 + Rj)

(R14 + disp10)

(R15 + udisp6)

(R15)

Ri, R15 + = 4

(R15)

Rs, R15 + = 4

(R15)

PS, R15 + = 4

Rs: Special-purpose

LDUH

@Rj, Ri

LDUH

@(R13, Rj), Ri

LDUH

@(R14, disp9), Ri

A
A
B

05
01
40

b
b
b

(Rj)

(R13 + Rj)

(R14 + disp9)

Zero-extension
Zero-extension
Zero-extension

LDUB

@Rj, Ri

LDUB

@(R13, Rj), Ri

LDUB

@(R14, disp8), Ri

A
A
B

06
02
60

b
b
b

(Rj)

(R13 + Rj)

(R14 + disp8)

Zero-extension
Zero-extension
Zero-extension

disp8

o8 = disp8

disp9

o8 = disp9>>1

disp10

o8 = disp10>>2

udisp6

u4 = udisp6>>2

Each disp is a code extension.

udisp4 is a 0 extension.

103

MB91101/MB91101A

· Memory store instructions (13 instructions)

Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler

description from disp8 to disp10 are as follows:

· Transfer instructions between registers/special-purpose registers transfer instructions

(5 instructions)

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

Ri, @Rj

Ri, @(R13, Rj)

Ri, @(R14, disp10)

Ri, @(R15, udisp6)

Ri, @R15

Rs, @R15

PS, @R15

A
A
B

E
E

14
10
30
13

17 0
17 8

17 9

a
a
a
a
a
a

(Rj)

(R13 + Rj)

(R14 + disp10)

(R15 + usidp6)

R15 = 4, Ri

(R15)

R15 = 4, Rs

(R15)

R15 = 4, PS

(R15)

Word
Word
Word

Rs: Special-purpose

STH

Ri, @Rj

STH

Ri, @(R13, Rj)

STH

Ri, @(R14, disp9)

A
A
B

15
11
50

a
a
a

(Rj)

(R13 + Rj)

(R14 + disp9)

Half word
Half word
Half word

STB

Ri, @Rj

STB

Ri, @(R13, Rj)

STB

Ri, @(R14, disp8)

A
A
B

16
12
70

a
a
a

(Rj)

(R13 + Rj)

(R14 + disp8)

Byte
Byte
Byte

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

MOV

Rj, Ri

MOV

Rs, Ri

MOV

Ri, Rs

MOV

PS, Ri

MOV

Ri, PS

E
E

17 1
07 1

C C C C

Transfer between
general-purpose
registers
Rs: Special-purpose

Rs: Special-purpose

disp8

o8 = disp8

disp9

o8 = disp9>>1

disp10

o8 = disp10>>2

udisp6

u4 = udisp6>>2

Each disp is a code extension.

udisp4 is a 0 extension.

MB91101/MB91101A

104

· Non-delay normal branch instructions (23 instructions)

Notes: · "2/1" in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch.

· The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and

assembler discription label9 and label12 are as follows.
label9

rel8 = (label9 PC 2)/2

label12

rel11 = (label12 PC 2)/2

· RETI must be operated while S flag = 0.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

JMP

@Ri

97 0

CALL

label12

CALL

@Ri

97 1

PC + 2

RP,

PC + 2 + rel11

PC + 2

RP, Ri

RET

97 2

Return

INT

#u8

3+3a

SSP = 4, PS

(SSP),

SSP = 4,
PC + 2

(SSP),

I flag,

S flag,

(TBR + 3FC u8

INTE

9F 3 3 + 3a SSP = 4, PS

(SSP),

SSP = 4,
PC + 2

(SSP),

S flag,

(TBR + 3D8 u8

For emulator

RETI

97 3 2 + 2a C C C C (R15)

PC, R15 = 4,

(R15)

PS, R15 = 4

BNO

label9

BRA

label9

BEQ

label9

BNE

label9

BNC

label9

BNV

label9

BLT

label9

BGE

label9

BLE

label9

BGT

label9

BLS

label9

BHI

label9

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

E1
E0
E2
E3
E4
E5
E6
E7
E8
E9

EA
EB

EC
ED

1
2

2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1

Non-branch
PC + 2 + rel8

PCif Z = = 1
PCif Z = = 0
PCif C = = 1
PCif C = = 0
PCif N = = 1
PCif N = = 0
PCif V = = 1
PCif V = = 0
PCif V xor N = = 1
PCif V xor N = = 0
PCif (V xor N) or Z = = 1
PCif (V xor N) or Z = = 0
PCif C or Z = = 1
PCif C or Z = = 0

105

MB91101/MB91101A

· Branch instructions with delays (20 instructions)

Notes: · The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and

assembler discription label9 and label12 are as follows.

label9

rel8 = (label9 PC 2)/2

label12

rel11 = (label12 PC 2)/2

· Delayed branch operation always executes next instruction (delay slot) before making a branch.
· Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other

instruction is stored, this device may operate other operation than defined.

The instruction described "1" in the other cycle column than branch instruction.
The instruction described "a", "b", "c" or "d" in the cycle column.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

JMP:D

@Ri

9F 0

CALL:D

label12

CALL:D

@Ri

9F 1

PC + 4

RP,

PC + 2 + rel11

PC + 4

RP, Ri

RET:D

9F 2

Return

BNO:D

label9

BRA:D

label9

BEQ:D

label9

BNE:D

label9

BC:D

label9

BNC:D

label9

BN:D

label9

BP:D

label9

BV:D

label9

BNV:D

label9

BLT:D

label9

BGE:D

label9

BLE:D

label9

BGT:D

label9

BLS:D

label9

BHI:D

label9

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

F1
F0
F2
F3
F4
F5
F6
F7
F8
F9

FA
FB

FC
FD

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Non-branch
PC + 2 + rel8

MB91101/MB91101A

106

· Direct addressing instructions

Note: The relations between the dir field of TYPE-D in the instruction format and the assembler description from

disp8 to disp10 are as follows:

· Resource instructions (2 instructions)

· Co-processor instructions (4 instructions)

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

DMOV

@dir10, R13

DMOV

R13, @dir10

DMOV

@dir10, @R13+

DMOV

@R13+, @dir10

DMOV

@dir10, @R15

DMOV

@R15+, @dir10

D
D
D
D
D
D

08
18

0C
1C

0B
1B

b
a

2a
2a
2a
2a

(dir10)

R13

(dir10)

(R13), R13 + = 4

(R13)

(dir10), R13 + = 4

R15 = 4, (dir10)

(R15)

(dir10), R15 + = 4

Word
Word
Word
Word
Word
Word

DMOVH

@dir9,

R13

DMOVH

R13, @dir9

DMOVH

@dir9,

@R13+

DMOVH

@R13+, @dir9

D
D
D
D

09
19

0D
1D

b
a

2a
2a

(dir9)

R13

(dir9)

(R13), R13 + = 2

(R13)

(dir9), R13 + = 2

Half word
Half word
Half word
Half word

DMOVB

@dir8,

R13

DMOVB

R13, @dir8

DMOVB

@dir8,

@R13+

DMOVB

@R13+, @dir8

D
D
D
D

0A
1A
0E
1E

b
a

2a
2a

(dir8)

R13

(dir8)

(R13), R13 + +

(R13)

(dir8), R13 + +

Byte
Byte
Byte
Byte

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

LDRES

@Ri+,

#u4

(Ri)

u4 resource

Ri + = 4

u4: Channel number

STRES

#u4, @Ri+

resource

(Ri)

Ri + = 4

u4: Channel number

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

COPOP

#u4, #CC, CRj, CRi

COPLD

#u4, #CC, Rj,

CRi

COPST

#u4, #CC, CRj, Ri

COPSV

#u4, #CC, CRj, Ri

E
E
E
E

9F C
9F D
9F E
9F F

2 + a

1 + 2a
1 + 2a
1 + 2a

Calculation
Rj

CRi

CRj

No error traps

disp8

dir + disp8

disp9

dir = disp9>>1

disp10

dir = disp10>>2

Each disp is a code extension

107

MB91101/MB91101A

· Other instructions (16 instructions)

*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler

description s10 is as follows.
s10

s8 = s10>>2

*2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler

description u10 is as follows.
u10

u8 = u10>>2

*3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified,

assembler generates LDM1. Both LDM0 and LDM1 may be generated.

*4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following

calculation; a

(n 1) + b + 1 when "n" is number of registers specified.

*5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified,

assembler generates STM1. Both STM0 and STM1 may be generated.

*6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following

calculation; a

n + 1 when "n" is number of registers specified.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

NOP

9F A

No changes

ANDCCR #u8
ORCCR

#u8

D
D

83
93

c
c

C C C C
C C C C

CCR and u8

CCR

CCR or u8

CCR

STILM

#u8

ILM

Set ILM immediate
value

ADDSP

#s10

R15 + = s10

ADD SP instruction

EXTSB

EXTUB

EXTSH

EXTUH

E
E
E
E

97 8
97 9

97 A
97 B

1
1
1
1

Sign extension 8

32 bits

Zero extension 8

32 bits

Sign extension 16

32 bits

Zero extension 16

32 bits

LDM0

(reglist)

LDM1

(reglist)

* LDM

(reglist)

(R15)

reglist,

R15 increment
(R15)

reglist,

R15 increment
(R15 + +)

reglist,

Load-multi R0 to R7

Load-multi R8 to R15

Load-multi R0 to R15

STM0

(reglist)

STM1

(reglist)

* STM2

(reglist)

R15 decrement,
reglist

(R15)

R15 decrement,
reglist

(R15)

reglist

(R15 + +)

Store-multi R0 to R7

Store-multi R8 to R15

Store-multi R0 to R15

ENTER

#u10

1+a

R14

(R15 4),

R15 4

R14,

R15 u10

R15

Entrance processing
of function

LEAVE

9F 9

R14 + 4

R15,

(R15 4)

R14

Exit processing of
function

XCHB

@Rj, Ri

TEMP,

(Rj)

Ri,

TEMP

(Rj)

For SEMAFO
management
Byte data

MB91101/MB91101A

108

· 20-bit normal branch macro instructions

*1: CALL20

(1) If label20 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL

label12

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

CALL

@Ri

*2: BRA20

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

JMP

@Ri

*3: Bcc20 (BEQ20 to BHI20)

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:20

#label20, Ri

JMP

@Ri

false:

Mnemonic

Operation

Remarks

* CALL20

label20, Ri

Next instruction address

RP, label20

Ri: Temporary register

* BRA20

label20, Ri

* BEQ20

label20, Ri

* BNE20

label20, Ri

* BC20

label20, Ri

* BNC20

label20, Ri

* BN20

label20, Ri

* BP20

label20, Ri

* BV20

label20, Ri

* BNV20

label20, Ri

* BLT20

label20, Ri

* BGE20

label20, Ri

* BLE20

label20, Ri

* BGT20

label20, Ri

* BLS20

label20, Ri

* BHI20

label20, Ri

label20

if (Z = = 1) then label20

ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0

Ri: Temporary register

109

MB91101/MB91101A

· 20-bit delayed branch macro instructions

*1: CALL20:D

(1) If label20 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL:D label12

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

CALL:D @Ri

*2: BRA20:D

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA:D

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

JMP:D

@Ri

*3: Bcc20:D (BEQ20:D to BHI20:D)

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc:D

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:20

#label20, Ri

JMP:D

@Ri

false:

Mnemonic

Operation

Remarks

* CALL20:D label20, Ri

Next instruction address + 2

RP, label20

Ri: Temporary register

* BRA20:D label20, Ri
* BEQ20:D label20, Ri
* BNE20:D label20, Ri
* BC20:D

label20, Ri

* BNC20:D label20, Ri
* BN20:D

label20, Ri

* BP20:D

label20, Ri

* BV20:D

label20, Ri

* BNV20:D label20, Ri
* BLT20:D

label20, Ri

* BGE20:D label20, Ri
* BLE20:D

label20, Ri

* BGT20:D label20, Ri
* BLS20:D

label20, Ri

* BHI20:D

label20, Ri

label20

if (Z = = 1) then label20

Ri: Temporary register

MB91101/MB91101A

110

· 32-bit normal macro branch instructions

*1: CALL32

(1) If label32 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL

label12

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

CALL

@Ri

*2: BRA32

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

JMP

@Ri

*3: Bcc32 (BEQ32 to BHI32)

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:32

#label32, Ri

JMP

@Ri

false:

Mnemonic

Operation

Remarks

* CALL32

label32, Ri

Next instruction address

RP, label32

Ri: Temporary register

* BRA32

label32, Ri

* BEQ32

label32, Ri

* BNE32

label32, Ri

* BC32

label32, Ri

* BNC32

label32, Ri

* BN32

label32, Ri

* BP32

label32, Ri

* BV32

label32, Ri

* BNV32

label32, Ri

* BLT32

label32, Ri

* BGE32

label32, Ri

* BLE32

label32, Ri

* BGT32

label32, Ri

* BLS32

label32, Ri

* BHI32

label32, Ri

label32

if (Z = = 1) then label32

Ri: Temporary register

111

MB91101/MB91101A

· 32-bit delayed macro branch instructions

*1: CALL32:D

(1) If label32 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL:D label12

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

CALL:D @Ri

*2: BRA32:D

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA:D

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

JMP:D

@Ri

*3: Bcc32:D (BEQ32:D to BHI32:D)

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc:D

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:32

#label32, Ri

JMP:D

@Ri

false:

Mnemonic

Operation

Remarks

* CALL32:D label32, Ri

Next instruction address + 2

RP, label32

Ri: Temporary register

* BRA32:D label32, Ri
* BEQ32:D label32, Ri
* BNE32:D label32, Ri
* BC32:D

label32, Ri

* BNC32:D label32, Ri
* BN32:D

label32, Ri

* BP32:D

label32, Ri

* BV32:D

label32, Ri

* BNV32:D label32, Ri
* BLT32:D

label32, Ri

* BGE32:D label32, Ri
* BLE32:D

label32, Ri

* BGT32:D label32, Ri
* BLS32:D

label32, Ri

* BHI32:D

label32, Ri

label32

if (Z = = 1) then label32

Ri: Temporary register

113

MB91101/MB91101A

PACKAGE DIMENSIONS

(Continued)

1995 FUJITSU LIMITED F100007S-2C-3

Details of "B" part

16.00±0.20(.630±.008)SQ

14.00±0.10(.551±.004)SQ

0.50(.0197)TYP

.007

.001

+.003

0.03

+0.08

0.18

INDEX

0.10(.004)

0.08(.003)

.059

.004

+.008

0.10

+0.20

1.50

.005

.001

+.002

0.02

+0.05

0.127

15.00

12.00

(.472)

REF

(.591)

NOM

"B"

"A"

100

0.50±0.20(.020±.008)

Details of "A" part

0.40(.016)MAX

0.15(.006)MAX

0.15(.006)

0.10±0.10

(.004±.004)

(STAND OFF)

0~10°

LEAD No.

(Mouting height)

Dimensions in mm (inches)

(FPT-100P-M05)

100-pin Plastic LQFP

MB91101/MB91101A

114

(Continued)

Note: The design may be modified changed without notice, contact to Fujitsu sales division when using the device.

1994 FUJITSU LIMITED F100008-3C-2

"A"

"B"

0.10(.004)

0.53(.021)MAX

0.18(.007)MAX

Details of "A" part

0 10°

Details of "B" part

12.35(.486)

REF

16.30±0.40

(.642±.016)

0.05(.002)MIN

(STAND OFF)

0.15±0.05(.006±.002)

INDEX

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

17.90±0.40

14.00±0.20

(.551±.008)

(.705±.016)

0.13(.005)

18.85(.742)REF

22.30±0.40(.878±.016)

100

0.25(.010)

0.30(.012)

0.65(.0256)TYP

0.30±0.10

(.012±.004)

LEAD No.

0.80±0.20

(.031±.008)

3.35(.132)MAX

(Mounting height)

Dimensions in mm (inches)

(FPT-100P-M06)

100-pin Plastic QFP

115

MB91101/MB91101A

FUJITSU LIMITED

For further information please contact:

Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608
Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122

http://www.fujitsu-ede.com/

Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220

http://www.fmap.com.sg/

F9907

FUJITSU LIMITED Printed in Japan

The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
measurement equipment, personal or household devices, etc.).

CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.

Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91101

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91101

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91101