DS07-05309-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
Microprocessor SPARClite
CMOS
32-bit Embedded Controller
MB86830 Series
MB86831/832/833/834/835/836
s
DESCRIPTION
The MB86830 series is a SPARClite *
1
series of RISC architecture processors, providing high performance for a
variety of embedded applications. Conforming to the SPARC *
2
architecture, the MB86830 series is upward code-
compatible with the conventional products in the SPARClite family. When running at 100 MHz, the MB86830 series
provides performance of 121 VAX-MIPS.
The MB86830 series has on-chip data and instruction caches, allowing the processor to operate independently of
the wait time for external memory. The independent instruction bus and internal data bus serve as high-bandwidth
interfaces between the IU (integer unit) and caches. The MB86830 series also contains an internal multiplier circuit
that facilitates interfacing with external devices, thereby providing high performance with continuous cache hits. The
DRAM controller supports both of EDO and fast-page mode DRAMs. The interrupt controller (IRC) supports eight
channels of interrupts, allowing a trigger mode and mask to be set for each of the channels. To get the most out of
the system with a minimum number of external circuits, the MB86830 series supports chip select output, program-
mable wait state generator, and page mode DRAM interfaces.
The combination of these features of the MB86830 series achieves high levels of speed, flexibility, and efficiency,
making it a line of ideal controllers for a variety of low-cost, high-performance embedded systems.
*1 : SPARClite is a trademark of SPARC International, Inc. in the United States.
Fujitsu Microelectronics, Inc. has been granted permission to use the trademark.
*2 : SPARC is a registered trademark of SPARC International, Inc. in the United States.
SPARC is based on technology developed by Sun Microsystems, Inc.
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PACKAGE
176-pin plastic QFP
MB86831/832/834
144-pin plastic LQFP
MB86833/835/836
144-pin plastic FBGA
MB86836
(FPT-176P-M01)
(FPT-144P-M08)
(BGA-144P-M02)
MB86830 Series
2
s
FEATURES
IU (integer unit)
Maximum operating frequency : 120 MHz
SPARC architecture V8E conforming
With 32-bits general register :136 / register window : 8
Instruction cash
The entry lock function is supported
Data cache
No cash controlling function supported
The entry lock function is supported
BIU (bus interface unit)
Purifetchi baffa
:1
Write buffer
:4
The burst mode is supported
Programmable chip selection function :6
Programmable weight state control
:6
For 8/16/32-bits bus
Automatic insertion function of idling cycle after ROM region is accessed
For burst mode ROM
With internal clock multiplication circuit
Sleep mode (low power consumption mode) supported
With DRAM controller (except on the MB86836)
With interrupt request controller (IRC)
On-chip general-purpose 16-bit timer (MB86836 only):1 channel (equivalent to the MB86942)
Support for the JTAG test port (MB86836 only)
MB86830 Series
3
s
PRODUCT LINEUP
*1:MB86836 108 MHz version is under developement.
*2: The general-purpose timer on the MB86836 is a subset of the prescaler-integrated 16-bit timer on the MB86942.
For the type supporting only the internal clock mode, refer to the document for the MB86941/942.
Part number
Item
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
CPU maximum frequency (MHz)
66/80
66/80/100
66
108/120
84
90/108*
1
BUS maximum frequency (MHz)
40
33
40
Ancillary Version Register
(0000)
16
(0001)
16
(0002)
16
(0003)
16
(0004)
16
(0001)
16
Instruction cache
4 KB/2 way 8 KB/2 way 1 KB/Direct 16 KB/2 way 4 KB/2 way 8 KB/2 way
Data cache
2 KB/2 way 8 KB/2 way 1 KB/Direct 16 KB/2 way 2 KB/2 way 8 KB/2 way
Cache size change function
No
8/4/2/1 KB
selectable
No
ADR pin
ADR<27:2>
ADR<23:2> ADR<27:2>
ADR<23:2>
ADR enhancement (ASISEL)
No
ADR<31:2> ADR<27:2> ADR<31:2>
ADR<27:2>
Clock gear function
No
Yes
DSU
No
Yes
No
Yes
No
DRAM controller
4bank
1bank
4bank
1bank
No
JTAG test port
No
Yes
General porpose 16-bit timer*
2
No
1ch
Internal pull-up/down resister pin
P63
P63,
P162 to P164
No
P41 to
P44, P79
Internal power supply (V
DD3
)
3.3 V
2.5 V
3.3 V
2.5 V
I/O power supply (V
DD5
)
3.3 V to 5.0 V
3.3 V
Package
SQFP176
FPT-176P-M01
24
24 mm
LQFP144
FPT-144P-
M08
20
20 mm
SQFP176
FPT-176P-
M01
24
24 mm
LQFP144
FPT-144P-
M08
20
20 mm
LQFP144
FPT-144P-
M08
20
20
mm
FBGA144
BGA-
144P-M02
12
12
mm
MB86830 Series
4
s
FOR PACKAGE AND PART NUMBER
Note:Refer to"PACKAGE DIMENSIONS" for details in each package.
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DIFFERENCES
1.Package
MB86831/832/834 : QFP176
MB86833/835/836 : LQFP144
MB86836 : FBGA144
2.Pin array
MB86831/832/834 : The pin is interchangeable.However, the terminal of MB86834 is the pull-up resistor none.
MB86833/835 : The pin is interchangeable.
MB86836 : MB86833/835, from which DRAMC related pins are deleted and to which one channel of
general-purpose 16-bit timer and the JTAG pin are added.
3.Maximum operation frequency
MB86831 : 66MHz/80MHz
MB86832 : 66MHz/80MHz/100MHz
MB86833 : 66MHz
MB86834 : 108MHz/120MHz
MB86835 : 84MHz
MB86836 : 90MHz/108MHz
4.Power-supply voltage
* : The power-supply voltage is different (Refer to "ELECTRIC CHARACTERISTICS") depending on the condition
of the operation frequency.
5.Cache memory
Package
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
FPT-176P-M01
Yes
Yes
No
Yes
No
No
FPT-144P-M08
No
No
Yes
No
Yes
Yes
BGA-144P-M02
No
No
No
No
No
Yes
Power-supply voltage
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
Internal power-supply
voltage
3.3 V
2.5 V
3.3 V
2.5 V
I/O power-supply voltage
3.3 V or 5.0 V
3.3 V
3.3 V
3.3 V
Cache memory
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
Instruction cash
4 KB/2 way
8 KB/2 way
1 KB/Direct
16 KB/2 way
4 KB/2 way
8 KB/2 way
Data cash
2 KB/2 way
8 KB/2 way
1 KB/Direct
16 KB/2 way
2 KB/2 way
8 KB/2 way
MB86830 Series
5
6.Register
7.Clock gear
MB86832/833/834/835/836 : Supported
MB86831 : No supported
8.External signal
*:RAS1# to RAS3# and DWE1# to DWE3# deletion.
Register name
MB86831/832/833/835/836
MB86834
Instruction Cache Invalidate
Register
(ICINVLD)
Map of
ASI
=
0x0c, ADR
=
0x00001000(Bank1)
ASI
=
0x0c, ADR
=
0x80001000(Bank2)
Map of
ASI
=
0x0c, ADR
=
0x00008000(Bank1)
ASI
=
0x0c, ADR
=
0x80008000(Bank2)
Data Cache Invalidate
Register
(DCINVLD)
Map of
ASI
=
0x0e, ADR
=
0x00001000(Bank1)
ASI
=
0x0e, ADR
=
0x80001000(Bank2)
Map of
ASI
=
0x0e, ADR
=
0x00008000(Bank1)
ASI
=
0x0e, ADR
=
0x80008000(Bank2)
Register name
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
Ancillary Version Register
(VER2)
(00)
16
(01)
16
(02)
16
(03)
16
(04)
16
(01)
16
Item
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
ASISEL pin function
No
Multiplex of
ADR<31:28>
and ASI<3:0>
Multiplex of
ADR<27:24>
and ASI<3:0>
Multiplex of
ADR<31:28>
and ASI<3:0>
Multiplex of ADR<27:24> and
ASI<3:0>
DSU (debugging
support unit)
No
Yes
No
Yes
No
DRAM controller
4Bank
supported
4Bank
supported
1Bank
supported*
4Bank
supported
1Bank
supported*
No
General-purpose
16-bit timer
No
Wih 1ch.
prescaler
(Equivalent to
MB86942)
JTAG
No
Support
Pull-up resistor or
pull-down resistor
Inclusion
Inclusion
No
Inclusion
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