DS04-22001-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP Communication Control
IEEE 1394 Bus Controller
(for MPEG, DVC)
MB86612
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DESCRIPTION
The MB86612 is 1394 serial bus controller exclusively for MPEG and DVC data transfer, compatible with the
IEEE 1394 "FireWire" standard (IEEE Standard 1394-1995). Two built-in ports plus a differential transceiver and
comparator are provided to enable formation of networks in a 1394 cable environment. The MB86612 supports
s100 data transfer speeds.
By integrating the physical layer and link layer on one chip, The MB86612 is designed to reduce mounting area
as well as power consumption.
The MB86612 has an exclusive data port for isochronous transfer, provides automatic packetizing and separation
of header and data units, and is optimized for continuity of transfer processing.
The MB86612 supports MPEG and DVC AV/C protocols, and includes the necessary built-in automatic
operations and CSR's for providing the necessary operations for MPEG and DVC data transfer.
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FEATURES
Compatible with IEEE 1394 high-performance serial bus standards
Physical layer and link layer integrated on one chip
2 cable ports
Supports s100 transfer speed (98.304 Mbit/sec)
3.3V single power supply operation
Built-in PLL (for crystal oscillator) for internal clock signal generation
Power saving modes
1) Forced sleep mode at instruction from MPU
2) Automatic sleep mode for non-connected ports
Header and data units automatically separated at receiving and automatic packetizing for sending
Supports cycle master functions
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PACKAGES
100-pin plastic LQFP
(FPT-100P-M05)
120-pin plastic FBGA
(BGA-120P-M01)
2
MB86612
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Built-in CSR's to provide isochronous resource manager functions
32-bit CRC generation and check functions
General purpose port for asynchronous transfer and control (16-bit MPU bus)
Exclusive built-in ports for isochronous transfer (8-bit bus)
Built-in CRS's and automatic processes to support AV/C protocol (MPEG, DVC)
1) Automatic separation of CIP headers at receiving, and automatic packetizing at sending.
2) Automatic generation of source packet headers (time stamp).
3) Source packet header (time stamp) match detection
4) DBC area automatic increment function
5) Empty packet sending and receiving
6) On-chip PCR (input/output 1 channel each)
7) Each CSR with automatic C&S lock processing and read processing
8) Automatic processing of late packet generation
Compatible with 4-core or 6-core cables
Packages: LQFP-100, FBGA-120
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