AE3E
FUJITSU SEMICONDUCTOR
DATA SHEET
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (
8/
16) FLASH MEMORY &
4M (
8/
16) STATIC RAM
MB84VD2118XA
-85
/MB84VD2119XA
-85
s
FEATURES
Power supply voltage of 2.7 to 3.6 V
High performance
85 ns maximum access time
Operating Temperature
25 to +85
C
Package 69-ball BGA , 56-pin TSOP
-- FLASH MEMORY
Simultaneous Read/Write operations (dual bank)
Miltiple devices available with different bank sizes (Refer to Table 1)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
Minimum 100,000 write/erase cycles
Sector erase architecture
Eight 4 K words and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
MB84VD2118XA: Top sector
MB84VD2119XA: Bottom sector
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
Low V
CC
write inhibit
2.5 V
Hidden ROM (Hi-ROM) region
64K byte of Hi-ROM, accessible through a new "Hi-ROM Enable" command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
(Continued)
2
MB84VD2118XA
-85
/MB84VD2119XA
-85
(Continued)
WP/ACC input pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2118XA:SA37,SA38 MB84VD2119XA:SA0,SA1)
At V
IH
, allows removal of boot sector protection
At V
ACC
, program time will reduse by 40%.
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
Please refer to "MBM29DL16XTD/BD" data sheet in detailed function
-- SRAM
Power dissipation
Operating : 40 mA max.
Standby : 7
A max.
Power down features using CE1s and CE2s
Data retention supply voltage: 1.5 V to 3.6 V
CE1s and CE2s Chip Select
Byte data control: LBs(DQ
0
-DQ
7
), UBs(DQ
8
-DQ
15
)
s
BLOCK DIAGRAM
V
SS
V
CC
s
16 M bit
RESET
Flash Memory
WE
4 M bit
Static RAM
CEf
A
0
to A
19
OE
CE1s
V
SS
V
CC
f
A
0
to A
19
A
0
to A
17
DQ
0
to DQ
15
/A
1
RY/BY
LBs
UBs
CIOf
WP/ACC
CE2s
DQ
0
to DQ
15
/A
1
DQ
0
to DQ
15
A
1
SA
CIOs
5
MB84VD2118XA
-85
/MB84VD2119XA
-85
s
PRODUCT LINE UP
Flash Memory
SRAM
Ordering Part No.
V
CC
= 3.0 V
MB84VD2118XA-85/MB84VD2119XA-85
Max. Address Access Time (ns)
85
85
Max. CE Access Time (ns)
85
85
Max. OE Access Time (ns)
35
45
Table 1 Pin Configuration
Pin
Function
Input/
Output
A
0
to A
17
Address Inputs (Common)
I
A
1
, A
18
to A
19
Address Input (Flash)
I
SA
Address Input (SRAM)
I
DQ
0
to DQ
15
Data Inputs/Outputs (Common)
I/O
CEf
Chip Enable (Flash)
I
CE1s
Chip Enable (SRAM)
I
CE2s
Chip Enable (SRAM)
I
OE
Output Enable (Common)
I
WE
Write Enable (Common)
I
RY/BY
Ready/Busy Outputs (Flash) Open Drain Output
O
UBs
Upper Byte Control (SRAM)
I
LBs
Lower Byte Control (SRAM)
I
CIOf
I/O Configulation (Flash)
CIOf = V
IH
is Word mode (16), CIOf = V
IL
is Byte mode (8)
I
CIOs
I/O Configulation (SRAM)
CIOs = V
IH
is Word mode (16), CIOs = V
IL
is Byte mode (8)
I
RESET
Hardware Reset Pin/Sector Protection Unlock (Flash)
I
WP/ACC
Write Protect / Accelaration (Flash)
I
N.C.
No Internal Connection
--
V
SS
Device Ground (Common)
Power
V
CC
f
Device Power Supply (Flash)
Power
V
CC
s
Device Power Supply (SRAM)
Power
+0.6 V
0.3 V
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