DS05-50306-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (
8/
16) FLASH MEMORY &
2M (
8/
16) STATIC RAM
MB84VD2108XEM
-70
/MB84VD2109XEM
-70
s
FEATURES
Power Supply Voltage of 2.7 V to 3.3 V
High Performance
70 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
Operating Temperature
40
C to +85
C
Package 56-ball BGA
(Continued)
s
PRODUCT LINE UP
Note: Both V
CC
f and V
CC
s must be in recommended operation range when either part is being accessed.
s
PACKAGE
Part No.
MB84VD2108XEM/MB84VD2109XEM
Supply Voltage(V)
V
CC
f= 3.0 V
V
CC
s= 3.0 V
Max Address Access Time (ns)
70
70
Max CE Access Time (ns)
70
70
Max OE Access Time (ns)
30
35
56-ball plastic BGA
(BGA-56P-M02)
+0.3 V
0.3 V
+0.3 V
0.3 V
MB84VD2108XEM/2109XEM
-70
2
(Continued)
FLASH MEMORY
Simultaneous Read/Write Operations (Dual Bank)
Miltiple devices available with different bank sizes (Please refer to ORDERING INFORMATION)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
Minimum 100,000 Write/Erase Cycles
Sector Erase Architecture
Eight 4 K words and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
MB84VD2108XEM: Top sector
MB84VD2109XEM: Bottom sector
Embedded Erase
TM
* Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program
TM
* Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
Low V
CC
Write Inhibit
2.5 V
HiddenROM Region
64K byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
WP/ACC Input Pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2108XEM:SA37,SA38 MB84VD2109XEM:SA0,SA1)
At V
IH
, allows removal of boot sector protection
At V
ACC
, program time will reduse by 40%.
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
Please refer to "MBM29DL16XTE/BE" Datasheet in Detailed Function
* :
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
SRAM
Power Dissipation
Operating : 40 mA Max
Standby
: 7
A Max
Power Down Features using CE1s and CE2s
Data Retention Supply Voltage: 1.5 V to 3.3 V
CE1s and CE2s Chip Select
Byte Data Control: LB (DQ
7
to DQ
0
), UB (DQ
15
to DQ
8
)
MB84VD2108XEM/2109XEM
-70
4
s
PIN DESCRIPTION
Pin Name
Function
Input/Output
A
16
to A
0
Address Inputs (Common)
I
A
19
to A
17
, A
-1
Address Input (Flash)
I
SA
Address Input (SRAM)
I
DQ
15
to DQ
0
Data Inputs / Outputs (Common)
I/O
CEf
Chip Enable (Flash)
I
CE1s
Chip Enable (SRAM)
I
CE2s
Chip Enable (SRAM)
I
OE
Output Enable (Common)
I
WE
Write Enable (Common)
I
RY/BY
Ready/Busy Outputs (Flash) Open Drain
Output
O
UB
Upper Byte Control (SRAM)
I
LB
Lower Byte
Control (SRAM)
I
CIOf
I/O Configuration (Flash)
CIOf
=
V
CC
f
is Word mode (
16
),
CIOf
=
V
SS
is Byte mode (
8
)
I
CIOs
I/O Configuration (SRAM)
CIOs
=
V
CC
s
is Word mode (
16),
CIOs
=
V
SS
is Byte mode (
8)
I
RESET
Hardware Reset Pin / Sector Protection Un-
lock (Flash)
I
WP/ACC
Write Protect / Acceleration (Flash)
I
N.C.
No Internal Connection
--
V
SS
Device Ground (Common)
Power
V
CC
f
Device Power Supply (Flash)
Power
V
CC
s
Device Power Supply (SRAM)
Power
PDF 
ZIP
