DS05-11416-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY Mobile FCRAM
TM
CMOS
16 Mbit (1 M word
16 bit)
Mobile Phone Application Specific Memory
MB82D01171B
-60L
/
-60LL
/
-70L
/
-70LL
CMOS 1,048,576-WORD
16 BIT
Fast Cycle Random Access Memory
with Low Power SRAM Interface
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DESCRIPTION
The Fujitsu MB82D01171B is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static
Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. This
MB82D01171B is suited for mobile applications such as Cellular Handset and PDA.
Note: FCRAM is a trademark of Fujitsu Limited, Japan.
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PRODUCT LINEUP
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PACKAGES
Parameter
MB82D01171B
60L
60LL
70L
70LL
Access Time (t
AA
Max, t
CE
Max)
60 ns
70 ns
Active Current (I
DDA1
Max)
20 mA
Standby Current (I
DDS1
Max)
100
A
70
A
100
A
70
A
Power Down Current (I
DDP
Max)
10
A
48-ball plastic FBGA
(BGA-48P-M18)
MB82D01171B
-60L/-60LL/-70L/-70LL
2
s
FEATURES
Asynchronous SRAM Interface
1 M word
16 bit Organization
Fast Random Access Time : t
AA
=
t
CE
=
60 ns, 70 ns
Low Power Consumption : I
DDS1
=
100
A (L version) , 70
A (LL version)
Wide Operating Conditions : V
DD
=
+
2.3 V to
+
2.7 V
+
2.7 V to
+
3.1 V
+
3.1 V to
+
3.5 V
T
A
=
-
30
C to
+
85
C
Byte Write Control
8 words Address Access Capability
Power Down Control by CE2
MB82D01171B
-60L/-60LL/-70L/-70LL
3
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PIN ASSIGNMENTS
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PIN DESCRIPTION
Pin Name
Description
A
19
to A
0
Address Input
CE1
Chip Enable (Low Active)
CE2
Chip Enable (High Active)
WE
Write Enable (Low Active)
OE
Output Enable (Low Active)
LB
Lower Byte Write Control (Low Active)
UB
Upper Byte Write Control (Low Active)
DQ
8
to DQ
1
Lower Byte Data Input/Output
DQ
16
to DQ
9
Upper Byte Data Input/Output
V
DD
Power Supply
V
SS
Ground
NC
No Connection
A
B
C
D
E
F
G
H
LB
DQ
9
DQ
10
V
SS
V
DD
DQ
15
DQ
16
A
18
OE
UB
DQ
11
DQ
12
DQ
13
DQ
14
A
19
A
8
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
A
2
CE1
DQ
2
DQ
4
DQ
5
DQ
6
WE
A
11
CE2
DQ
1
DQ
3
V
DD
V
SS
DQ
7
DQ
8
NC
1
6
5
4
3
2
(TOP VIEW)
(BGA-48P-M18)
MB82D01171B
-60L/-60LL/-70L/-70LL
4
s
s
s
s
BLOCK DIAGRAM
V
DD
V
SS
CE2
CE1
WE
LB
UB
OE
A
19
to A
0
DQ
8
to DQ
1
DQ
16
to DQ
9
Address
Latch &
Buffer
Row
Decoder
Memory
Cell
Array
16,777,216 bit
I/O
Buffer
Input Data
Latch &
Control
Sense /
Switch
Output
Data
Control
Column /
Decoder
Address
Latch &
Buffer
Power
Control
Timing
Control
MB82D01171B
-60L/-60LL/-70L/-70LL
5
s
s
s
s
FUNCTION TRUTH TABLE
Note : L
=
Logic Low, H
=
Logic High, X
=
either "L" or "H", High-Z
=
High Impedance
*1 : Output Disable mode should not be kept longer than 1
s.
*2 : Byte control at Read mode is not supported.
*3 : Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
*4 : Either or both LB and UB must be Low for Read operation.
*5 : Can be either V
IL
or V
IH
but must be valid before Read or Write.
Mode
CE2
CE1
WE
OE
LB
UB
A
19
to A
0
DQ
8
to DQ
1
DQ
16
to DQ
9
I
DD
Data
Retention
Standby (Deselect)
H
H
X
X
X
X
X
High-Z
High-Z
I
DDS
Yes
Output Disable*
1
L
H
H
X
X
*5
High-Z
High-Z
I
DDA
No Read
H
L
H
H
Valid
High-Z
High-Z
Read*
2
L *
4
L *
4
Valid
Output
Valid
Output
Valid
Write (Upper Byte)
L
H
H
L
Valid
Invalid
Input
Valid
Write (Lower Byte)
L
H
Valid
Input
Valid
Invalid
Write
(Word) L
L
Valid
Input
Valid
Input
Valid
Power Down *
3
L
X
X
X
X
X
X
High-Z
High-Z
I
DDP
No
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