DS05-11411-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
2
1 M
32-BIT
SINGLE DATA RATE I/F FCRAM
TM
Consumer/Embedded Application Specific Memory for SiP
MB81ES653225-12/-12L
CMOS 2-Bank
1,048,576-Word
32-Bit
Fast Cycle Random Access Memory (FCRAM) with Single Data Rate for SiP
DESCRIPTION
The Fujitsu MB81ES653225 is a Single Data Rate Interface Fast Cycle Random Access Memory (FCRAM*)
containing 67,108,864 memory cells accessible in a 32-bit format. The MB81ES653225 features a fully synchro-
nous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence.
The MB81ES653225 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power
consumption and low voltage operation than regular synchronous DRAM (SDRAM) .
The MB81ES653225 is dedicated for SiP (System in a package) , and ideally suited for various embedded/
consumer applications including digital AVs and image processing where a large band width and low power
consumption memory is needed.
* : FCRAM is a trademark of Fujitsu Limited, Japan.
PRODUCT LINE
Parameter
MB81ES653225
12
12L
Clock Frequency (Max)
CL
=
2
54.0 MHz
CL
=
3
85.0 MHz
Burst Mode Cycle Time (Min)
CL
=
2
18.5 ns
CL
=
3
11.7 ns
Access Time from Clock (Max)
CL
=
2
12 ns
CL
=
3
8.7 ns
Operating Current (Max) (32 page length)
35 mA
Power Down Mode Current (Max)
0.5 mA
0.1 mA
Self Refresh Current (Max) (Ta
=
+
85
C) 1000
A
450
A
MB81ES653225-12/-12L
2
FEATURES
1 M word
32 bit
2 banks organization
Low power supply
- V
DD
:
+
1.8 V
0.15 V
- V
DDQ
:
+
1.8 V
0.15 V
1.8 V-CMOS I/O interface
8 K refresh cycles every 32 ms
Auto-and Self-refresh
Two banks operation
Burst read/write operation and burst read/single write operation capability
Programmable burst type, burst length, and CAS Latency
Programmable page length function
Programmable Partial Array Self Refresh (PASR)
Programmable Temperature Compensated Self Refresh (TCSR)
Deep power down mode
Extended temperature operation
- MB81ES653225-12 : From 0
C to
+
85
C (Ta)
- MB81ES653225-12L : From
-
25
C to
+
85
C (Ta)
CKE power down mode
Output enable and input data mask
Disable function for TEST
Self burnin function for TEST
Built In Self Test (BIST) function for TEST
MB81ES653225-12/-12L
3
PAD LAYOUT
VDD
VSS
CKE
CLK
CSB
RASB
CASB
WEB
BA
A11
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
DQM0
DQM2
VDDQ
VSSQ
DQ0
DQ1
DQ2
DQ3
VDDQ
VSSQ
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
VDDQ
VSSQ
DQ20
DQ21
DQ22
DQ23
VDD
VSS
VDD
VSS
A9
A12
A13
TBST
A14
BME
DQM1
DQM3
VDDQ
DSE
VSSQ
DQ8
DQ9
DQ10
DQ11
VDDQ
VSSQ
DQ12
DQ13
DQ14
DQ15
DQ24
DQ25
DQ26
DQ27
VDDQ
VSSQ
DQ28
DQ29
DQ30
DQ31
VDD
VSS
Pad No. 137
Pad No. 72
Pad No. 1
Pad No. 71
MB81ES653225-12/-12L
4
PAD DESCRIPTIONS
* : A
13
must be connected to V
SS
in 128 page length mode. A
14
must be connected to V
SS
in 128 page length
mode and 64 page length mode.
Symbol
Function
V
DDQ
, V
DD
Supply Voltage
DQ
31
to DQ
0
Data I/O
V
SSQ
, V
SS
Ground
WE (WEB)
Write Enable
CAS (CASB)
Column Address Strobe
RAS (RASB)
Row Address Strobe
CS (CSB)
Chip Select
BA
Bank Select (Bank Address)
AP
Auto Precharge Enable
A
14
to A
0
*
Address Input
Row
Column
128 page
A
12
to A
0
A
6
to A
0
64 page
A
13
to A
0
A
5
to A
0
32 page
A
14
to A
0
A
4
to A
0
CKE
Clock Enable
CLK
Clock Input
DQM
3
to DQM
0
Input Mask/Output Enable
DSE
Disable Mode Entry (apply V
SS
except Disable Mode)
BME
Self Burn-in Mode Entry (apply V
SS
except Self Burn-in Mode)
TBST
BIST Mode Entry (apply V
SS
except BIST Mode)
Don't Bond
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