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Электронный компонент: MB811L323229-12

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DS05-11410-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
2
512K
32-BIT
SINGLE DATA RATE I/F FCRAM
TM
Consumer/Embedded Application Specific Memory for SiP
MB811L323229-12/18
s
DESCRIPTION
The Fujitsu MB811L323229 is a Single Data Rate Interface Fast Cycle Random Access Memory (FCRAM*)
containing 33,554,432 memory cells accessible in a 32-bit format. The MB811L323229 features a fully synchro-
nous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence.
The MB811L323229 is utilized using Fujitsu advanced FCRAM core technology and designed for low power
consumption and low voltage operation than regular synchronous DRAM (SDRAM).
The MB811L323229 is dedicated for SiP (System in a package), and ideally suited for various embedded/
consumer applications including digital AVs and image processing where a large band width and low power
consumption memory is needed.
*: FCRAM is a trademark of Fujitsu Limited, Japan.
s
PRODUCT LINE
Parameter
MB811L323229-12
MB811L323229-18
Clock Frequency
81 MHz Max
54 MHz Max
CL - t
RCD
- t
RP
CL = 2
2 - 2 - 2 clk Min
2 - 2 - 2 clk Min
Burst Mode Cycle Time
CL = 2
12 ns Min
18 ns Min
Access Time from Clock
CL = 2
9 ns Max
9 ns Max
Operating Current
120mA Max
80mA Max
Power Down Mode Current (I
CC2PS
)
1 mA Max
1 mA Max
Self Refresh Current (I
CC6
)
2.5 mA Max
2.5 mA Max
MB811L323229-12/18
2
s
FEATURES
V
CCQ
: +3.3V Supply 0.3V tolerance or +2.5V Supply 0.2V tolerance
V
DD
: +2.5 V Supply 0.2 V tolerance
LVCMOS compatible I/O interface
2 K refresh cycles every 32 ms
Two bank operation (512 K word
32 bit
2 bank)
Burst read/write operation and burst read/single write operation capability
Programmable burst type and burst length
Burst type : Sequential Mode, Interleave Mode
Burst length : BL
=
1, 2, 4, 8, full column (256)
CAS latency
=
2
Auto-and Self-refresh
CKE power down mode
Byte control with DQM
0
to DQM
3
MB811L323229-12/18
3
s
PAD LAYOUT
PA
D
BME
V
SS
V
DD
DQ
24
DQ
23
V
SSQ
V
CCQ
DQ
25
DQ
22
DQ
26
DQ
21
DQ
27
DQ
20
DQ
28
DQ
19
DQ
29
DQ
18
DQ
30
DQ
17
V
CCQ
V
SSQ
DQ
31
DQ
16
V
SSI
V
SS
V
DDI
V
DD
DQM
3
DQM
2
DSE
A
3
A
2
A
4
A
1
A
5
A
0
A
6
A
10
/AP
A
7
V
SS
V
DD
A
8
BA
A
9
CKE
CSB
CLK
RASB
CASB
WEB
DQM
1
DQM
0
V
SSI
V
SS
V
DDI
V
DD
DQ
8
DQ
7
V
CCQ
V
SSQ
DQ
9
DQ
6
DQ
10
DQ
5
DQ
11
DQ
4
DQ
12
DQ
3
DQ
13
DQ
2
DQ
14
DQ
1
V
SSQ
V
CCQ
DQ
15
DQ
0
V
SS
V
DD
PADNo.88
PADNo.1
MB811L323229-12/18
4
s
PAD DESCRIPTIONS
Symbol
Function
V
CCQ
, V
DD
, V
DDI
Supply Voltage
DQ
0
to DQ
31
Data I/O
V
SS
, V
SSQ,
V
SSI
Ground
--
Don't Bond
WE(WEB)
Write Enable
CAS(CASB)
Column Address Strobe
RAS(RASB)
Row Address Strobe
CS(CSB)
Chip Select
BA
Bank Select (Bank Address)
AP
Auto Precharge Enable
A
0
to A
10
Address Input
Row: A
0
to A
10
Column: A
0
to A
7
CKE
Clock Enable
CLK
Clock Input
DQM
0
to DQM
3
Data Input /Output Mask
DSE
Disable (apply V
SS
except DISABLE mode)
BME
Burn in Mode Entry (apply V
SS
except Burn in mode)
MB811L323229-12/18
5
s
BLOCK DIAGRAM
CLK
RAS
CAS
WE
DSE
RAS
CAS
WE
DQM0 ~
DQM3
DQ
0
~
DQ
31
A
0
~ A
9
,
A
10
/AP
BA
I/O
V
CCQ
V
DDI
V
DD
CKE
BME
CS
V
SS
V
SSI
V
SSQ
MB811L323229 BLOCK DIAGRAM
BANK-1
COMMAND
DECODER
CLOCK
BUFFER
ADDRESS
BUFFER/
REGISTER
I/O DATA
BUFFER/
REGISTER
MODE
REGISTER
FCRAM
CORE
(2,048
256
32)
COL.
ADDR.
BANK-0
ROW
ADDR.
To each block
CONTROL
SIGNAL
LATCH
COLUMN
ADDRESS
COUNTER