Sept. 1995
Edition 1.0a
DATA SHEET
Copyright
1992 by FUJITSU LIMITED
1
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 400MHz PRESCALER
The Fujitsu MB1514 is a dual serial input PLL (phase locked loop) frequency syn-
thesizer designed for cordless telephone applications.
The MB1514 has two PLL circuits on a single chip; one for transmission (PLL-1)
and the other for reception (PLL-2). Separate power supply pins are provided for
each PLL circuit. Transmission PLL contains a low sensitivity charge pump for
modulation, and reception PLL contains a high sensitivity charge pump for fast
lock-up time. 400MHz dual modulus prescalers are provided and enables a pulse
swallow function.
MB1514 operates at 3.0 V typ. power supply voltage and dissipates 8mA typ. of
current realized through the use of Bi-CMOS technology.
FEATURES
Low voltage operation : Vcc = 2.2V to 4.2V
High operating frequency : fin = 400MHz (Pin = 10dBm, Vcc = 3.0V)
Low current consumption : Icc = 8mA typ. (Vcc = 3V)
Power saving function
Two charge pumps
Low sensitivity charge pump for transmission (PLL-1)
High sensitivity charge pump for reception (PLL-2)
Plastic 20-pin DIP package (Suffix: -P)
Plastic 20-pin SOP package (Suffix: -PF)
MB1514
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
PLASTIC PACKAGE
DIP20PM02
ABSOLUTE MAXIMUM RATINGS
FPT20PM01
NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit.
Symbol
V
CC
V
O1
V
O2
I
O
T
STG
Value
0.5 to +6.0
0.5 to V
CC
+0.5
0.5 to +6.0
10
55 to +125
Unit
V
V
V
mA
C
Ratings
Supply Voltage
PIN ASSIGNMENT
Output Current
Storage Temperature
Output
Voltage
OSC
OUT
, D
O
, BS
LD, LF
O
DIP20PM02/
FPT20PM01
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Clock
Data
LE
fin
2
V
CC2
PS
LF
O2
LF
I2
D
O2
BS
2
GND
OSC
IN
OSC
OUT
f
in1
V
CC1
LD
LF
O1
LF
I1
D
O1
BS
1
PLASTIC PACKAGE
MB1514
2
Phase detector
(PLL2)
Binary 11-bit program-
mable counter (PLL2)
BLOCK DIAGRAM
4
20-bit latch (PLL1)
Binary 7-bit swallow
counter (PLL1)
Binary 11-bit program-
mable counter (PLL1)
Phase detector
(PLL1)
Charge
pump
(PLL-1)
7
8
LD/fr/fp1/fp2
selector
2
3
Reference counter
(5121024)
17
Prescaler
(PLL2)
20-bit latch (PLL2)
Binary 7-bit swallow
counter (PLL2)
Charge
pump
(PLL-2)
Crystal
oscillation
circuit
9
10
6
12
11
18
Schmitt
circuit
19
Schmitt
circuit
20
Schmitt
circuit
C
N
T
23-bit shift
register
Latch selection
circuit
14
13
1
15
Power saving
Crystal oscillatio
and PLL2 circui
become inactive
PS
V
CC2
16
GND
LF
I2
LF
O2
BS
2
D
O2
LD
BS
1
D
O1
LF
I1
LF
O1
fin
1
OSC
IN
OSC
OUT
fin
2
LE
Data
Clock
5
LD
LE
2
LD
1
LD
1
/LD
2
FC
2
FC
1
F
P1
F
P2
V
CC1
NOTE;
PLL1 : Transmission section
PLL2 : Reception section
Prescaler
(PLL1)
MB1514
3
BLOCK DESCRIPTIONS
TRANSMISSION/RECEPTION BLOCK
20-bit latch
Programmable divider;
Binary 7-bit swallow counter (Divide ratio: 0 to 127)
Binary 11-bit programmable counter (Divide ratio: 16 to 2047)
The programmable dividers for transmission and reception are able to be controlled independently.
Phase detectors with phase polarity change function
400MHz dual modulus prescalers (Divide ratio: 64/65)
Charge pumps
Transistors for LPFs
Analog swithes
23-bit shift register
Reference divider;
Reference counter (Divide ratio: 1700)
(Divide frequency = 12.5 kHz (Crystal oscillator frequency = 12.8 kHz))
COMMON BLOCK
Crystal oscillation circuit
Latch selector
Shmitt circuits
LD/fr/fp output selector
MB1514
4
PIN DESCRIPTIONS
Pin No.
Symbol
I/O
1
GND
Ground.
2
OSC
IN
I
I
nput and output of a reference divider and a crystal is externally connected between these
3
OSC
OUT
O
pins.
4
fin
1
I
Input of a prescaler of PLL-1 (Transmission section).
Connection with a VCO should be AC (capacitor) coupling.
5
V
CC1
Power supply for PLL-1 block.
When power is cut off, PLL-1 block's latched data is cancelled.
6
LD
O
Output of lock detectors, a reference divider, and programmable dividers.
Output data is selected by data setting of LD bits in the serial data. This is open-drain output.
7
LF
O1
O
Output of the transistor, used for transmission LPF.
8
LF
I1
I
Input of the transistor, used for transmission LPF.
9
D
O1
O
Output of the charge pump(PLL-1).
Phase polarity is inverted by FC bit setting in the serial data.
10
BS
1
O
Output of the analog switch(PLL-1).
Usually this pin is high-impedance state. When LE is set to high, the state of the internal
charge pump is output.
11
BS
2
O
Output of the analog switch(PLL-2: reception section).
Usually this pin is high-impedance state. When LE is set to high, the state of the internal
charge pump is output.
12
D
O2
O
Output of the charge pump(PLL-2).
Phase polarity is inverted by FC bit setting in the serial data.
13
LF
I2
I
Input of the transistor which is used for reception LPF.
14
LF
O2
O
Output of the transistor which is used for reception LPF.
15
PS
I
Power saving control for PLL-2 circuits.
PS
H
L
Active state
Power saving state
(Crystal oscillation circuit and PLL2 circuits are
inactive)
State
Pin Descriptions
MB1514
5
PIN DESCRIPTIONS
Pin No.
Symbol
I/O
16
V
CC2
Power supply for PLL-2 circuits, a reference counter, a shift register, and a crystal oscillation
circuit. When power is cut off, PLL-2 block's and reference counter's latched data are
cancelled.
17
fin
2
I
Input of a prescaler of PLL-2.
Connection with a VCO should be AC (capacitor) coupling.
18
LE
I
Load enable signal input. This pin involves a schmitt trigger circuit.
When this pin is high (LE="H"), the data stored in a shift register is transferred into the latch
according to the control bit in the serial data.
And at the moment, internal analog switch is closed(ON), then each charge pump output
signal is output through the BS pin.
19
Data
I
Serial data input. This pin involves a schmitt trigger circuit.
The stored data in the shift register is transferred to either transmission or reception sections
depending upon the control bit as follows.
20
Clock
I
Clock input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
Each rising edge of the clock shifts one bit of data into the shift register.
Control bit data
H
L
Latch of PLL-1 (transmission)
Latch of PLL-2 (reception)
The destination of data
FUNCTIONAL DESCRIPTIONS
Divide ratio can be set using the following equation:
f
VCO
= { (M x N) + A} x f
OSC
R (A < N)
f
VCO
: Output frequency of an external voltage controlled oscillator (VCO)
M:
Preset divide ratio of an internal dual modulus prescaler (64)
N:
Preset divide ratio of binary 12-bit programmable counter (16 to 2047)
A:
Preset divide ratio of binary 5-bit swallow counter (0
A
127)
f
OSC
: Output frequency of the external reference frequency oscillator
R:
Preset divide ratio of reference counter (1700)
Pin Descriptions
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