Coypright
1990 by FUJITSU LIMITED
LOW POWER SERIAL INPUT PLL SYNTHESIZER
WITH 1.1 GHz PRESCALER
The Fujitsu MB1502, utilizing BI-CMOS technology, is a single chip serial input PLL
synthesizer with pulse-swallow function. The MB1502 contains a 1.1GHz two
modulus prescaler that can select of either 64/65 or 128/129 divide ratio, control
signal generator, 16-bit shift register, 15-bit latch, programmable reference divider
(binary 14-bit programmable reference counter), 1-bit switch counter, phase
comparator with phase conversion function, charge pump, crystal oscillator, 19-bit
shift register, 18-bit latch, programmable divider (binary 7-bit swallow counter and
binary 11-bit programmable counter) and analog switch to speed up lock up time.
It operates supply voltage of 5V typ. and achieves very low supply current of 8mA typ.
realized through the use of Fujitsu Advanced Process Technology.
FEATURES
High operating frequency: f
IN MAX
=1.1GHz (V
IN MIN
=10dBm)
Pulse swallow function: 64/65 or 128/129
Low supply current: I
CC
=8mA typ.
Serial input 18-bit programmable divider consisting of:
-- Binary 7-bit swallow counter: 0 to 127
-- Binary 11-bit programmable counter: 16 to 2047
Serial input 15-bit programmable reference divider consisting of:
-- Binary 14-bit programmable reference counter: 8 to 16383
-- 1-bit switch counter (SW) sets divide ratio of prescaler
On-chip analog switch achieves fast lock up time
2 types of phase detector output
-- On-chip charge pump (Bipolar type)
-- Output for external charge pump
Wide operating temperature: 40
_
C to +85
_
C
16-pin Plastic DIP Package (Suffix: --P)
16-pin Plastic Flat Package (Suffix: --PF)
ABSOLUTE MAXIMUM RATINGS
(See NOTE)
RatIng
Symbol
Value
Unit
Power Supply Voltage
V
CC
0.5 to +7.0
V
Power Supply Voltage
V
P
V
CC
to 10.0
V
Output Voltage
V
OUT
0.5 to V
CC
+0.5
V
Open-drain Voltage
V
OOP
0.5 to 0.8
V
Output Current
I
OUT
10
mA
Storage Temperature
T
STG
55 to +125
_
C
NOTE:
Permanent device damage may occur if the above Absolute Maximum RatIngs are exceed-
ed.Functional operation should be restricted to the condItions as detailed in the operational
sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DATA SHEET
November 1990
Edition 5.0
MB1502
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
Pin Assignment
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages
to this high impedance circuit.
Plastic Package
DIP-16P-M04
Plastic Package
FPT-16PM06
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OSC
IN
OSC
OUT
V
P
V
CC
D
O
GND
LD
f
IN
f
OUT
BiSW
FC
LE
Data
Clock
R
P
MB1502
2
MB1502 Block Diagram
Crystal
Oscillator
Circuit
11
1
4
6
2
16-Bit Shift Register
16-Bit Shift Register
15-Bit Latch
15-Bit Latch
Programmable
Reference Divider
Binary 14-Bit
Reference Counter
1-bit
SW
19-Bit Shift Register
19-Bit Shift Register
8
10
18-Bit Latch
7-Bit Latch
11-Bit Latch
Binary 7-Bit
Swallow Counter
9
Prescaler
Circuit
Control
1-Bit Latch
Binary 11-Bit
Programmable Counter
Control Circuit
Programmable Divider
Charge
Pump
Phase
Comparator
16
15
12
7
13
3
5
14
f
OUT
D
O
V
P
P
R
LD
FC
BiSW
V
CC
GND
LE
OSC
IN
OSC
OUT
f
in
Data
Clock
MB1502
3
PIN DESCRIPTION
Pin
No.
Pin
Name
I/O
Description
1
2
OSC
IN
OSC
OUT
I
O
Oscillator input.
Oscillator output.
A crystal is placed between OSC
IN
and OSC
OUT
.
3
V
P
--
Power supply input for charge pump and analog switch.
4
V
CC
--
Power supply voltage input.
5
D
O
O
Charge pump output.
The characteristics of charge pump is reversed depending upon FC input.
6
GND
--
Ground
7
LD
O
Phase comparator output.
Normally this pin outputs high level. While the phase difference of f
r
, and f
p
exists, this
pin outputs low level.
8
f
IN
l
Prescaler input.
The connection with an external VCO should be AC connection.
9
Clock
I
Clock input for 19-bit shift register and 16-bit shift register.
On rising edge of the clock shifts one bit of data into the shift registers.
10
Data
l
Binary serial data input.
The last bit of the data is a control bit which specified destination of shift registers.
When this bit is high level and LE is high level, the data stored in shift register is transferred to 15-bit latch.
When this bit is low level and LE is high level, the data is transferred to 18-bit latch.
11
LE
I
Load enable input (with internal pull up resistor).
When LE is high or open, the data stored in shift register is transferred into latch depending upon the control
bit. At the time, internal charge pump output to be connected to BISW pin because internal analog switch
becomes ON state.
12
FC
l
Phase select input of phase comparator (with internal pull up resistor).
When FC is low level, the characteristics of charge pump, phase comparator is reversed.
FC input signal is also used to control f
OUT
pin (test pin) output level for f
r
or f
p
.
13
BISW
O
Analog switch output.
Usually BISW pin is set high-impedance state. When internal analog switch is ON (LE pin is high level), this
pin outputs internal charge pump state.
14
f
OUT
O
Monitor pin of phase comparator input.
f
OUT
pin outputs either programmable reference divider output (f
r
) or programmable divider output (f
p
)
depending upon FC pin input level.
15
16
P
R
O
O
Outputs for external charge pump.
The characteristics are reversed according to FC input.
P pin is N-channel open drain output.
MB1502
4
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable
reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored
data is transferred into latch depending upon the control bit.
Control data "H" data is transferred into 15-bit latch.
Control data "L" data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is
shown below.
Control bit
Divide ratio of prescaler setting bit
LSB
MSB
C
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
W
Divide ratio of programmable reference counter setting bit
14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide
Ratio
R
S
14
S
13
S
12
S
11
S
10
S
9
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
9
0
0
0
0
0
0
0
0
0
0
1
0
0
1
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NOTES: Divide ratio less than 8 is prohibited.
Divide ratio: 8 to 16383
SW: This bit selects divide ratio of prescaler.
SW=H : 64
SW=L :128
S1 to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets as high level).
Data is input from MSB side.
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown on following page.
MB1502
5
Control bit
LSB
MSB
C
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
1
0
S
1
1
S
1
2
S
1
3
S
1
4
S
1
5
S
1
6
S
1
7
S
1
8
Divide ratio of programmable
counter setting bit
Divide ratio of swallow
counter setting bit
7-BIT SWALLOW COUNTER DIVIDE RATIO
Divide
Ratio
A
S
7
S
6
S
5
S
4
S
3
S
2
S
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
127
1
1
1
1
1
1
1
NOTE:
Divide ratio: 0 to 127
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide
Ratio
N
S
1
8
S
1
7
S
1
6
S
1
5
S
1
4
S
1
3
S
1
2
S
1
1
S
1
0
S
9
S
8
16
0
0
0
0
0
0
1
0
0
0
1
17
0
0
0
0
0
0
1
0
0
0
1
2047
1
1
1
1
1
1
1
1
1
1
1
NOTES: Divide ratio less than 16 is prohibited.
Divide ratio: 16 to 2047
S1 to S7: Swallow counter divide ratio setting bit. (0 to 127)
S8 to S18: Programmable counter divide ratio setting bit. (16 to 2047)
C: Control bit (sets as low level).
Data is input from MSB side.
PULSE SWALLOW FUNCTION
f
vco
=
[(PxN)+A] x f
osc
R
f
VCO
:
Output frequency of external voltage controlled oscillator (VCO)
N:
Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A:
Preset divide ratio of binary 7-bit swallow counter (0
A
127, A<N)
f
OSC
:
Output frequency of the external reference frequency oscillator
R:
Preset divide ratio of binary 14-bit programmable reference counter (8 to 16383)
P:
Preset modulus of external dual modulus prescaler (64 or 128)
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