MC100ES6220
Rev 4, 04/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
Low Voltage Dual 1:10 Differential
ECL/PECL Clock Fanout Buffer
The MC100ES6220 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6220
supports various applications that require the distribution of precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low skew outputs and superior digital signal
characteristics. Target applications for this clock driver are high performance
clock distribution in computing, networking and telecommunication systems.
Features
Two independent 1:10 differential clock fanout buffers
130 ps maximum device skew
SiGe technology
Supports DC to 1 GHz operation of clock or data signals
ECL/PECL compatible differential clock outputs
ECL/PECL compatible differential clock inputs
Single 3.3 V, 3.3 V, 2.5 V or 2.5 V supply
Standard 52-lead LQFP package with exposed pad for enhanced thermal
characteristics
Supports industrial temperature range
Pin and function compatible to the MC100EP220
52-lead Pb-free Package Available
Functional Description
The MC100ES6220 is designed for low skew clock distribution systems and
supports clock frequencies up to 1 GHz. The device consists of two independent
clock fanout buffers. The CLKA and CLKB inputs can be driven by ECL or PECL compatible signals. The input signal of each
clock buffer is distributed to 10 identical, differential ECL/PECL outputs. If V
BB
is connected to the CLKA or CLKB input and
bypassed to GND by a 10 nF capacitor, the MC100ES6220 can be driven by single-ended ECL/PECL signals utilizing the V
BB
bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6220 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6220 supports positive (PECL) and negative (ECL) supplies. The MC100ES6220 is pin and function compatible to the
MC100EP220.
MC100ES6220
LOW VOLTAGE DUAL
1:10 DIFFERENTIAL ECL/PECL
CLOCK FANOUT BUFFER
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 1336A-01
TB SUFFIX
52-LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336A-01
Advanced Clock Drivers Devices
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Freescale Semiconductor
MC100ES6220
Figure 1. MC100ES6220 Logic Diagram
Figure 2. 52-Lead Package Pinout (Top View)
V
CC
QA0
V
BB
CLKB
V
CC
Fanout Buffer B
Fanout Buffer A
V
EE
V
EE
QA0
QA1
QA1
QA8
QA8
QA9
QA9
QB0
QB0
QB8
QB8
QB1
QB1
QB9
QB9
CLKB
CLKA
CLKA
V
CC
QA5
QA5
QA4
QA4
QA3
QA3
QA2
QA2
QA1
QA1
QA0
QA0
QB2
QB2
QB3
QB3
QB4
QB4
QB5
QB5
QB6
QB6
QB7
QB7
V
CC
QA
6
QA
7
QA
8
QA
9
V
CC
V
CC
V
EE
CL
KA
CL
KA
V
BB
CL
KB
CL
KB
V
EE
QB
9
QB
9
QB
8
QB
8
40
41
42
43
44
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
16
15
14
1 2 3 4 5 6 7 8 9 10 11 12 13
39 38 37 36 35 34 33 32 31 30 29 28 27
26
MC100ES6220
QA
6
QA
7
QA
8
QA
9
QB
0
QB
0
QB
1
QB
1
V
CC
QA4
Table 1. Pin Configuration
Pin
I/O
Type
Function
CLKA, CLKA
Input
ECL/PECL
Differential reference clock signal input for fanout buffer A
CLKB, CLKB
Input
ECL/PECL
Differential reference clock signal input for fanout buffer B
QA[0-9], QA[0-9]
Output
ECL/PECL
Differential clock outputs of fanout buffer A
QB[0-9], QB[0-9]
Output
ECL/PECL
Differential clock outputs of fanout buffer B
V
EE
(1)
1. In ECL mode (negative power supply mode), V
EE
is either 3.3 V or 2.5 V and V
CC
is connected to GND (0 V). In PECL mode (positive
power supply mode), V
EE
is connected to GND (0 V) and V
CC
is either
+3.3 V or +2.5 V. In both modes, the input and output levels are
referenced to the most positive supply (V
CC
).
Supply
Negative power supply
V
CC
Supply
Positive power supply. All V
CC
pins must be connected to the positive
power supply for correct DC and AC operation.
V
BB
Output
DC
Reference voltage output for single ended ECL and PECL operation
Advanced Clock Drivers Devices
Freescale Semiconductor
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MC100ES6220
Table 2. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol
Characteristics
Min
Max
Unit
Condition
V
CC
Supply Voltage
0.3
3.6
V
V
IN
DC Input Voltage
0.3
V
CC
+ 0.3
V
V
OUT
DC Output Voltage
0.3
V
CC
+ 0.3
V
I
IN
DC Input Current
20
mA
I
OUT
DC Output Current
50
mA
T
S
Storage Temperature
65
125
C
T
FUNC
Functional Temperature Range
T
A
= 40
T
J
= +110
C
Table 3. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
V
TT
Output Termination Voltage
V
CC
2
(1)
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase.
V
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
4000
V
CDM
ESD Protection (Charged Device Model)
2000
V
LU
Latch-Up Immunity
200
mA
C
IN
Input Capacitance
4.0
pF
Inputs
JA
,
JC
,
JB
Thermal Resistance (junction-to-ambient,
junction-to-board, junction-to-case)
See
Table 8. Thermal Resistance
C/W
T
J
Operating Junction Temperature
(2)
(continuous operation)
MTBF = 9.1 years
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are
specified up to 110
C junction temperature allowing the MC100ES6220 to be used in applications requiring industrial temperature range. It
is recommended that users of the MC100ES6220 employ thermal modeling analysis to assist in applying the junction temperature
specifications to their particular application.
0
110
C
Advanced Clock Drivers Devices
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Freescale Semiconductor
MC100ES6220
Table 4. PECL DC Characteristics (V
CC
= 2.5 V
5% or V
CC
= 3.3 V
5%, V
EE
= GND, T
J
= 0
C to +110C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL differential signals)
V
PP
Differential Input Voltage
(1)
1. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
0.1
1.3
V
Differential operation
V
CMR
Differential Cross Point Voltage
(2)
2. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
1.0
V
CC
0.3
V
Differential operation
I
IN
Input Current
(1)
150
A
V
IN
= V
IL
or V
IN
= V
IH
Clock Inputs (PECL single ended signals)
V
IH
Input Voltage High
V
CC
1.165
V
CC
0.880
V
V
IL
Input Voltage Low
V
CC
1.810
V
CC
1.475
V
I
IN
Input Current
(3)
3. Input have internal pullup/pulldown resistors which affect the input current.
150
A
V
IN
= V
IL
or V
IN
= V
IH
PECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9)
V
OH
Output High Voltage
V
CC
1.1
V
CC
1.005
V
CC
0.7
V
I
OH
= 30 mA
(4)
4. Termination 50
to V
TT
.
V
OL
Output Low Voltage
V
CC
1.9
V
CC
1.705
V
CC
1.4
V
I
OL
= 5 mA
(4)
Supply current and V
BB
I
EE
(5)
5. I
CC
calculation:
I
CC
= (number of differential output used) x (I
OH
+ I
OL
)
+ I
EE
I
CC
= (number of differential output used) x (V
OH
V
TT
)
R
load
+ (V
OL
V
TT
)
R
load
+ I
EE
.
Maximum Quiescent Supply Current without
Output Termination Current
80
130
mA
V
EE
pins
V
BB
Output Reference Voltage
V
CC
1.42
V
CC
1.20
V
I
BB
= 0.3 mA
Table 5. ECL DC Characteristics (V
EE
= 2.5 V
5% or V
EE
= 3.3 V
5%, V
CC
= GND, T
J
= 0
C to +110C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals)
V
PP
Differential Input Voltage
(1)
1. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
0.1
1.3
V
Differential operation
V
CMR
Differential Cross Point Voltage
(2)
2. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
V
EE
+ 1.0
0.3
V
Differential operation
I
IN
Input Current
(1)
150
A
V
IN
= V
IL
or V
IN
= V
IH
Clock Inputs (ECL single ended signals)
V
IH
Input Voltage High
1.165
0.880
V
V
IL
Input Voltage Low
1.810
1.475
V
I
IN
Input Current
(3)
3. Input have internal pullup/pulldown resistors which affect the input current.
150
A
V
IN
= V
IL
or V
IN
= V
IH
ECL Clock Outputs (QA0A9, QA0A9, QB0B9, QB0B9)
V
OH
Output High Voltage
1.1
1.005
0.7
V
I
OH
= 30 mA
(4)
4. Termination 50
to V
TT
.
V
OL
Output Low Voltage
1.9
1.705
1.4
V
I
OL
= 5 mA
(4)
Supply Current and V
BB
I
EE
(5)
5. I
CC
calculation: I
CC
= (number of differential output used) x (I
OH
+ I
OL
)
+ I
EE
I
CC
= (number of differential output used) x (V
OH
V
TT
)
R
load
+ (V
OL
V
TT
)
R
load
+ I
EE
.
Maximum Quiescent Supply Current without
Output Termination Current
80
130
mA
V
EE
pins
V
BB
Output Reference Voltage
1.42
1.20
V
I
BB
= 0.3 mA
Advanced Clock Drivers Devices
Freescale Semiconductor
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MC100ES6220
Figure 3. MC100ES6220 AC Test Reference
Figure 4. MC100ES6220 AC Reference Measurement Waveform
Table 6. AC Characteristics (ECL: V
EE
= 3.3 V
5% or V
EE
= 2.5 V
5%, V
CC
= GND) or
(PECL: V
CC
= 3.3 V
5% or V
CC
= 2.5 V
5%, V
EE
= GND, T
J
= 0
C to +110C)
(1)
1. AC characteristics apply for parallel output termination of 50
to V
TT
.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals)
V
PP
Differential Input Voltage
(2)
(peak-to-peak)
2. V
PP
(AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including t
PD
and
device-to-device skew.
0.3
1.3
V
V
CMR
Differential Input Crosspoint Voltage
(3)
PECL
ECL
3. V
CMR
(AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the
V
CMR
(AC) range and the input swing lies within the V
PP
(AC) specification. Violation of V
CMR
(AC) or V
PP
(AC) impacts the device
propagation delay, device and part-to-part skew.
1.1
V
EE
+ 1.1
V
CC
0.3
0.3
V
V
f
CLK
Input Frequency
0
1000
MHz
Differential
PECL/ECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9)
t
PD
Propagation Delay CLKx to Qx0-9
285
550
ps
Differential
V
O(P-P)
Differential Output Voltage (peak-to-peak)
400
600
mV
t
sk(O)
Output-to-Output Skew
60
130
ps
Differential
t
sk(PP)
Output-to-Output Skew (part-to-part)
200
ps
Differential
t
JIT(CC)
Output Cycle-to-Cycle Jitter
RMS (1
)
1
ps
t
SK(P)
DC
O
Output Pulse Skew
(4)
Output Duty Cycle
f
REF
< 0.1 GHz
f
REF
< 1.0 GHz
4. Output pulse skew is the absolute difference of the propagation delay times: | t
pLH
t
pHL
|.
49.65
46.5
50
50
35
50.35
53.5
ps
%
%
DC
REF
= 50%
DC
REF
= 50%
t
r
, t
f
Output Rise/Fall Time
50
350
ps
20% to 80%
Differential Pulse
Generator
Z = 50
R
T
= 50
Z = 50
DUT
MC100ES6220
V
TT
R
T
= 50
Z = 50
V
TT
t
PD
(CLK
N
to Q
X
)
V
CMR
= V
CC
1.3 V
V
PP
= 0.8 V
CLK
N
CLK
N
Q
X
Q
X
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