MC100ES6210
Rev 3, 02/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
Low Voltage 2.5/3.3 V Differential
ECL/PECL/HSTL Fanout Buffer
The MC100ES6210 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6210
supports various applications that require to distribute precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low clock skew outputs and superior digital
signal characteristics. Target applications for this clock driver is high performance
clock distribution in computing, networking and telecommunication systems.
Features
Dual 1:5 differential clock distribution
30 ps maximum device skew
Fully differential architecture from input to all outputs
SiGe technology supports near-zero output skew
Supports DC to 3 GHz operation of clock or data signals
ECL/PECL compatible differential clock outputs
ECL/PECL compatible differential clock inputs
Single 3.3 V,
3.3 V, 2.5 V or
2.5 V supply
Standard 32 lead LQFP package
Industrial temperature range
Pin and function compatible to the MC100EP210
32-lead Pb-free Package Available
Functional Description
The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The
device consists of two independent 1:5 clock fanout buffers. The input signal of each fanout buffer is distributed to five identical,
differential ECL/PECL outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL compatible signals.
If V
BB
is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6210 can be driven
by single-ended ECL/PECL signals utilizing the V
BB
bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6210 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6210 supports positive (PECL) and negative (ECL) supplies. The is function and pin compatible to the MC100EP210.
MC100ES6210
LOW VOLTAGE DUAL
1:5 DIFFERENTIAL PECL/ECL/HSTL
CLOCK FANOUT BUFFER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
Advanced Clock Drivers Devices
2
Freescale Semiconductor
MC100ES6210
Figure 1. MC100ES6210 Logic Diagram
Figure 2. 32-Lead Package Pinout (Top View)
CLKA
CLKA
CLKB
CLKB
QA0
QA0
QA1
QA1
QA2
QA2
QA3
QA3
QA4
QA4
QB0
QB0
QB1
QB1
QB2
QB2
QB3
QB3
QB4
QB4
V
BB
V
CC
V
CC
Q2
Q1
Q0
V
CC
QB2
QA
3
QA
3
AQ
4
QA
4
QB
0
QB
0
QB
1
QB
1
V
CC
N.
C
.
CL
KA
V
BB
CL
KA
CL
KB
CL
KB
V
EE
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
MC100ES6210
V
CC
V
CC
QB4
QB3
QB2
Q0
Q1
Q2
QB3
QB4
V
CC
Table 1. Pin Configuration
Pin
I/O
Type
Function
CLKA, CLKA
Input
ECL/PECL
Differential reference clock signal input (fanout buffer A)
CLKB, CLKB
Input
ECL/PECL
Differential reference clock signal input (fanout buffer B)
QA[0-4], QA[0-4]
Output
ECL/PECL
Differential clock outputs (fanout buffer A)
QB[0-4], QB[0-4]
Output
ECL/PECL
Differential clock outputs (fanout buffer B)
V
EE
(1)
1. In ECL mode (negative power supply mode), V
EE
is either 3.3 V or 2.5 V and V
CC
is connected to GND (0 V). In PECL mode (positive
power supply mode), V
EE
is connected to GND (0 V) and V
CC
is either +3.3 V or +2.5 V. In both modes, the input and output levels are
referenced to the most positive supply (V
CC
)
Supply
Negative power supply
V
CC
Supply
Positive power supply. All V
CC
pins must be connected to the positive
power supply for correct DC and AC operation.
V
BB
Output
DC
Reference voltage output for single ended ECL or PECL operation
Table 2. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol
Characteristics
Min
Max
Unit
Condition
V
CC
Supply Voltage
0.3
3.6
V
V
IN
DC Input Voltage
0.3
V
CC
+ 0.3
V
V
OUT
DC Output Voltage
0.3
V
CC
+ 0.3
V
I
IN
DC Input Current
20
mA
I
OUT
DC Output Current
50
mA
T
S
Storage temperature
65
125
C
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MC100ES6210
Table 3. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
V
TT
Output Termination Voltage
V
CC
2
(1)
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase.
V
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
CDM
ESD Protection (Charged Device Model)
V
LU
Latch-Up Immunity
200
mA
C
IN
Input Capacitance
4.0
pF
Inputs
JA
Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
JESD 51-6, 2S2P multilayer test board
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
JC
Thermal Resistance Junction to Case
23.0
26.3
C/W
MIL-SPEC 883E
Method 1012.1
T
J
Operating Junction Temperature
(2)
(continuous operation)
MTBF = 9.1 years
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are
specified up to 110
C junction temperature allowing the MC100ES6210 to be used in applications requiring industrial temperature range. It
is recommended that users of the MC100ES6210 employ thermal modeling analysis to assist in applying the junction temperature
specifications to their particular application.
110
C
Table 4. PECL DC Characteristics (V
CC
= 2.5 V
5% or V
CC
= 3.3 V
5%, V
EE
= GND, T
J
= 0
C to +110C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL differential signals)
V
PP
Differential Input Voltage
(1)
1. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
0.1
1.3
V
Differential operation
V
CMR
Differential Cross Point Voltage
(2)
2. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
1.0
V
CC
0.3
V
Differential operation
I
IN
Input Current
(1)
100
A
V
IN
= V
IL
or V
IN
= V
IH
PECL Clock Outputs (QA0-4, QA0-4, QB0-4, QB0-4)
V
OH
Output High Voltage
V
CC
1.2
V
CC
1.005
V
CC
0.7
V
I
OH
= 30 mA
(3)
3. Equivalent to a termination of 50
to V
TT
.
V
OL
Output Low Voltage
V
CC
= 3.3 V
5%
V
CC
= 2.5 V
5%
V
CC
1.9
V
CC
1.9
V
CC
1.705
V
CC
1.705
V
CC
1.5
V
CC
1.3
V
I
OL
= 5 mA
(3)
Supply Current and V
BB
I
EE
Maximum Quiescent Supply Current
without Output Termination Current
60
100
mA
V
EE
pin
V
BB
Output Reference Voltage
V
CC
1.38
V
CC
1.26
V
CC
1.14
V
I
BB
= 0.2 mA
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Freescale Semiconductor
MC100ES6210
Table 5. ECL DC Characteristics (V
EE
=
2.5 V
5% or V
EE
=
3.3 V
5%, V
CC
= GND, T
J
= 0
C to +110C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals)
V
PP
Differential Input Voltage
(1)
1. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
0.1
1.3
V
Differential operation
V
CMR
Differential Cross Point Voltage
(2)
2. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
V
EE
+ 1.0
0.3
V
Differential operation
I
IN
Input Current
(1)
100
A
V
IN
= V
IL
or V
IN
= V
IH
ECL Clock Outputs (QA04, QA04, QB04, QB04)
V
OH
Output High Voltage
1.2
1.005
0.7
V
I
OH
= 30 mA
(3)
3. Equivalent to a termination of 50
to V
TT
.
V
OL
Output Low Voltage
V
CC
= 3.3 V
5%
V
CC
= 2.5 V
5%
1.9
1.9
1.705
1.705
1.5
1.3
V
I
OL
= 5 mA
(3)
Supply Current and V
BB
I
EE
Maximum Quiescent Supply Current
without Output Termination Current
60
100
mA
V
EE
pin
V
BB
Output Reference Voltage
1.38
1.26
1.14
V
I
BB
= 0.2 mA
Advanced Clock Drivers Devices
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MC100ES6210
Figure 3. MC100ES6210 AC Test Reference
Table 6. AC Characteristics (ECL: V
EE
=
3.3 V
5% or V
EE
=
2.5 V
5%, V
CC
= GND) or
(PECL: V
CC
= 3.3 V
5% or V
CC
= 2.5 V
5%, V
EE
= GND, T
J
= 0
C to +110
C)
(1)
(2)
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50
to V
TT
.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals)
V
PP
Differential Input Voltage
(3)
(peak-to-peak)
3. V
PP
(AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including t
PD
and
device-to-device skew.
0.3
0.3
1.3
V
V
CMR
Differential Input Crosspoint Voltage
(4)
PECL
ECL
4. V
CMR
(AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the
V
CMR
(AC) range and the input swing lies within the V
PP
(AC) specification. Violation of V
CMR
(AC) or V
PP
(AC) impacts the device
propagation delay, device and part-to-part skew.
1.2
V
EE
+ 1.2
V
CC
0.3
0.3 V
V
V
ECL Clock Outputs (Q09, Q09)
f
CLK
Input Frequency
0
3000
MHz Differential
t
PD
Propagation Delay
CLKA to QAx or CLKB to QBx
175
260
350
ps
Differential
V
O(P-P)
Differential Output Voltage (peak-to-peak)
f
O
< 1.1 GHz
f
O
< 2.5 GHz
f
O
< 3.0 GHz
0.45
0.35
0.20
0.70
0.55
0.35
V
V
V
t
sk(O)
Output-to-Output Skew (per bank)
13
30
ps
Differential
t
sk(PP)
Output-to-Output Skew (part-to-part)
175
ps
Differential
t
JIT(CC)
Output Cycle-to-Cycle Jitter
1
ps
t
SK(P)
DC
Q
Output Pulse Skew
(5)
Output Duty Cycle
f
REF
< 0.1 GHz
f
REF
< 1.0 GHz
5. Output pulse skew is the absolute difference of the propagation delay times: | t
PLH
t
PHL
|.
49.5
45.0
50
50
50
50.5
55.0
ps
%
%
DC
REF
= 50%
DC
REF
= 50%
t
r
, t
f
Output Rise/Fall Time
30
250
ps
20% to 80%
Differential Pulse
Generator
Z = 50
R
T
= 50
Z
O
= 50
DUT
MC100ES6210
V
TT
R
T
= 50
Z
O
= 50
V
TT
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Freescale Semiconductor
MC100ES6210
PACKAGE DIMENSIONS
12 REF
DIM
MIN
MAX
MILLIMETERS
A
A1
7.00 BSC
A2
0.80 BSC
b
9.00 BSC
b1
0.30
0.40
c
0.09
0.20
c1
0.09
0.16
D
D1
e
E
E1
L
L1
1.00 REF
R1
0.08
0.20
R2
S
1
1.40
1.60
0.05
0.15
1.35
1.45
0.30
0.45
0.08
---
0
7
9.00 BSC
7.00 BSC
0.50
0.70
q
q
0.20 REF
D1
D/2
E
E1
1
8
9
17
25
32
D1/2
E1/2
E/2
4X
D
7
A
D
B
A-B
0.20 H
D
4X
A-B
0.20 C
D
6
6
4
4
DETAIL G
PIN 1 INDEX
DETAIL AD
R R2
(S)
L
(L1)
0.25
GAUGE PLANE
A2
A
A1
(
1)
8X
R R1
e
SEATING
PLANE
DETAIL AD
0.1 C
C
32X
28X
H
DETAIL G
F
F
e/2
A, B, D
3
SECTION F-F
BASE
c1
c
b
b1
METAL
A-B
M
0.20
D
C
5
8
PLATING
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
Advanced Clock Drivers Devices
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MC100ES6210
NOTES
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MC100ES6210
Rev. 3
02/2005
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