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Электронный компонент: TMB22153AMS100

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TMB22153AMS100
Demonstration Board for the TMC22x5yA
Multistandard Digital Video Decoder
Pr
eliminar
y Infor
mation
www.fairchildsemi.com
Features
Accepts analog composite or YC
Outputs 10-bit digital RGB, D1, or YC
B
C
R
Locks to studio reference
R-bus serial interface compatibility
Raytheon demo board compatibility
Applications
Evaluation of TMC22x5yA Digital Video Decoder
Input for Genesis 10-bit Line Doubler board
Input for DAC and encoder demo boards
System Breadboarding
Related Products
TMC2069P7C DAC demonstration board
TMC2074P7C Encoder demonstration board
TMB2193MS100 Encoder demonstration board
TMC2070P7C R-bus interface board
Raydemo software
Description
The TMB22153AMS100 Demonstration Board showcases
the TMC22x5yA Digital Video Decoder. The onboard MMC
FE-100 dual 10-bit A/D modules generate digitized compos-
ite or YC for the decoder. The decoder outputs D1, digital
RGB, or YC
B
C
R
. Clocks and synchronization pulses are gen-
erated by Fairchild's TMC2072 Genlocking Video Digitizer.
Block Diagram
FE-100x-1
FE-100x-2
Framestore
Connector
RBUS
TMC22153A
TMC2072
SW1
D.C. supply
Analog signals
Composite/Luma
video input
Y/C video input
Chroma
video input
Digital signals
TMB22153AMS100
96 way Edge
Connector (male)
10 bit G/Y
10 bit B/U
10 bit R/V or D1
PXCK clock
HSYNC
VSYNC
SYNC\ (D/A signals)
BLANK\ (D/A signals)
Micro (top)
FPGA (bottom)
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals
and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
Rev. 001
TMB22153AMS100
PRELIMINARY INFORMATION
2
Pr
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y Infor
mation
Functional Description
The TMB22153AMS100 is designed to demonstrate the
performance of the TMC22x5yA Digital Video Decoder. For
complete descriptions of the TMC22x5yA, TMC2072,
TMC1185, and TMC2242 please refer to part datasheets.
The TMB22153AMS100 is designed to be used in
conjunction with other Fairchild demo boards, namely the
TMC2069P7C DAC, and TMB2193MS100 encoder boards.
The 96 pin edge connectors plug easily into each other.
When used together, the boards demonstrate a high
performance 10-bit digital video decoding system.
TMC22x5yA Digital Video Decoder
The TMC22x5yA accepts digitized video input on two
10-bit buses, "YOVER[9:0]" and "COVER[9:0]". Based on
the status of its control registers, it then outputs the data to
the output edge connector of the board in a variety of
formats. Please see Table 1 for a listing of board default
video standards and output formats that are loadable to the
control registers.
After the TMC22x5yA control registers have been initially
loaded by the microcontroller, subsequent changes to the
control registers may be made through the R-bus interface
and Raydemo software.
It is important that the control registers be loaded correctly in
order to obtain the desired output. Once the control registers
have been set to output the correct data from the
TMC22x5yA, then several board switches must also be
correctly configured in order to obtain the desired output.
TMC2072 Genlocking Video Digitizer
The TMC2072 Genlocking Video Digitizer accepts analog
composite data through the composite input BNC on the left
side of the board. A 20MHz clock crystal provides the Gen-
lock with an input clock. The TMC2072 outputs horizontal
and vertical syncs, and a 27MHz clock. The clock is used to
drive the Decoder and EPLD. Like the TMC22x5yA, the
Genlock part must be programmed at startup. Instructions on
how to do this are in the "Microcontroller" section of this
documentation.
EPLD
An Altera EPF10K10TC144-4 EPLD executes several
essential board functions. The EPLD serves as a buffer and
multiplexer for data buses and a register for several impor-
tant control signals. These signals may be cross-referenced
to the included schematics. The EPLD control registers may
be modified using the Raydemo software. The Raydemo
EPLD R-bus address is 0000001. For a more complete
description or specification of signals going to or coming
from the TMC22x5yA and TMC2072, please refer to the
Fairchild Semiconductor Data Book (also available on CD-
ROM) or the website at www.fairchildsemi.com.
Microcontroller
An Atmel 89C55 microcontroller is used to program the
TMC22x5yA and TMC2072 registers. The microcontroller
programs the parts through the R-bus at power up and repro-
grams them each time the "Reset" button is pushed. Please
see Table 1 on the next page for a description of available
microcontroller-programmed board configurations.
Table 1. TMB22153AMS100 Demonstration Board Video Standard Selection
P
3-0
Input Format
Video Standard
Output Format
0000
composite
NTSC
YUV
0001
Y/C
NTSC
YUV
0010
composite
NTSC
D1
0011
Y/C
NTSC
D1
0100
composite
NTSC
RGB
0101
composite, field-based
NTSC
YUV
0110
composite, field-based
NTSC
D1
0111
composite, frame-based
NTSC
YUV
1000
composite
PAL
YUV
1001
Y/C
PAL
YUV
1010
composite
PAL
D1
1011
Y/C
PAL
D1
1100
composite
PAL
RGB
1101
composite, field-based
PAL
YUV
1110
composite, field-based
PAL
D1
1111
reserved
PRELIMINARY INFORMATION
TMB22153AMS100
3
Pr
eliminar
y Infor
mation
Quick Setup/Verification for Composite NTSC
Input, YUV Output
1.
Configure jumpers:
If using R-Bus interface, JP2 must be closed
(connected)
Leave JP1 open (unconnected)
Verify that JP4 is linked to the odd-numbered pins of
JP6
2.
Configure slider-switches (push red slider TOWARD
specified marking on board) :
E1
"FPGA"
E2
"FPGA"
E3
"VS"
E4
"PXCK4\"
E5
"GP"
E6
"GH"
E7
"GV"
E8
"XP"
3.
If you have reason to believe the bottom cover has been
removed, remove it and configure S4 as follows:
1-7
ON (low)
8
OFF (high)
4.
Ensure BNC J1 (VIN1) is connected to composite
NTSC signal.
5.
Ensure piano-key switches P
3-0
, Y are in the "LOW"
(down) position.
6.
Plug in power-supply connector and apply power.
LED's corresponding to applied voltages should light-
up.
7.
Press and release the MRST button (S2). The TMC2072
and TMC22x5yA should both be programmed. To
verify the TMC2072 is functioning correctly, check for
presence of a clock (TP sync pulses, VS (TP18) and
HS (TP17). Likewise, to verify the TMC22x5yA is
functioning, check for presence of DHSYNC (TP5) and
DVSYNC (TP6).
Power Supply Requirements
The TMB22153AMS100 power supply connector is on
the top edge of the board toward the left side. The
TMB22153AMS100 board requires DC power supply
voltages of +5V and -5V.
The +5V supply provides power and voltage references to
the TMC22x5yA and /TMC2072, as well as driving TTL
logic devices. It is for this reason that a bench power supply
with short cable lengths is recommended.
TMB22153AMS100
PRELIMINARY INFORMATION
4
Pr
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PRELIMINARY INFORMATION
TMB22153AMS100
5
Pr
eliminar
y Infor
mation
C
8

N
O
T

I
N
S
T
A
L
L
E
D
I
F

C
R
1
0

I
S

I
N
S
T
A
L
L
E
D
V
C
C
V
C
C
V
C
C
V
C
C
V
C
C
G
V
S
Y
N
C
A
G
N
D
C
V
B
S
7
G
P
X
C
K
C
V
B
S
5
C
V
B
S
1
C
V
B
S
6
S
A
2
C
V
B
S
0
2
0
M
C
L
K
S
D
A
G
V
S
Y
N
C
C
V
B
S
3
G
H
S
Y
N
C
G
N
D
G
H
S
Y
N
C
S
C
L
G
P
X
C
K
C
V
B
S
[
0
.
.
7
]
D
G
N
D
G
R
S
T
\
C
V
B
S
2
C
V
B
S
4
S
A
0
S
A
1
V
A
L
I
D
S
A
1
S
D
A
G
R
S
T
\
G
P
X
C
K
G
H
S
Y
N
C
S
A
0
A
N

C
O
M
P
/
L
U
M
A
C
V
B
S
[
0
.
.
7
]
S
A
2
S
C
L
G
V
S
Y
N
C
T
P
5
T
P
C
1
3
6
.
8
p
F
C
8
0
.
1
u
F
C
4
0
.
1
u
F
R
5
4
.
7
5
K
R
3
7
5
T
P
4
T
P
+C
1
1
2
2
u
F
/
6
.
3
v
C
1
4
0
.
1
u
F
C
1
9
1
5
0
p
F
C
1
8
0
.
1
u
F
C
2
0
3
9
0
p
F
U
1
T
M
C
2
0
7
2
K
H
C
V
I
N
1
6
5
V
I
N
2
6
1
V
I
N
3
5
8
N
C
9
N
C
1
2
S
A
2
3
S
C
L
5
E
X
T

P
X
C
K
9
4
L
D
V
4
0
N
C
8
5
N
C
1
9
N
C
2
0
C
V
B
S
0
2
1
C
V
B
S
1
2
2
C
V
B
S
5
2
8
C
V
B
S
7
3
0
G
H
S
Y
N
C
3
2
G
V
S
Y
N
C
3
3
V
A
L
I
D
3
4
N
C
1
3
F
I
D
0
3
5
V
R
E
F
7
0
C
O
M
P
8
8
R
T
6
8
R
B
5
7
N
C
8
3
C
B
Y
P
7
5
P
F
D

I
N
7
7
N
C
1
0
N
C
1
4
C
V
B
S
4
2
5
F
I
D
2
3
7
N
C
4
3
C
L
K

I
N
9
1
C
V
B
S
2
2
3
P
X
C
K
4
5
C
L
K

O
U
T
9
3
N
C
9
9
S
A
0
1
S
A
1
2
R
E
S
E
T
7
N
C
1
1
N
C
1
5
I
N
T
1
7
C
V
B
S
3
2
4
C
V
B
S
6
2
9
B
U
R
L
3
1
F
I
D
1
3
6
N
C
4
7
N
C
5
3
N
C
5
4
N
C
5
6
N
C
5
9
N
C
6
2
N
C
6
6
N
C
7
1
N
C
7
6
N
C
7
8
N
C
7
9
N
C
8
0
D
D
S

O
U
T
8
2
N
C
8
4
P
X
C
K

S
E
L
8
6
S
D
A
4
C
7
0
.
1
u
F
T
P
2
T
P
R
6
4
.
7
5
K
+
C
1
0
2
2
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F
/
6
.
3
v
C
9
0
.
1
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F
R
2
7
5
H
3
1
T
P
3
T
P
H
1
1
C
6
0
.
1
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F
T
P
1
T
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1
7
5
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4
3
.
3
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C
2
1
0
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1
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F
C
3
0
.
1
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F
C
1
6
0
.
1
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F
Y
1
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0
M
H
z
O
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T
5
H
2
1
C
1
2
0
.
1
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F
C
R
1
1
.
2
3
5
V
2
1
L
1
I
N
D
U
C
T
O
R
C
1
0
.
1
u
F
C
2
0
.
1
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F
C
1
5
0
.
1
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F
C
1
7
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1
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F
C
5
0
.
1
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F