TL D 8827
NMC27C32B
32768-Bit
(4096
x
8
)
CMOS
EPROM
December 1996
NMC27C32B
32 768-Bit (4096 x 8) CMOS EPROM
General Description
The NMC27C32B is a 32k UV erasable and electrically re-
programmable CMOS EPROM ideally suited for applica-
tions where fast turnaround pattern experimentation and
low power consumption are important requirements
The NMC27C32B is designed to operate with a single
a
5V
power supply with
g
10% tolerance
The NMC27C32B is packaged in a 24-pin dual-in-line pack-
age with a quartz window The quartz window allows the
user to expose the chip to ultraviolet light to erase the bit
pattern A new pattern can then be written electrically into
the device by following the programming procedure
This EPROM is fabricated with National's proprietary time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low pow-
er consumption and excellent reliability
Features
Y
Low CMOS power consumption
Active Power 55 mW Max
Standby Power 0 55 mW Max
Y
Extended temperature range
b
40 C to
a
85 C
Y
Fast and reliable programming
Y
TTL CMOS compatible inputs outputs
Y
TRI-STATE
output
Y
Manufacturer's identification code for automatic
programming
Y
High current CMOS level output drivers
Y
Compatible with NMOS 2732
Block Diagram
TL D 8827 1
Pin Names
A0 A11
Addresses
CE
Chip Enable
OE
Output Enable
V
PP
Programming Voltage
O
0
O
7
Outputs
V
CC
Power Supply
GND
Ground
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation
RRD-B30M17 Printed in U S A
http
www national com
Connection Diagram
27C256
27C128
27C64
27C16
27256
27128
2764
2716
V
PP
V
PP
V
PP
A12
A12
A12
A7
A7
A7
A7
A6
A6
A6
A6
A5
A5
A5
A5
A4
A4
A4
A4
A3
A3
A3
A3
A2
A2
A2
A2
A1
A1
A1
A1
A0
A0
A0
A0
O
0
O
0
O
0
O
0
O
1
O
1
O
1
O
1
O
2
O
2
O
2
O
2
GND
GND
GND
GND
NMC27C32B
Dual-In-Line Package
TL D 8827 2
27C16
27C64
27C128
27C256
2716
2764
27128
27256
V
CC
V
CC
V
CC
PGM
PGM
A14
V
CC
NC
A13
A13
A8
A8
A8
A8
A9
A9
A9
A9
V
PP
A11
A11
A11
OE
OE
OE
OE
A10
A10
A10
A10
CE
CE
CE
CE
O
7
O
7
O
7
O
7
O
6
O
6
O
6
O
6
O
5
O
5
O
5
O
5
O
4
O
4
O
4
O
4
O
3
O
3
O
3
O
3
Note
Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C32B pins
Order Number NMC27C32BQ
See NS Package Number J24AQ
Commercial Temp Range (0 C to
a
70 C) V
CC
e
5V
g
10%
Parameter Order Number
Access Time (ns)
NMC27C32BQ150
150
NMC27C32BQ200
200
NMC27C32BQ250
250
Extended Temp Range (
b
40 C to
a
85 C) V
CC
e
5V
g
10%
Parameter Order Number
Access Time (ns)
NMC27C32BQE200
200
http
www national com
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Temperature Under Bias
b
40 C to
a
85 C
Storage Temperature
b
65 C to
a
150 C
V
CC
Supply Voltage with
Respect to Ground
a
7 0V to
b
0 6V
All Input Voltages except A9
and OE V
PP
with
Respect to Ground (Note 9)
a
6 5V to
b
0 6V
All Output Voltages with
Respect to Ground (Note 9)
V
CC
a
1 0V to GND
b
0 6V
OE V
PP
Supply and A9 Voltage with
Respect to Ground
a
14 0V to
b
0 6V
Power Dissipation
1 0W
Lead Temperature (Soldering 10 sec )
300 C
Operating Conditions
(Note 6)
Temperature Range
NMC27C32BQ150 200 250
0 C to
a
70 C
NMC27C32BQE200
b
40 C to
a
85 C
V
CC
Power Supply
a
5V
g
10%
READ OPERATION
DC Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
LI
Input Load Current
V
IN
e
V
CC
or GND
0 01
1
m
A
I
PP
OE V
PP
Load Current
OE V
PP
e
V
CC
or GND
10
m
A
I
LO
Output Leakage Current
V
OUT
e
V
CC
or GND CE
e
V
IH
0 01
1
m
A
I
CC1
V
CC
Current (Active)
CE
e
V
IL
f
e
5 MHz
5
20
mA
TTL Inputs
Inputs
e
V
IH
or V
IL
I O
e
0 mA
I
CC2
V
CC
Current (Active)
CE
e
GND f
e
5 MHz
3
10
mA
CMOS Inputs
Inputs
e
V
CC
or GND I O
e
0 mA
I
CCSB1
V
CC
Current (Standby)
CE
e
V
IH
0 1
1
mA
TTL Inputs
I
CCSB2
V
CC
Current (Standby)
CE
e
V
CC
0 5
100
m
A
CMOS Inputs
V
IL
Input Low Voltage
b
0 2
0 8
V
V
IH
Input High Voltage
2 0
V
CC
a
1
V
V
OL1
Output Low Voltage
I
OL
e
2 1 mA
0 45
V
V
OH1
Output High Voltage
I
OH
e b
400 mA
2 4
V
V
OL2
Output Low Voltage
I
OL
e
10 mA
0 1
V
V
OH2
Output High Voltage
I
OH
e b
10 mA
V
CC
b
0 1
V
AC Electrical Characteristics
NMC27C32B
Symbol
Parameter
Conditions
Q150
Q200 QE200
Q250
Units
Min
Max
Min
Max
Min
Max
t
ACC
Address to Output Delay
CE
e
OE
e
V
IL
150
200
250
ns
t
CE
CE to Output Delay
OE
e
V
IL
150
200
250
ns
t
OE
OE to Output Delay
CE
e
V
IL
60
60
70
ns
t
DF
OE High to Output Float
CE
e
V
IL
0
50
0
60
0
70
ns
t
CF
CE High to Output Float
OE
e
V
IL
0
50
0
60
0
60
ns
t
OH
Output Hold from Addresses
CE
e
OE
e
V
IL
CE or OE Whichever
0
0
0
ns
Occurred First
http
www national com
3
Capacitance
T
A
e a
25 C f
e
1 MHz (Note 2)
Symbol
Parameter
Conditions
Typ
Max
Units
C
IN1
Input Capacitance except OE V
PP
V
IN
e
0V
6
12
pF
C
IN2
OE V
PP
Input Capacitance
V
IN
e
0V
16
20
pF
C
OUT
Output Capacitance
V
OUT
e
0V
9
12
pF
AC Test Conditions
Output Load
1 TTL Gate and
C
L
e
100 pF (Note 8)
Input Rise and Fall Times
s
5 ns
Input Pulse Levels
0 45V to 2 4V
Timing Measurement Reference Level
Inputs
0 8V and 2V
Outputs
0 8V and 2V
AC Waveforms
(Note 7)
TL D 8827 3
Note 1
Stresses above those listed under ``Absolute Maximum Ratings'' may cause permanent damage to the device This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability
Note 2
This parameter is only sampled and is not 100% tested
Note 3
OE may be delayed up to t
ACC
b
t
OE
after the falling edge of CE without impacting t
ACC
Note 4
The t
DF
and t
CF
compare level is determined as follows
High to TRI-STATE the measured V
OH1
(DC)
b
0 10V
Low to TRI-STATE the measured V
OL1
(DC)
a
0 10V
Note 5
TRI-STATE may be attained using OE or CE
Note 6
The power switching characteristics of EPROMs require careful device decoupling It is recommended that at least a 0 1 mF ceramic capacitor be used on
every device between V
CC
and GND
Note 7
The outputs must be restricted to V
CC
a
1 0V to avoid latch-up and device damage
Note 8
1 TTL Gate I
OL
e
1 6 mA I
OH
e b
400 mA
C
L
100 pF includes fixture capacitance
Note 9
Inputs and outputs can undershoot to
b
2 0V for 20 ns Max except for OE V
PP
which cannot exceed
b
0 2V
Note 10
Typical values are for T
A
e
25 C and nominal supply voltages
http
www national com
4
Programming Characteristics
(Notes 1 2 3
4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
AS
Address Setup Time
1
m
s
t
OES
OE Setup Time
1
m
s
t
DS
Data Setup Time
1
m
s
t
VCS
V
CC
Setup Time
1
m
s
t
AH
Address Hold Time
0
m
s
t
DH
Data Hold Time
1
m
s
t
CF
Chip Enable to Output Float Delay
OE
e
V
IL
0
60
ns
t
PW
Program Pulse Width
95
100
105
m
s
t
OEH
OE Hold Time
1
m
s
t
DV
Data Valid from CE
OE
e
V
IL
250
ns
t
PRT
OE Pulse Rise Time
50
ns
During Programming
t
VR
V
PP
Recovery Time
1
m
s
I
PP
V
PP
Supply Current During
CE
e
V
IL
30
mA
Programming Pulse
OE
e
V
PP
I
CC
V
CC
Supply Current
10
mA
T
A
Temperature Ambient
20
25
30
C
V
CC
Power Supply Voltage
6 0
6 25
6 5
V
V
PP
Programming Supply Voltage
12 5
12 75
13 0
V
t
FR
Input Rise Fall Time
5
ns
V
IL
Input Low Voltage
0 0
0 45
V
V
IH
Input High Voltage
2 4
4 0
V
t
IN
Input Timing Reference Voltage
0 8
2 0
V
t
OUT
Output Timing Reference Voltage
0 8
2 0
V
Programming Waveforms
TL D 8827 4
Note 1
National's standard product warranty applies only to devices programmed to specifications described herein
Note 2
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
The EPROM must not be inserted into or removed from a
board with voltage applied to V
PP
or V
CC
Note 3
The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V Care must be taken when switching the V
PP
supply to prevent any overshoot from exceeding this 14V maximum specification At least a 0 1 mF capacitor is required across V
CC
to GND to suppress spurious
voltage transients which may damage the device
Note 4
Programming and program verify are tested with the fast Program Algorithm at typical power supply voltages and timings
http
www national com
5
PDF 
ZIP