2005 Fairchild Semiconductor Corporation
DS005315
www.fairchildsemi.com
September 1983
Revised January 2005
MM74HC164 8-Bi
t Seri
al-
i
n
/
Para
ll
el-
out Shi
f
t
Regi
ster
MM74HC164
8-Bit Serial-in/Parallel-out Shift Register
General Description
The MM74HC164 utilizes advanced silicon-gate CMOS
technology. It has the high noise immunity and low con-
sumption of standard CMOS integrated circuits. It also
offers speeds comparable to low power Schottky devices.
This 8-bit shift register has gated serial inputs and CLEAR.
Each register bit is a D-type master/slave flip-flop. Inputs A
& B permit complete control over the incoming data. A
LOW at either or both inputs inhibits entry of new data and
resets the first flip-flop to the low level at the next clock
pulse. A high level on one input enables the other input
which will then determine the state of the first flip-flop. Data
at the serial inputs may be changed while the clock is HIGH
or LOW, but only information meeting the setup and hold
time requirements will be entered. Data is serially shifted in
and out of the 8-bit register during the positive going transi-
tion of the clock pulse. Clear is independent of the clock
and accomplished by a low level at the CLEAR input.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
CC
and ground.
Features
s
Typical operating frequency: 50 MHz
s
Typical propagation delay: 19 ns (clock to Q)
s
Wide operating supply voltage range: 2V to 6V
s
Low input current: 1
A maximum
s
Low quiescent supply current: 80
A maximum
(74HC Series)
s
Fanout of 10 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Order Number
Package
Package Description
Number
MM74HC164M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC164MX_NL
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC164MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC164MTCX_NL
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HC164N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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2
MM
74HC164
Connection Diagram
Top View
Truth Table
H
=
HIGH Level (steady state), L
=
LOW Level (steady state)
X
=
Irrelevant (any input, including transitions)
=
Transition from LOW-to-HIGH level.
Q
AO
, Q
BO
, Q
HO
=
the level of Q
A
, Q
B
, or Q
H
, respectively, before the indi-
cated steady state input conditions were established.
Q
An
, Q
Gn
=
The level of Q
A
or Q
G
before the most recent
transition of the
clock; indicated a one-bit shift.
Logic Diagram
Inputs
Outputs
Clear
Clock
A
B
Q
A
Q
B
...
Q
H
L
X
X
X
L
L
L
H
L
X
X
Q
AO
Q
BO
Q
HO
H
H
H
H
Q
An
Q
Gn
H
L
X
L
Q
An
Q
Gn
H
X
L
L
Q
An
Q
Gn
3
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MM74HC164
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating -- plastic "N" package:
-
12 mW/
C from 65
C to 85
C.
DC Electrical Characteristics
(Note 4)
Note 4: For a power supply of 5V
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Supply Voltage (V
CC
)
-
0.5 to
+
7.0V
DC Input Voltage (V
IN
)
-
1.5 to V
CC
+
1.5V
DC Output Voltage (V
OUT
)
-
0.5 to V
CC
+
0.5V
Clamp Diode Current (I
IK
, I
OK
)
20 mA
DC Output Current, per pin (I
OUT
)
25 mA
DC V
CC
or GND Current, per pin (I
CC
)
50 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Dissipation (P
D
)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
C
Min
Max
Units
Supply Voltage (V
CC
)
2
6
V
DC Input or Output Voltage
(V
IN
, V
OUT
)
0
V
CC
V
Operating Temperature Range (T
A
)
-
40
+
85
C
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
1000
ns
V
CC
=
4.5V
500
ns
V
CC
=
6.0V
400
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
2.0V
1.5
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
3.15
6.0V
4.2
4.2
4.2
V
IL
Maximum LOW Level
2.0V
0.5
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
1.35
6.0V
1.8
1.8
1.8
V
OH
Minimum HIGH Level
V
IN
=
V
IH
or V
IL
V
Output Voltage
|I
OUT
|
20
A
2.0V
2.0
1.9
1.9
1.9
4.5V
4.5
4.4
4.4
4.4
6.0V
6.0
5.9
5.9
5.9
V
IN
=
V
IH
or V
IL
|I
OUT
|
4.0 mA
4.5V
4.2
3.98
3.84
3.7
|I
OUT
|
5.2 mA
6.0V
5.7
5.48
5.34
5.2
V
OL
Maximum LOW Level
V
IN
=
V
IH
or V
IL
V
Output Voltage
|I
OUT
|
20
A
2.0V
0
0.1
0.1
0.1
4.5V
0
0.1
0.1
0.1
6.0V
0
0.1
0.1
0.1
V
IN
=
V
IH
or V
IL
|I
OUT
|
4.0 mA
4.5V
0.2
0.26
0.33
0.4
|I
OUT
|
5.2 mA
6.0V
0.2
0.26
0.33
0.4
I
IN
Maximum Input
V
IN
=
V
CC
or GND
6.0V
0.1
1.0
1.0
A
Current
I
CC
Maximum Quiescent
V
IN
=
V
CC
or GND
6.0V
8.0
80
160
A
Supply Current
I
OUT
=
0
A
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4
MM
74HC164
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
AC Electrical Characteristics
C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Note 5: C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
f
MAX
Maximum Operating Frequency
30
MHz
t
PHL
, t
PLH
Maximum Propagation Delay
19
30
ns
Clock to Output
t
PHL
Maximum Propagation Delay
23
35
ns
Clear to Output
t
REM
Minimum Removal Time,
-
2
0
ns
Clear to Clock
t
S
Minimum Setup Time
12
20
ns
Data to Clock
t
H
Minimum Hold Time
1
5
ns
Clock to Data
t
W
Minimum Pulse Width
10
16
ns
Clear or Clock
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
f
MAX
Maximum Operating Frequency
2.0V
5
4
3
MHz
4.5V
27
21
18
6.0V
31
24
20
t
PHL
, t
PLH
Maximum Propagation Delay
2.0V
115
175
218
254
ns
Clock to Output
4.5V
13
35
44
51
6.0V
20
30
38
44
t
PHL
Maximum Propagation Delay
2.0V
140
205
256
297
ns
Clear to Output
4.5V
28
41
51
59
6.0V
24
35
44
51
t
REM
Minimum Removal Time
2.0V
-
7
0
0
0
ns
Clear to Clock
4.5V
-
3
0
0
0
6.0V
-
2
0
0
0
t
S
Minimum Setup Time
2.0V
25
100
125
150
ns
Data to Clock
4.5V
14
20
25
30
6.0V
12
17
21
25
t
H
Minimum Hold Time
2.0V
-
2
5
5
5
ns
Clock to Data
4.5V
0
5
5
5
6.0V
1
5
5
5
t
W
Minimum Pulse Width
2.0V
22
80
100
120
ns
Clear or Clock
4.5V
11
16
20
24
6.0V
10
14
18
20
t
THL
, t
TLH
Maximum Output
2.0V
75
95
110
ns
Rise and Fall Time
4.5V
15
19
22
6.0V
13
16
19
t
r
, t
f
Maximum Input
2.0V
1000
1000
1000
ns
Rise and Fall Time
4.5V
500
500
500
6.0V
400
400
400
C
PD
Power Dissipation Capacitance
(Note 5)
(per package)
5.0V
150
pF
C
IN
Maximum Input Capacitance
5
10
10
10
pF
5
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MM74HC164
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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6
MM
74HC164
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
7
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MM74HC164 8-Bi
t Seri
al-
i
n
/
Para
ll
el-
out Shi
f
t
Regi
ster
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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