2000 Fairchild Semiconductor Corporation
DS009809
www.fairchildsemi.com
October 1988
Revised May 2000
DM93S62
9-
Input
Par
i
t
y
Chec
ker/
G
e
n
erat
or
DM93S62
9-Input Parity Checker/Generator
General Description
The DM93S62 is a very high speed 9-input parity checker/
generator for use in error detection and error correction
applications. The DM93S62 provides odd and even parity
for up to nine data bits. The even parity output (PE) is
HIGH if an even number of inputs are HIGH and E is LOW.
The odd parity output (PO) will be HIGH if an odd number
of inputs are HIGH and E is LOW. A HIGH level on the
Enable (E) input forces both outputs LOW.
Ordering Code:
Logic Symbol
V
CC
=
Pin 14
GND
=
Pin 7
Connection Diagram
Pin Descriptions
Truth Table
(E
=
LOW)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Order Number
Package Number
Package Description
DM93S62N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Name
Description
I0I8
Data Inputs
E
Output Enable (Active LOW)
PO
Odd Parity Output
PE
Even Parity Output
Number of Inputs
Outputs
I0I8 that are HIGH
PO
PE
1, 3, 5, 7, 9
H
L
0, 2, 4, 6, 8
L
H
www.fairchildsemi.com
2
DM
93S62
Functional Description
The DM93S62 is a very high speed 9-input parity checker
or generator. It is intended primarily for error detection in
systems which transmit data in 8-bit bytes, but it can be
expanded to any number of data inputs. Both even and odd
parity outputs are available to allow maximum flexibility for
both parity generation and parity checking. When the
device is enabled (E
=
LOW), the Even Parity output (PE)
is HIGH when an even number of inputs is HIGH, and the
Odd Parity output (PO) is HIGH when an odd number of
inputs is HIGH. The active LOW Enable (E) controls the
state of both outputs; when the Enable (E) is HIGH, both
outputs will be LOW. The Enable may be used to strobe the
outputs at very high speeds to synchronize or inhibit the
parity data.
The DM93S62 has been designed with two sections using
Exclusive-NOR comparison techniques. Eight data inputs
I0I7 represent one section which will generate a parity bit
in 16 ns to 20 ns. The ninth input (I8) bypasses three levels
of logic and switches the outputs in 6.0 ns to 9.0 ns. This
feature may be used to compensate for delayed arrival of
the parity bit, allowing faster system cycle times (Figure 1).
The fast I8 input is also useful when more than nine bits
are to be checked. The output of one DM93S62 drives the
I8 input of a second DM93S62, providing a 17-bit parity
check in 29 ns (typ).
When some inputs of the DM93S62 are not used, such as
for words of less than nine bits or when using parallel
expansion techniques, there is an optimum delay scheme
for termination of the unused inputs (see Table 1). In
essence, if one of the inputs of any Exclusive-NOR stays
HIGH, the delay from the other input to the output is mini-
mized.
TABLE 1. Termination Recommendations for Less than Nine Bits
FIGURE 1. Fast Input I8 allows Higher System Speed
Number of
I0
I1
I2
I3
I4
I5
I6
I7
I8
Data Inputs
3
D0
L
D1
L
D2
L
L
L
L
4
D0
L
D1
L
D2
L
D3
L
L
5
D0
L
D1
L
D2
L
D3
L
D4
6
D0
D1
D2
D3
D4
L
D5
L
L
7
D0
D1
D2
D3
D4
L
D5
L
D6
8
D0
D1
D2
D3
D4
D5
D6
D7
L
3
www.fairchildsemi.com
DM93S62
Logic Diagram
www.fairchildsemi.com
4
DM
93S62
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Note 2: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
V
CC
=
+
5.0V, T
A
=
+
25
C
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
1
mA
I
OL
LOW Level Output Current
20
mA
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 2)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.7
3.4
V
Output Voltage
V
IL
=
Max
V
OL
LOW Level Output
V
CC
=
Min, I
OL
=
Max
0.35
0.5
V
Voltage
V
IH
=
Min
I
I
Input Current @ Max Input Voltage
V
CC
=
Max, V
I
=
5.5V
1
mA
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V
50
A
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.5V, I0I8
-
1.6
mA
V
CC
=
Max, V
I
=
0.5V, E Only
-
3.2
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 3)
-
40
-
100
mA
I
CC
Supply Current
V
CC
=
Max
65
mA
Symbol
Parameter
C
L
=
15 pF
Units
Min
Max
t
PLH
Propagation Delay
26
ns
t
PHL
I0I7 to PE
22
t
PLH
Propagation Delay
12
ns
t
PHL
I8 to PE
9.0
t
PLH
Propagation Delay
26
ns
t
PHL
I0I7 to PO
26
t
PLH
Propagation Delay
13
ns
t
PHL
I8 to PO
13
t
PLH
Propagation Delay
7.0
ns
t
PHL
E to PE
7.0
t
PLH
Propagation Delay
7.0
ns
t
PHL
E to PO
7.0
5
www.fairchildsemi.com
DM93S62
9-
Input
Par
i
t
y
Chec
ker/
G
e
n
erat
or
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
PDF 
ZIP