2000 Fairchild Semiconductor Corporation
DS009821
www.fairchildsemi.com
October 1988
Revised April 2000
DM74LS181
4-
Bit
Ari
t
h
m
e
t
i
c
Logi
c Uni
t
DM74LS181
4-Bit Arithmetic Logic Unit
General Description
The DM74LS181 is a 4-bit Arithmetic Logic Unit (ALU)
which can perform all the possible 16 logic operations on
two variables and a variety of arithmetic operations.
Features
s
Provides 16 arithmetic operations: add, subtract, com-
pare, double, plus twelve other arithmetic operations
s
Provides all 16 logic operations of two variables:
exclusive-OR, compare, AND, NAND, OR, NOR, plus
ten other logic operations
s
Full lookahead for high speed arithmetic operation on
long words
Ordering Code:
Logic Symbols
Active High Operands
Active Low Operands
V
CC
=
Pin 24
GND
=
Pin 12
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
DM74LS181N
N24A
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
Pin Names
Description
A0A3
Operand Inputs (Active LOW)
B0B3
Operand Inputs (Active LOW)
S0S3
Function Select Inputs
M
Mode Control Input
C
n
Carry Input
F0F3
Function Outputs (Active LOW)
A
=
B
Comparator Output
G
Carry Generate Output (Active LOW)
P
Carry Propagate Output (Active LOW)
C
n
+
4
Carry Output
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2
DM74LS181
Functional Description
The DM74LS181 is a 4-bit high speed parallel Arithmetic
Logic Unit (ALU). Controlled by the four Function Select
inputs (S0S3) and the Mode Control input (M), it can per-
form all the 16 possible logic operations or 16 different
arithmetic operations on active HIGH or active LOW oper-
ands. The Function Table lists these operations
When the Mode Control input (M) is HIGH, all internal car-
ries are inhibited and the device performs logic operations
on the individual bits as listed. When the Mode Control
input is LOW, the carries are enabled and the device per-
forms arithmetic operations on the two 4-bit words. The
device incorporates full internal carry lookahead and pro-
vides for either ripple carry between devices using the C
n
+
4
output, or for carry lookahead between packages using the
signals P (Carry Propagate) and G (Carry Generate). In the
ADD mode, P indicates that F is 15 or more, while G indi-
cates that F is 16 or more. In the SUBTRACT mode, P indi-
cates that F is zero or less, while G indicates that F is less
than zero. P and G are not affected by carry in. When
speed requirements are not stringent, it can be used in a
simple ripple carry mode by connecting the Carry output
(C
n
+
4
) signal to the Carry input (C
n
) of the next unit. For
high speed operation the device is used in conjunction with
the 9342 or 93S42 carry lookahead circuit. One carry loo-
kahead package is required for each group of four
DM74LS181 devices. Carry lookahead can be provided at
various levels and offers high speed capability over
extremely long word lengths.
The A
=
B output from the device goes HIGH when all four
F outputs are HIGH and can be used to indicate logic
equivalence over four bits when the unit is in the subtract
mode. The A
=
B output is open-collector and can be wired-
AND with other A
=
B outputs to give a comparison for
more than four bits. The A
=
B signal can also be used with
the C
n
+
4
signal to indicate A
>
B and A
<
B.
The Function Table lists the arithmetic operations that are
performed without a carry in. An incoming carry adds a one
to each operation. Thus, select code LHHL generates A
minus B minus 1 (2s complement notation) without a carry
in and generates A minus B when a carry is applied.
Because subtraction is actually performed by complemen-
tary addition (1s complement), a carry out means borrow;
thus a carry is generated when there is no underflow and
no carry is generated when there is underflow. As indi-
cated, this device can be used with either active LOW
inputs producing active LOW outputs or with active HIGH
inputs producing active HIGH outputs. For either case the
table lists the operations that are performed to the oper-
ands labeled inside the logic symbol.
Function Table
Note 1: Each bit is shifted to the next most significant position.
Note 2: Arithmetic operations expressed in 2s complement notation.
Mode Select
Active LOW Operands
Active HIGH Operands
Inputs
& F
n
Outputs
& F
n
Outputs
Logic
Arithmetic
(Note 2)
Logic
Arithmetic
(Note 2)
S3
S2
S1
S0
(M
=
H)
(M
=
L) (C
n
=
L)
(M
=
H)
(M
=
L) (C
n
=
H)
L
L
L
L
A
A minus 1
A
A
L
L
L
H
AB
AB minus 1
A
+
B
A
+
B
L
L
H
L
A
+
B
AB minus 1
A B
A
+
B
L
L
H
H
Logic 1
minus 1
Logic 0
minus 1
L
H
L
L
A
+
B
A plus (A
+
B)
AB
A plus AB
L
H
L
H
B
AB plus (A
+
B)
B
(A
+
B) plus AB
L
H
H
L
A
B
A minus B minus 1
A
B
A minus B minus 1
L
H
H
H
A
+
B
A
+
B
AB
AB minus 1
H
L
L
L
A B
A plus (A
+
B)
A
+
B
A plus AB
H
L
L
H
A
B
A plus B
A
B
A plus B
H
L
H
L
B
AB plus (A
+
B)
B
(A
+
B) plus AB
H
L
H
H
A
+
B
A
+
B
AB
AB minus 1
H
H
L
L
Logic 0
A plus A (Note 1)
Logic 1
A plus A (Note 1)
H
H
L
H
AB
AB plus A
A
+
B
(A
+
B) plus A
H
H
H
L
AB
AB minus A
A
+
B
(A
+
B) plus A
H
H
H
H
A
A
A
A minus 1
3
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DM74LS181
Logic Diagram
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4
DM74LS181
Absolute Maximum Ratings
(Note 3)
Note 3: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 4: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
0.4
mA
I
OL
LOW Level Output Current
8
mA
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 4)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.5
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max,
2.7
V
Output Voltage
V
IL
=
Max
V
OL
LOW
Level V
CC
=
Min, I
OL
=
Max,
0.35
0.5
V
Output Voltage
V
IH
=
Min
I
OL
=
4 mA, V
CC
=
Min
0.25
0.4
I
I
Input Current @ Max
V
CC
=
Max, V
I
=
7V
M input
0.1
Input Voltage
A
n
, B
n
0.3
mA
S
n
0.4
C
n
0.5
I
IH
HIGH Level
V
CC
=
Max, V
I
=
2.7V
M input
20
Input Current
A
n
, B
n
60
A
S
n
80
C
n
100
I
IL
LOW Level
V
CC
=
Max, V
I
=
0.4V
M input
-
0.4
Input Current
A
n
, B
n
-
1.2
mA
S
n
-
1.6
C
n
-
2.0
I
OS
Short Circuit
V
CC
=
Max
-
20
-
100
mA
Output Current
(Note 5)
I
CC
Supply Current
V
CC
=
Max, B
n
, C
n
=
GND
37
mA
S
n
, M, A
n
=
4.5V
5
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DM74LS181
Switching Characteristics
V
CC
=
5V, T
A
=
25
C
Sum Mode Test Table 1
Function Inputs
S0
=
S3
=
4.5V, S1
=
S2
=
M
=
0V
Symbol
Parameter
Conditions
C
L
=
15 pF
Units
Min
Max
t
PLH
Propagation Delay
M
=
GND
27
ns
t
PHL
C
n
to C
n
+
4
20
t
PLH
Propagation Delay
M
=
GND
26
ns
t
PHL
C
n
to F
20
t
PLH
Propagation Delay
M, S
1
, S
2
=
GND;
29
ns
t
PHL
A or B to G (Sum)
S
1
, S
3
=
4.5V
23
t
PLH
Propagation Delay
M, S
0
, S
3
=
GND;
32
ns
t
PHL
A or B to G (Diff)
S
1
, S
2
=
4.5V
26
t
PLH
Propagation Delay
M, S
1
, S
2
=
GND;
30
ns
t
PHL
A or B to P (Sum)
S
0
, S
3
=
4.5V
30
t
PLH
Propagation Delay
M, S
0
, S
3
=
GND;
30
ns
t
PHL
A or B to P (Diff)
S
1
, S
2
=
4.5V
33
t
PLH
Propagation Delay
M, S
1
, S
2
=
GND;
32
ns
t
PHL
A
i
or B
i
to F
i
(Sum)
S
0
, S
3
=
4.5V
25
t
PLH
Propagation Delay
M, S
0
, S
3
=
GND;
32
ns
t
PHL
A
i
or B
i
to F
i
(Diff)
S
1
, S
2
=
4.5V
33
t
PLH
Propagation Delay
M
=
4.5V
33
ns
t
PHL
A or B to F (Logic)
29
t
PLH
Propagation Delay
M, S
1
, S
2
=
GND;
38
ns
t
PHL
A or B to C
n
+
4
(Sum)
S
0
, S
3
=
4.5V
38
t
PLH
Propagation Delay
M, S
0
, S
3
=
GND;
41
ns
t
PHL
A or B to C
n
+
4
(Diff)
S
1
, S
2
=
4.5V
41
t
PLH
Propagation Delay
M, S
0
, S
3
=
GND;
50
ns
t
PHL
A or B to A
=
B
S
1
, S
2
=
4.5V;
62
R
L
=
2 k
to 5.0V
Input
Other Input
Other Data Inputs
Output
Symbol
Under
Same Bit
Under
Test
Apply
Apply
Apply
Apply
Test
4.5V
GND
4.5V
GND
t
PLH
A
i
B
i
None
Remaining
C
n
F
i
t
PHL
A and B
t
PLH
B
i
A
i
None
Remaining
C
n
F
i
t
PHL
A and B
t
PLH
A
B
None
None
Remaining
P
t
PHL
A and B, C
n
t
PLH
B
A
None
None
Remaining
P
t
PHL
A and B, C
n
t
PLH
A
None
B
Remaining
Remaining
G
t
PHL
B
A, C
n
t
PLH
B
None
A
Remaining
Remaining
G
t
PHL
B
A, C
n
t
PLH
A
None
B
Remaining
Remaining
C
n
+
4
t
PHL
B
A, C
n
t
PLH
B
None
A
Remaining
Remaining
C
n
+
4
t
PHL
B
A, C
n
t
PLH
C
n
None
None
All
All
Any F
t
PHL
A
B
or C
n
+
4
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