2002 Fairchild Semiconductor Corporation
DS011635
www.fairchildsemi.com
August 1993
Revised February 2002
7
4
VH
C16
1
4-
Bit
Bi
nary Counte
r
w
i
th Asynchr
onous C
l
ear
74VHC161
4-Bit Binary Counter with Asynchronous Clear
General Description
The VHC161 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC161 is a high-speed synchronous modulo-
16 binary counter. This device is synchronously presettable
for application in programmable dividers and have two
types of Count Enable inputs plus a Terminal Count output
for versatility in forming synchronous multistage counters.
The VHC161 has an asynchronous Master Reset input that
overrides all other inputs and forces the outputs LOW. An
input protection circuit insures that 0V to 7V can be applied
to the input pins without regard to the supply voltage. This
device can be used to interface 5V to 3V systems and two
supply systems such as battery backup. This circuit pre-
vents device destruction due to mismatched supply and
input voltages.
Features
s
High Speed:
f
MAX
=
185 MHz (typ) at T
A
=
25
C
s
Synchronous counting and loading
s
High-speed synchronous expansion
s
Low power dissipation:
I
CC
=
4
A (max) at T
A
=
25
C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
s
Power down protection provided on all inputs
s
Low noise: V
OLP
=
0.8V (max)
s
Pin and function compatible with 74HC161
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Order Number
Package Number
Package Description
74VHC161M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC161SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC161MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC161N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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74
V
HC161
Connection Diagram
Pin Descriptions
Functional Description
The VHC161 counts in modulo-16 binary sequence. From
state 15 (HHHH) it increments to state 0 (LLLL). The clock
inputs of all flip-flops are driven in parallel through a clock
buffer. Thus all changes of the Q outputs (except due to
Master Reset of the VHC161) occur as a result of, and syn-
chronous with, the LOW-to-HIGH transition of the CP input
signal. The circuits have four fundamental modes of opera-
tion, in order of precedence: asynchronous reset, parallel
load, count-up and hold. Five control inputs--Master
Reset, Parallel Enable (PE), Count Enable Parallel (CEP)
and Count Enable Trickle (CET)--determine the mode of
operation, as shown in the Mode Select Table. A LOW sig-
nal on MR overrides all other inputs and asynchronously
forces all outputs LOW. A LOW signal on PE overrides
counting and allows information on the Parallel Data (P
n
)
inputs to be loaded into the flip-flops on the next rising
edge of CP. With PE and MR HIGH, CEP and CET permit
counting when both are HIGH. Conversely, a LOW signal
on either CEP or CET inhibits counting.
The VHC161 uses D-type edge-triggered flip-flops and
changing the PE, CEP and CET inputs when the CP is in
either state does not cause errors, provided that the recom-
mended setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchro-
nous multistage counters, the TC outputs can be used with
the CEP and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limit on clock frequency. For faster clock
rates, the carry lookahead connections shown in Figure 2
are recommended. In this scheme the ripple delay through
the intermediate stages commences with the same clock
that causes the first stage to tick over from max to min to
start its final cycle. Since this final cycle requires 16 clocks
to complete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that lim-
its the clock period is the CP to TC delay of the first stage
plus the CEP to CP setup time of the last stage. The TC
output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, registers or
counters.
Logic Equations: Count Enable
=
CEP CET PE
TC
=
Q
0
Q
1
Q
2
Q
3
CET
FIGURE 1. Multistage Counter with Ripple Carry
FIGURE 2. Multistage Counter with Lookahead Carry
Pin Names
Description
CEP
Count Enable Parallel Input
CET
Count Enable Trickle Input
CP
Clock Pulse Input
MR
Asynchronous Master Reset Input
P
0
P
3
Parallel Data Inputs
PE
Parallel Enable Inputs
Q
0
Q
3
Flip-Flop Outputs
TC
Terminal Count Output
3
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Mode Select Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
State Diagram
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
MR
PE
CET CEP
Action on the Rising
Clock Edge (
)
L
X
X
X
Reset (Clear)
H
L
X
X
Load (P
n
Q
n
)
H
H
H
H
Count (Increment)
H
H
L
X
No Change (Hold)
H
H
X
L
No Change (Hold)
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74
V
HC161
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter guaranteed by design.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Voltage (V
IN
)
-
0.5V to
+
7.0V
DC Output Voltage (V
OUT
)
-
0.5V to V
CC
+
0.5V
Input Diode Current (I
IK
)
-
20 mA
Output Diode Current (I
OK
)
20 mA
DC Output Current (I
OUT
)
25 mA
DC V
CC
/GND Current (I
CC
)
50 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
Supply Voltage (V
CC
)
2.0V to
+
5.5V
Input Voltage (V
IN
)
0V to
+
5.5V
Output Voltage (V
OUT
)
0V to V
CC
Operating Temperature (T
OPR
)
-
40
C to
+
85
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
3.3V
0.3V
0
100 ns/V
V
CC
=
5.0V
0.5V
0
20 ns/V
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level
2.0
1.50
1.50
V
Input Voltage
3.0
-
5.5
0.7 V
CC
0.7 V
CC
V
IL
LOW Level
2.0
0.50
0.50
V
Input Voltage
3.0
-
5.5
0.3 V
CC
0.3 V
CC
V
OH
HIGH Level
2.0
1.9
2.0
1.9
Output Voltage
3.0
2.9
3.0
2.9
V
I
OH
=
-
50
A
4.5
4.4
4.5
4.4
V
IN
=
V
IH
3.0
2.58
2.48
V
or V
IL
I
OH
=
-
4 mA
4.5
3.94
3.80
I
OH
=
-
8 mA
V
OL
LOW Level
2.0
0.0
0.1
0.1
Output Voltage
3.0
0.0
0.1
0.1
V
I
OL
=
50
A
4.5
0.0
0.1
0.1
V
IN
=
V
IH
3.0
0.36
0.44
V
or V
IL
I
OL
=
4 mA
4.5
0.36
0.44
I
OL
=
8 mA
I
IN
Input Leakage Current
0
-
5.5
0.1
1.0
A
V
IN
=
5.5V or GND
I
CC
Quiescent Supply Current
5.5
4.0
40.0
A
V
IN
=
V
CC
or GND
Symbol
Parameter
V
CC
T
A
=
25
C
Units
Conditions
(V)
Typ
Limits
V
OLP
Quiet Output Maximum
5.0
0.4
0.8
V
C
L
=
50 pF
(Note 3)
Dynamic V
OL
V
OLV
Quiet Output Minimum
5.0
-
0.4
-
0.8
V
C
L
=
50 pF
(Note 3)
Dynamic V
OL
V
IHD
Minimum HIGH Level
5.0
3.5
V
C
L
=
50 pF
(Note 3)
Dynamic Input Voltage
V
ILD
Maximum LOW Level
5.0
1.5
V
C
L
=
50 pF
(Note 3)
Dynamic Input Voltage
5
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AC Electrical Characteristics
Note 4: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr)
=
C
PD
* V
CC
* f
IN
+
I
CC
.
When the outputs drive a capacitive load, total current consumption is the sum of C
PD
, and
I
CC
which is obtained from the following formula:
C
Q0
C
Q3
and C
TC
are the capacitances at Q0Q3 and TC, respectively. F
CP
is the input frequency of the CP.
Symbol
Parameter
V
CC
T
A
=
25
C
T
A
=
-
40
to
+
85
C
Units
Conditions
(V)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
3.3
0.3
8.3
12.8
1.0
15.0
ns
C
L
=
15 pF
t
PHL
Time (CPQ
n
)
10.8
16.3
1.0
18.5
C
L
=
50 pF
5.0
0.5
4.9
8.1
1.0
9.5
ns
C
L
=
15 pF
6.4
10.1
1.0
11.5
C
L
=
50 pF
t
PLH
Propagation Delay
3.3
0.3
8.7
13.6
1.0
16.0
ns
C
L
=
15 pF
t
PHL
Time (CPTC, Count)
11.2
17.1
1.0
19.5
C
L
=
50 pF
5.0
0.5
4.9
8.1
1.0
9.5
ns
C
L
=
15 pF
6.4
10.1
1.0
11.5
C
L
=
50 pF
t
PLH
Propagation Delay
3.3
0.3
11.0
17.2
1.0
20.0
ns
C
L
=
15 pF
t
PHL
Time (CPTC, Load)
13.5
20.7
1.0
23.5
C
L
=
50 pF
5.0
0.5
6.2
10.3
1.0
12.0
ns
C
L
=
15 pF
7.7
12.3
1.0
14.0
C
L
=
50 pF
t
PLH
Propagation Delay
3.3
0.3
7.5
12.3
1.0
14.5
ns
C
L
=
15 pF
t
PHL
Time (CETTC)
10.5
15.8
1.0
18.0
C
L
=
50 pF
5.0
0.5
4.9
8.1
1.0
9.5
ns
C
L
=
15 pF
6.4
10.1
1.0
11.5
C
L
=
50 pF
t
PHL
Propagation Delay
3.3
0.3
8.9
13.6
1.0
16.0
ns
C
L
=
15 pF
Time (MR Q
n
)
11.2
17.1
1.0
19.5
C
L
=
50 pF
5.0
0.5
5.5
9.0
1.0
10.5
ns
C
L
=
15 pF
7.0
11.0
1.0
12.5
C
L
=
50 pF
t
PHL
Propagation Delay
3.3
0.3
8.4
13.2
1.0
15.5
ns
C
L
=
15 pF
Time (MR TC)
10.9
16.7
1.0
19.0
C
L
=
50 pF
5.0
0.5
5.0
8.6
1.0
10.0
ns
C
L
=
15 pF
6.5
10.6
1.0
12.0
C
L
=
50 pF
f
MAX
Maximum Clock
3.3
0.3
80
130
70
MHz
C
L
=
15 pF
Frequency
55
85
50
C
L
=
50 pF
5.0
0.5
135
185
115
MHz
C
L
=
15 pF
95
125
85
C
L
=
50 pF
C
IN
Input Capacitance
4
10
10
pF
V
CC
=
Open
C
PD
Power Dissipation Capacitance
23
pF
(Note 4)
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