1999 Fairchild Semiconductor Corporation
DS010902
www.fairchildsemi.com
January 1991
Revised August 1999
7
4FR543 Oct
a
l
Lat
ched T
r
anscei
ver
wit
h
3-ST
A
T
E Outpu
t
s
74FR543
Octal Latched Transceiver with 3-STATE Outputs
General Description
The 74FR543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. Both the A and B outputs will source 15 mA and sink
64 mA.
Features
s
Functionally equivalent to 74F543
s
Back-to-back registers for storage
s
Bidirectional data path
s
A and B outputs have current sourcing capability of
15 mA and current sinking capability of 64 mA
s
Separate controls for data flow in each direction
s
Guaranteed pin-to-pin skew
s
Guaranteed 4000V minimum ESD protection
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Order Number
Package Number
Package Description
74FR543SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74FR543SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
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2
74FR543
Pin Descriptions
Functional Description
The 74FR543 contains two sets of D-type latches, with
separate input and output controls for each. For data flow
from A-to-B, for example, the A-to-B Enable (CEAB) input
must be LOW in order to enter data from the A Port or take
data from the B Port as indicated in the Data I/O Control
Table. With CEAB LOW, a LOW signal on (LEAB) input
makes the A-to-B latches transparent; a subsequent LOW-
to-HIGH transition of the LEAB line puts the A latches in
the storage mode and their outputs no longer change with
the A inputs. With CEAB and OEAB both LOW, the B out-
put buffers are active and reflect the data present on the
output of the A latches. Control of data flow from B-to-A is
similar, but using the CEBA, LEBA and OEBA.
Data I/O Control Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Logic Diagram
Pin Names
Description
OEAB, OEBA
Output Enable Inputs
LEAB, LEBA
Latch Enable Inputs
CEAB, CEBA
Chip Enable Inputs
A
0
A
7
Side A Inputs or 3-STATE Outputs
B
0
B
7
Side B Inputs or 3-STATE Outputs
Inputs
Latch Output
CEAB LEAB OEAB
Status
Buffers
H
X
X
Latched
High Z
X
H
X
Latched
--
L
L
X
Transparent
--
X
X
H
--
High Z
L
X
L
--
Driving
3
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7
4FR543
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH Voltage
2.4
V
Min
I
OH
=
-
3 mA (A
n
, B
n
)
2.0
V
Min
I
OH
=
-
15 mA (A
n
, (B
n
)
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
=
64 mA (A
n
, B
n
)
I
IH
Input HIGH Current
5
A
Max
V
IN
=
2.7V
I
BVI
Input HIGH Current
7
A
Max
V
IN
=
7.0V (Control Pins)
Breakdown Test
I
BVIT
Input HIGH Current
100
A
Max
V
IN
=
5.5V (A
n
, B
n
)
Breakdown Test (I/O)
I
IL
Input LOW Current
-
150
A
Max
V
IN
=
0.5 (CEAB, CEBA)
-
100
A
Max
V
IN
=
0.5 (LEAB, LEBA, OEAB, OEBA)
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
=
1.9
A,
All Other Pins Grounded
I
OD
Output Circuit Leakage Test
3.75
A
0.0
V
IOD
=
150 mV,
All Other Pins Grounded
I
IH
+
I
OZH
Output Leakage Current
25
A
Max
V
OUT
=
2.7V (A
n
, B
n
)
I
IL
+
I
OZL
Output Leakage Current
-
150
A
Max
V
OUT
=
0.5V (A
n
, B
n
)
I
OS
Output Short-Circuit Current
-
100
-
225
mA
Max
V
OUT
=
0.0V (A
n
, B
n
)
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
=
V
CC
(A
n
, B
n
)
I
ZZ
Bus Drainage Test
100
A
0.0
V
OUT
=
5.25V (A
n
, B
n
)
I
CCH
Power Supply Current
59
72
mA
Max
All Outputs HIGH
I
CCL
Power Supply Current
87
102
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
69
85
mA
Max
Outputs 3-STATE
C
IN
Input Capacitance
8.0
pF
5.0
Control Pins
17.0
pF
5.0
A
n
, B
n
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4
74FR543
AC Electrical Characteristics
AC Operating Requirements
Extended AC Electrical Characteristics
Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase,
i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.
Note 4: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 5: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi-
cation applies to any outputs switching HIGH-to-LOW, (t
OSHL
), LOW-to-HIGH, (t
OSLH
), or HIGH-to-LOW and/or LOW-to-HIGH, (t
OST
). Specifications guaran-
teed with all outputs switching in phase.
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
1.3
3.0
4.7
1.3
4.7
ns
t
PHL
A
n
to B
n
or B
n
to A
n
1.3
2.6
4.7
1.3
4.7
t
PLH
Propagation Delay
2.3
5.7
8.5
2.3
8.5
ns
t
PHL
LEAB to B, LEBA to A
2.3
4.0
8.5
2.3
8.5
t
PZH
Output Enable Time
2.3
4.3
7.4
2.3
7.4
ns
t
PZL
2.3
4.9
7.4
2.3
7.4
t
PHZ
Output Disable Time
1.6
3.9
7.0
1.6
7.0
ns
t
PLZ
1.6
3.5
7.0
1.6
7.0
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
2.5
0.5
2.5
ns
t
S
(L)
D
n
to LE
2.5
0.1
2.5
t
H
(H)
Hold Time, HIGH or LOW
2.0
0.0
2.0
ns
t
H
(L)
D
n
to LE
2.0
-
0.6
2.0
t
W
(H)
LE Pulse Width HIGH
6.0
3.6
6.0
ns
Symbol
Parameter
T
A
=
0
C to
+
70
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
250 pF
Eight Outputs Switching
(Note 4)
(Note 3)
Min
Max
Min
Max
t
PLH
Propagation Delay
1.3
6.3
3.2
8.7
ns
t
PHL
A
n
to B
n
or B
n
to A
n
1.3
6.3
3.2
8.7
t
PLH
Propagation Delay
2.3
10.2
4.2
12.8
ns
t
PHL
LEAB to B, LEBA to A
2.3
10.2
4.2
12.8
t
PZH
Output Enable Time
2.3
11.1
ns
t
PZL
2.3
11.1
t
PHZ
Output Disable Time
1.6
7.2
ns
t
PLZ
1.6
7.2
t
OSHL
Pin-to-Pin Skew
1.2
ns
(Note 5)
for HL Transitions
t
OSLH
Pin-to-Pin Skew
1.0
ns
(Note 5)
for LH Transitions
t
OST
Pin-to-Pin Skew
3.1
ns
(Note 5)
for HL/LH Transitions
5
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7
4FR543
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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6
74FR543 Octal
La
tched T
r
an
sceive
r
wi
th 3-
S
T
A
T
E O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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