Exar

Corporation 48720 Kato Road, Fremont CA, 94538

(510) 668-7000

FAX (510) 668-7017

www.exar.com

PRELIMINARY

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

FEBRUARY 2004

REV. P1.3.4

GENERAL DESCRIPTION

The XRT83L34 is a fully integrated Quad (four
channel) long-haul and short-haul line interface unit
for T1 (1.544Mbps) 100

, E1 (2.048Mbps) 75

120

or J1 110

applications.

In long-haul applications the XRT83L34 accepts
signals that have been attenuated from 0 to 36dB at
772kHz in T1 mode (equivalent of 0 to 6000 feet of
cable loss) or 0 to 43dB at 1024kHz in E1 mode.

In T1 applications, the XRT83L34 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements as
well as for Channel Service Units (CSU) Line Build
Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB
as required by FCC rules. It also provides
programmable transmit pulse generators for each
channel that can be used for output pulse shaping
allowing performance improvement over a wide
variety of conditions.

The XRT83L34 provides both a parallel Host
microprocessor interface as well as a Hardware mode
for programming and control.

Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. An on-chip

crystal-less jitter attenuator with a 32 or 64 bit FIFO
can be placed either in the receive or the transmit
path with loop bandwidths of less than 3Hz. The
XRT83L34 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75

100

110

and 120

for both transmitter and

receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing for redundancy applications The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a
variety of external clock sources.

APPLICATIONS

T1 Digital Cross-Connects (DSX-1)

ISDN Primary Rate Interface

CSU/DSU E1/T1/J1 Interface

T1/E1/J1 LAN/WAN Routers

Public switching Systems and PBX Interfaces

T1/E1/J1 Multiplexer and Channel Banks

Features (See Page 2)

IGURE

1 B

LOCK

IAGRAM

THE

XRT83L34 T1/E1/J1 LIU (H

OST

ODE

)

O ne of four channels, CHANNEL_n - (n= 0:3)

HW /HO ST

W R_R/W

RD_DS

A LE_A S

RDY _DTA CK

INT

ICT

TPO S_n/TDATA _n

TNE G_n/CO DES _n

TCLK _n

RCLK _n

RNE G_n/LCV _n

RP OS_n/RDATA _n

RLOS _n

RTIP_n
RRING_n

MAST ER CLO CK S YNT H ESIZER

Q RSS

PAT T ER N

GEN ERAT O R

DMO _n

TTIP_n

TRING _n

TXON_n

HDB 3/

B8ZS

ENCO DER

T X /R X JIT T ER

AT T ENUAT O R

T IMIN G

CO NT R O L

T X FIL T ER

& PUL SE

SHAPER

LINE
DRIVER

D RIVE

MON IT O R

L O CAL

ANAL OG

LO O PBACK

REM OT E

L O OPB AC K

D IG IT AL

LO OPB AC K

HDB 3/

B8ZS

DECO DER

T X /R X JIT T ER

AT T ENUAT O R

T IMING &

DAT A

REC O VERY

PEAK

DET ECT O R

& S LICER

Q RSS

D ET ECT OR

NE T W OR K

L OO P

D ET ECT OR

EQ UALIZ ER

C ON T RO L

AIS

DET EC T O R

LO S

DET EC T O R

L BO [3:0]

LO O PBACK

ENABL E

SEL

ECT

NL CD EN AB LE

Q RSS ENABL E

P TS1

P TS2

D[7:0]

P CLK

A[7:0]
RE SET

MIC RO PRO CESSO R CO NT RO LL ER

T EST

DF M

T AO S

ENABL E

MCLK E1

MCLK T1

MCLKO UT

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

FEATURES

Fully integrated four channel long-haul or short-
haul transceivers for E1,T1 or J1 applications

Adaptive Receive Equalizer for up to 36dB cable
attenuation

Programable Transmit Pulse Shaper for E1,T1 or J1
short-haul interfaces

Five fixed transmit pulse settings for T1 short-haul
applications plus a fully programmable waveform
generator for transmit output pulse shaping that
can be used for both T1 and E1 modes.

Transmit Line Build-Outs (LBO) for T1 long-haul
application from 0dB to -22.5dB in three 7.5dB
steps

Selectable receiver sensitivity from 0 to 36dB cable
loss for T1 @772kHz and 0 to 43dB for E1
@1024kHz

Receive monitor mode handles 0 to 29dB resistive
attenuation along with 0 to 6dB of cable attenuation
for E1 and 0 to 3dB of cable attenuation for T1
modes

Supports 75

and 120

(E1), 100

(T1) and 110

(J1) applications

Internal and/or external impedance matching for
75

, 100

110

and 120

Tri-State transmit output and receive input
capability for redundancy applications

Provides High Impedance for Tx and Rx during
power off

Transmit return loss meets or exceeds ETSI 300-
166 standard

On-chip digital clock recovery circuit for high input
jitter tolerance

Crystal-less digital jitter attenuator with 32-bit or 64-
bit FIFO selectable either in transmit or receive path

On-chip frequency multiplier generates T1 or E1
Master clocks from variety of external clock sources

High receiver interference immunity

On-chip transmit short-circuit protection and
limiting, and driver fail monitor output (DMO)

Receive loss of signal (RLOS) output

On-chip HDB3/B8ZS/AMI encoder/decoder
functions

QRSS pattern generator and detection for testing
and monitoring

Error and Bipolar Violation Insertion and Detection

IGURE

2 B

LOCK

IAGRAM

THE

XRT83L34 T1/E1/J1 LIU (H

ARDWARE

ODE

)

One of four Ch annels, C HAN NEL_n - (n=0 : 3)

HW /HO ST

G AUG E
JAS EL1
JAS EL0

RXT S EL

T XT S EL

T E RS EL1
T E RS EL0

RXRE S1
RXRE S0

IC T

MC LKE1

M C LKT1

CLKSE L[2:0]

T POS_n/TDA TA_n

TNEG _n/C OD ES_n

TC LK_n

RC LK_n

R NEG _n/LC V_n

RPO S_n/RDA TA_n

RLO S_n

R TIP_n
R RIN G_n

MAST ER CL OC K SYNT H ESIZER

Q RSS

PAT T ERN

GENE RAT OR

DMO_n

T T IP_n

T RING _n

T XO N_n

HDB3 /

B8Z S

EN CO DER

T X/RX JIT T ER

AT T EN UAT OR

T IMING

CO NT R OL

T X FIL T ER

& PUL SE

SHAPER

L INE
D RIVER

L O CAL

AN AL OG

L OO PBACK

R EMOT E

LO O PBACK

D IGIT AL

LO O PBAC K

HDB3 /

B8Z S

D ECO DER

T X/RX JIT T ER

AT T EN UAT OR

T IMIN G &

DAT A

REC OVER Y

PEAK

DET E CT O R

& SL ICER

QR SS

DET ECT O R

NET W O RK

LO OP

DET ECT O R

EQ UALIZ ER

CO NT R OL

AIS

DET ECT O R

LO S

DET EC T OR

L BO [3 :0]

L OO PBACK

ENAB LE

SELEC

NL CD ENABL E

QR SS ENAB LE

HARW AR E C ON T RO L

T EST

RESE T
T RA T IO
SR/DR
EQ C[4:0]
T CLK E
RCLK E
RXMUT E
AT AO S

DR IVE

MO NIT O R

DF M

MCLKO UT

T AO S_n

LO OP 1_n
LO OP 0_n

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

IGURE

3 P

THE

XRT83L34

TC LK _2

TP O S _2/TD A TA _2

TN E G _2/C O D E S _2

u P T S 1/RC LK E

uP TS 2/TC LK E

R X R E S 0
R X R E S 1

R X TS E L

TX TS E L

TE R S E L1

TE R S E L0

G N D

D V D D

D G N D

IN T/TR A TIO

IC T

R E S E T

TX O N _0

TX O N _1

TX O N _2

TX O N _3

TN E G _1/C O D E S _1

TP O S _1/TD A TA _1

TC LK _1

103

104

105
106

107
108

109

110

111

112

113

114
115

116

117
118

119

120

121

122

123
124

125

126
127

128

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

D M O _0

A [0]/E Q C 0

A [1]/E Q C 1

A [2]/E Q C 2

A [3]/E Q C 3

A [4]/E Q C 4
A [5]/JA S E L0

A [6]/JA S E L1

D G N D

D G N D
D V D D

D V D D

uP C LK /A TA O S

D [0]/LO O P 0_3

D [1]/LO O P 1_3

D [2]/LO O P 0_2
D [3]/LO O P 1_2

D [4]/LO O P 0_1

D [5]/LO O P 1_1

D [6]/LO O P 0_0

D [7]/LO O P 1_0
A G N D
A V D D

C LK S E L2

102

101

100

LK_3

/
TD

/
CO

RCL

_3/

V_3

/
R

DD_

I
P

RRI

TTI

I
N

DD_

TTI

ND_

RRI

I
P

/
R

_2/

LCV

RCL

RDY

/
R

/
T

E_AS

/
T

S_1

/
W

/
T

/
TD

/
CO

RCL

_0/

LCV

_0/

I
P

RRI

ND_

TTI

I
N

/
D

I
N

DD_

TTI

RRI

I
P

DD_

/
RDA

_1/

RCL

LL_1

LL_2

LL_1

NDP

KSE

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

TABLE OF CONTENTS

GENERAL DESCRIPTION ................................................................................................. 1

PPLICATIONS

.............................................................................................................................................. 1

Figure 1 Block Diagram of the XRT83L34 T1/E1/J1 LIU (Host Mode) ............................................ 1
Figure 2 Block Diagram of the XRT83L34 T1/E1/J1 LIU (Hardware Mode) ................................... 2

EATURES

.................................................................................................................................................... 2

ORDERING INFORMATION ...................................................................................................................... 3

Figure 3 Pin Out of the XRT83L34 .................................................................................................... 4

TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTION BY FUNCTION ................................................................................... 5

ECEIVE

ECTIONS

...................................................................................................................................... 5

RANSMITTER

ECTIONS

.............................................................................................................................. 7

ICROPROCESSOR

NTERFACE

...................................................................................................................... 9

ITTER

TTENUATOR

.................................................................................................................................. 12

LOCK

YNTHESIZER

.................................................................................................................................. 13

LARM

UNCTION

//R

EDUNDANCY

UPPORT

................................................................................................. 14

OWER

AND

GROUND

................................................................................................................................. 18

FUNCTIONAL DESCRIPTION ......................................................................................... 19

ASTER

LOCK

ENERATOR

...................................................................................................................... 19

Figure 4. Two Input Clock Source .................................................................................................. 19
Figure 5. One Input Clock Source .................................................................................................. 19

RECEIVER ........................................................................................................................ 20

ECEIVER

NPUT

......................................................................................................................................... 20

ABLE

1: M

ASTER

LOCK

ENERATOR

............................................................................................... 20

ECEIVE

ONITOR

ODE

........................................................................................................................... 21

ECEIVER

OSS

IGNAL

(RLOS) ........................................................................................................... 21

Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ............... 21
Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ......................... 22
Figure 8. Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition ............... 22

ECEIVE

HDB3/B8ZS D

ECODER

................................................................................................................ 23

ECOVERED

LOCK

(RCLK) S

AMPLING

DGE

............................................................................................ 23

Figure 9. Simplified Diagram of Extended RLOS mode (E1 Only) ............................................... 23
Figure 10. Receive Clock and Output Data Timing ....................................................................... 23

ITTER

TTENUATOR

.................................................................................................................................. 24

APPED

LOCK

(JA M

UST

NABLED

THE

RANSMIT

ATH

) ................................................................. 24

ABLE

2: M

AXIMUM

IDTH

FOR

ULTIPLEXER

APPER

PPLICATIONS

........................................ 24

RBITRARY

ULSE

ENERATOR

FOR

AND

1 .......................................................................................... 25

TRANSMITTER ................................................................................................................. 25

IGITAL

ATA

ORMAT

............................................................................................................................... 25

RANSMIT

LOCK

(TCLK) S

AMPLING

DGE

................................................................................................ 25

Figure 11. Arbitrary Pulse Segment Assignment .......................................................................... 25

RANSMIT

HDB3/B8ZS E

NCODER

.............................................................................................................. 26

Figure 12. Transmit Clock and Input Data Timing ........................................................................ 26
T

ABLE

3: E

XAMPLES

HDB3 E

NCODING

........................................................................................... 26

ABLE

4: E

XAMPLES

B8ZS E

NCODING

........................................................................................... 26

RIVER

AILURE

ONITOR

(DMO) .............................................................................................................. 27

RANSMIT

ULSE

HAPER

& L

INE

UILD

(LBO)

CIRCUIT

...................................................................... 27

ABLE

5: R

ECEIVE

QUALIZER

ONTROL

AND

RANSMIT

INE

UILD

-O

ETTINGS

........................... 27

TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 29

RECEIVER (C

HANNELS

0 - 3) ................................................................................................................... 29

Internal Receive Termination Mode .......................................................................................................... 29

ABLE

6: R

ECEIVE

ERMINATION

ONTROL

.......................................................................................... 29

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

Figure 13. Simplified Diagram for the Internal Receive and Transmit Termination Mode ........ 29
T

ABLE

7: R

ECEIVE

ERMINATIONS

....................................................................................................... 30

Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ............. 30

TRANSMITTER (C

HANNELS

0 - 3) ............................................................................................................ 31

Transmit Termination Mode ...................................................................................................................... 31
External Transmit Termination Mode ........................................................................................................ 31

Figure 15. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ................... 31
T

ABLE

8: T

RANSMIT

ERMINATION

ONTROL

....................................................................................... 31

ABLE

9: T

ERMINATION

ELECT

ONTROL

.......................................................................................... 31

REDUNDANCY APPLICATIONS ............................................................................................................. 32

ABLE

10: T

RANSMIT

ERMINATION

ONTROL

..................................................................................... 32

ABLE

11: T

RANSMIT

ERMINATIONS

................................................................................................... 32

TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 33

Figure 16. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ....... 34
Figure 17. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy ............. 34
Figure 18. Simplified Block Diagram - Transmit Section for N+1 Redundancy ......................... 35
Figure 19. Simplified Block Diagram - Receive Section for N+1 Redundancy .......................... 36

ATTERN

RANSMIT

AND

ETECT

UNCTION

............................................................................................... 37

RANSMIT

NES

(TAOS) .................................................................................................................... 37

ETWORK

OOP

ODE

ETECTION

AND

RANSMISSION

.............................................................................. 37

ABLE

12: P

ATTERN

TRANSMISSION

CONTROL

..................................................................................... 37

ABLE

13: L

OOP

-C

ODE

ETECTION

ONTROL

..................................................................................... 37

RANSMIT

AND

ETECT

UASI

-R

ANDOM

IGNAL

OURCE

(TDQRSS) ......................................................... 38

OOP

-B

ACK

ODES

................................................................................................................................... 39

OCAL

NALOG

OOP

-B

ACK

(ALOOP) ....................................................................................................... 39

ABLE

14: L

OOP

BACK

CONTROL

ARDWARE

MODE

........................................................................ 39

ABLE

15: L

OOP

BACK

CONTROL

OST

MODE

................................................................................. 39

Figure 20. Local Analog Loop-back signal flow ........................................................................... 39

EMOTE

OOP

-B

ACK

(RLOOP) ................................................................................................................. 40

Figure 21. Remote Loop-back mode with jitter attenuator selected in receive path ................. 40
Figure 22. Remote Loop-back mode with jitter attenuator selected in Transmit path .............. 40

IGITAL

OOP

-B

ACK

(DLOOP) .................................................................................................................. 41

UAL

OOP

-B

ACK

...................................................................................................................................... 41

Figure 23. Digital Loop-back mode with jitter attenuator selected in Transmit path ................ 41
Figure 24. Signal flow in Dual loop-back mode ............................................................................ 41

MICROPROCESSOR PARALLEL INTERFACE .............................................................. 42

ABLE

16: M

ICROPROCESSOR

INTERFACE

SIGNAL

DESCRIPTION

........................................................... 42

ICROPROCESSOR

EGISTER

ABLES

........................................................................................................ 43

ABLE

17: M

ICROPROCESSOR

EGISTER

DDRESS

............................................................................. 43

ABLE

18: M

ICROPROCESSOR

EGISTER

ESCRIPTION

................................................................. 43

ICROPROCESSOR

EGISTER

ESCRIPTIONS

............................................................................................. 46

ABLE

19: M

ICROPROCESSOR

EGISTER

#0, B

ESCRIPTION

........................................................... 46

ABLE

20: M

ICROPROCESSOR

EGISTER

#1, B

ESCRIPTION

........................................................... 47

ABLE

21: M

ICROPROCESSOR

EGISTER

#2, B

ESCRIPTION

........................................................... 49

ABLE

22: M

ICROPROCESSOR

EGISTER

#3, B

ESCRIPTION

........................................................... 51

ABLE

23: M

ICROPROCESSOR

EGISTER

#4, B

ESCRIPTION

........................................................... 53

ABLE

24: M

ICROPROCESSOR

EGISTER

#5, B

ESCRIPTION

........................................................... 54

ABLE

25: M

ICROPROCESSOR

EGISTER

#6, B

ESCRIPTION

........................................................... 56

ABLE

26: M

ICROPROCESSOR

EGISTER

#7, B

ESCRIPTION

........................................................... 57

ABLE

27: M

ICROPROCESSOR

EGISTER

#8, B

ESCRIPTION

........................................................... 58

ABLE

28: M

ICROPROCESSOR

EGISTER

#9, B

ESCRIPTION

........................................................... 58

ABLE

29: M

ICROPROCESSOR

EGISTER

#10, B

ESCRIPTION

......................................................... 59

ABLE

30: M

ICROPROCESSOR

EGISTER

#11, B

ESCRIPTION

......................................................... 59

ABLE

31: M

ICROPROCESSOR

EGISTER

#12, B

ESCRIPTION

......................................................... 60

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

III

ABLE

32: M

ICROPROCESSOR

EGISTER

#13, B

ESCRIPTION

.......................................................... 60

ABLE

33: M

ICROPROCESSOR

EGISTER

#14, B

ESCRIPTION

.......................................................... 61

ABLE

34: M

ICROPROCESSOR

EGISTER

#15, B

ESCRIPTION

.......................................................... 61

ABLE

35: M

ICROPROCESSOR

EGISTER

#64, B

ESCRIPTION

.......................................................... 62

CLOCK SELECT REGISTER ........................................................................................... 63

Figure 25. Register 0x81h Sub Registers ...................................................................................... 63
T

ABLE

36: M

ICROPROCESSOR

EGISTER

#65, B

ESCRIPTION

.......................................................... 64

ABLE

37: M

ICROPROCESSOR

EGISTER

#66, B

ESCRIPTION

.......................................................... 65

ELECTRICAL CHARACTERISTICS ................................................................................ 67

ABLE

38: A

BSOLUTE

AXIMUM

ATINGS

........................................................................................... 67

ABLE

39: DC D

IGITAL

NPUT

AND

UTPUT

LECTRICAL

HARACTERISTICS

........................................ 67

ABLE

40: XRT83L34 P

OWER

ONSUMPTION

.................................................................................... 67

ABLE

41: E1 R

ECEIVER

LECTRICAL

HARACTERISTICS

..................................................................... 68

ABLE

42: T1 R

ECEIVER

LECTRICAL

HARACTERISTICS

..................................................................... 69

ABLE

43: E1 T

RANSMIT

ETURN

OSS

EQUIREMENT

........................................................................ 69

ABLE

44: E1 T

RANSMITTER

LECTRICAL

HARACTERISTICS

............................................................... 70

ABLE

45: T1 T

RANSMITTER

LECTRICAL

HARACTERISTICS

............................................................... 70

Figure 26. ITU G.703 Pulse Template ............................................................................................. 71
T

ABLE

46: T

RANSMIT

ULSE

ASK

PECIFICATION

.............................................................................. 71

Figure 27. DSX-1 Pulse Template (normalized amplitude) ........................................................... 72
T

ABLE

47: DSX1 I

NTERFACE

SOLATED

PULSE

MASK

AND

CORNER

POINTS

........................................... 72

ABLE

48: AC E

LECTRICAL

HARACTERISTICS

.................................................................................... 73

Figure 28. Transmit Clock and Input Data Timing ........................................................................ 73

ICROPROCESSOR

NTERFACE

I/O T

IMING

.................................................................................................. 74

Intel Interface Timing - Asynchronous ....................................................................................................... 74

Figure 29. Receive Clock and Output Data Timing ....................................................................... 74
Figure 30. Intel Asynchronous Programmed I/O Interface Timing .............................................. 74
T

ABLE

49: A

SYNCHRONOUS

ODE

1 - I

NTEL

8051

AND

80188 I

NTERFACE

IMING

............................... 75

Motorola Asychronous Interface Timing .................................................................................................... 76

Figure 31. Motorola 68K Asynchronous Programmed I/O Interface Timing .............................. 76
T

ABLE

50: A

SYNCHRONOUS

- M

OTOROLA

68K - I

NTERFACE

IMING

PECIFICATION

............................. 76

Figure 32. Microprocessor Interface Timing - Reset Pulse Width ............................................... 76

ORDERING INFORMATION ............................................................................................. 77

ACKAGE

IMENSIONS

- 14

, 128

PACKAGE

................................................................................ 77

EVISIONS

................................................................................................................................................. 78

OTES

: ......................................................................................................................................... 79

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

PIN DESCRIPTION BY FUNCTION

RECEIVE SECTIONS

IGNAL

AME

YPE

ESCRIPTION

RLOS_0

RLOS_1

RLOS_2

RLOS_3

Receiver Loss of Signal for Channel _0

This output signal goes `High' for at least one RCLK_0 cycle to indicate loss
of signal at the receive 0 input. RLOS will remain "High" for the entire dura-
tion of the loss of signal detected by the receiver logic.

See "Receiver Loss of Signal (RLOS)" on page 20.

Receiver Loss of Signal for Channel _1

Receiver Loss of Signal for Channel _2

Receiver Loss of Signal for Channel _3

RCLK_0

RCLK_1

RCLK_2

RCLK_3

Receiver Clock Output for Channel _0

Receiver Clock Output for Channel _1

Receiver Clock Output for Channel _2

Receiver Clock Output for Channel _3

RNEG_0

LCV_0

RNEG_1

LCV_1

RNEG_1

LCV_2

RNEG_1

LCV_3

Receiver Negative Data Output for Channel _0 - Dual-Rail mode

This signal is the receiver negative-rail output data.

Line Code Violation Output for Channel _0 - Single-Rail mode

This signal goes `High' for one RCLK_0 cycle to indicate a code violation is
detected in the received data of Channel _0. If AMI coding is selected, every
bipolar violation received will cause this pin to go "High".

Receiver Negative Data Output for Channel _1

Line Code Violation Output for Channel _1

Receiver Negative Data Output for Channel _2

Line Code Violation Output for Channel _2

Receiver Negative Data Output for Channel _3

Line Code Violation Output for Channel _3

RPOS_0

RDATA_0

RPOS_1

RDATA_1

RPOS_2

RDATA_2

RPOS_3

RDATA_3

Receiver Positive Data Output for Channel _0 - Dual-Rail mode

This signal is the receive positive-rail output data sent to the Framer.

Receiver NRZ Data Output for Channel _0 - Single-Rail mode

This signal is the receive output data.

Receiver Positive Data Output for Channel _1

Receiver NRZ Data Output for Channel _1

Receiver Positive Data Output for Channel _2

Receiver NRZ Data Output for Channel _2

Receiver Positive Data Output for Channel _3

Receiver NRZ Data Output for Channel _3

RTIP_0

RTIP_1

RTIP_2

RTIP_3

Receiver Differential Tip Positive Input for Channel _0

Positive differential receive input from the line.

Receiver Differential Tip Positive Input for Channel _1

Receiver Differential Tip Positive Input for Channel _2

Receiver Differential Tip Positive Input for Channel _3

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

RRING_0

RRING_1

RRING_2

RRING_3

Receiver Differential Ring Negative Input for Channel _0

Negative differential receive input from the line.

Receiver Differential Ring Negative Input for Channel _1

Receiver Differential Ring Negative Input for Channel _2

Receiver Differential Ring Negative Input for Channel _3

RXMUTE

RDY_DTACK

Receive Muting - Hardware mode

Connecting this pin `High' will mute (force to ground) the outputs RPOS_n/
RNEG_n when a LOS condition occurs, to prevent data chattering. This pin
is internally pulled "low" consequently muting is normally disabled.

OTES

Internally pulled "Low" with 50k

resistor.

In Hardware mode, all receive channels share the same RXMUTE
control function.

Ready Output (Data Transfer Acknowledge Output) - Host mode

See "Ready Output (Data Transfer Acknowledge Output) - Host Mode" on
page 9.

RXRES0

RXRES1

108

109

Receive External Resistor Control Pins - Hardware mode

Receive External Resistor Control Pin 0

Receive External Resistor Control Pin 1

These pins are used to determine the value of the external Receive fixed
resistor according to the following table:

OTE

: These pins are internally pulled "Low" with 50k

resistor.

RCLKE

PTS1

106

Receive Clock Edge - Hardware Mode

Set this pin "High" to sample RPOS_N/RNEG_n on the falling edge of
RCLK_n. With this pin tied "Low", output data are updated on the rising edge
of RCLK_n.

Microprocessor Type Select Input pin 1 - Host mode

This pin along with µPTS2 (pin 107) is used to select the microprocessor
type.

See "Microprocessor Type Select Input Pins - Host Mode:" on page 10.

OTE

: This pin is internally pulled "Low" with a 50k

resistor.

IGNAL

AME

YPE

ESCRIPTION

R equired Fixed External

RX Resistor

No External Fixed R esistor

240

210

150

RXRES0

RXRES 1

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

TRANSMITTER SECTIONS

IGNAL

AME

YPE

ESCRIPTION

TCLKE

PTS2

107

Transmit Clock Edge - Hardware Mode

With this pin set to a "High", transmit input data of all channels are sampled at
the rising edge of TCLK_n. With this pin tied "Low", input data are sampled at
the falling edge of TCLK_n.

Microprocessor Type Select Input pin 2 - Host Mode

This pin along with

PTS1 (pin 106) selects the microprocessor type.

See

"Microprocessor Type Select Input Pins - Host Mode:" on page 10.

OTE

: This pin is internally pulled "Low" with a 50k

resistor.

TTIP_0

TTIP_1

TTIP_2

TTIP_3

Transmitter Tip Output for Channel _0

Positive differential transmit output to the line.

Transmitter Tip Output for Channel _1

Transmitter Tip Output for Channel _2

Transmitter Tip Output for Channel _3

TRING_0

TRING_1

TRING_2

TRING_3

Transmitter Ring Output for Channel _0

Negative differential transmit output to the line.

Transmitter Ring Output for Channel _1

Transmitter Ring Output for Channel _2

Transmitter Ring Output for Channel _3

TPOS_0

TDATA_0

TPOS_1

TDATA_1

TPOS_2

TDATA_2

TPOS_3

TDATA_3

127

104

101

Transmitter Positive Data Input for Channel _0 - Dual-rail mode

This signal is the positive-rail input data for transmitter 0.

Transmitter 0 Data Input - Single-Rail mode

This pin is used as the NRZ input data for transmitter 0.

Transmitter Positive Data Input for Channel _1

Transmitter 1 Data Input

Transmitter Positive Data Input for Channel _2

Transmitter 2 Data Input

Transmitter Positive Data Input for Channel _3

Transmitter 3 Data Input

OTE

: Internally pulled "Low" with a 50k

resistor for each channels.

TNEG_0

CODES_0

TNEG_1

CODES_1

TNEG_2

CODES_2

TNEG_3

CODES_3

126

105

100

Transmitter Negative NRZ Data Input for Channel _0

Dual-Rail mode

This signal is the negative-rail input data for transmitter 0.

Single-Rail mode

This pin can be left unconnected.

Coding Select for Channel _0 - Hardware mode and Single-Rail mode

Connecting this pin "Low" enables HDB3 in E1 or B8ZS in T1 encoding and
decoding for Channel _0. Connecting this pin "High" selects AMI data format.

Transmitter Negative NRZ Data Input for Channel _1

Coding Select for Channel _1

Transmitter Negative NRZ Data Input for Channel _2

Coding Select for Channel _2

Transmitter Negative NRZ Data Input for Channel _3

Coding Select for Channel _3

OTE

: Internally pulled "Low" with a 50k

resistor for channel _n

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

TCLK_0

TCLK_1

TCLK_2

TCLK_3

128

103

102

Transmitter Clock Input for Channel _0 - Host mode and Hardware mode

E1 rate at 2.048MHz ± 50ppm. T1 rate at 1.544MHz ± 32ppm.

During normal operation TCLK_0 is used for sampling input data at TPOS_0/
TDATA_0 and TNEG_0/CODES_0 while MCLK is used as the timing refer-
ence for the transmit pulse shaping circuit.

Transmitter Clock Input for Channel _1

Transmitter Clock Input for Channel _2

Transmitter Clock Input for Channel _3

OTE

: Internally pulled "Low" with a 50k

resistor for all channels.

TAOS_0

TAOS_1

TAOS_2

TAOS_3

WR_R/W

RD_DS

ALE_AS

Transmit All Ones for Channel _0 - Hardware mode

Setting this pin "High" enables the transmission of an "All Ones" Pattern from
Channel _0. A "Low" level stops the transmission of the "All Ones" Pattern.

Transmit All Ones for Channel _1

Transmit All Ones for Channel _2

Transmit All Ones for Channel _3

Host mode: these pins act as various microprocessor functions.

See "Micro-

processor Interface" on page 9.

OTE

: These pins are internally pulled "Low" with a 50k

resistor.

TXON_0

TXON_1

TXON_2

TXON_3

122

123

124

125

Transmitter Turn On for Channel _0

Hardware mode

Setting this pin "High" turns on the Transmit Section of Channel _0 and has no
control of the Channel_0 receiver. When TXON_0 = "0" then TTIP_0 and
TRING_0 driver outputs will be tri-stated.

OTE

: In Hardware mode only, all receiver channels will be turned on upon

power-up and there is no provision to power them off. The receive
channels can only be independently powered on or off in Host mode.

In Host mode

The TXON_n bits in the channel control registers turn each channel Transmit
section ON or OFF. However, control of the on/off function can be transferred
to the Hardware pins by setting the TXONCTL bit (bit 6) to "1" in the register at
address hex 0x42.

Transmitter Turn On for Channel _1

Transmitter Turn On for Channel _2

Transmitter Turn On for Channel _3

OTE

: Internally pulled "Low" with a 50k

resistor for all channels.

IGNAL

AME

YPE

ESCRIPTION

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

MICROPROCESSOR INTERFACE

IGNAL

AME

YPE

ESCRIPTION

HW_HOST

Mode Control Input

This pin selects Hardware or Host mode. Leave this pin unconnected or tie
"High" to select Hardware mode.

For Host mode, this pin must be tied "Low".

OTE

: Internally pulled "High" with a 50k

resistor.

WR_R/W

TAOS_0

Write Input (Read/Write) - Host mode

Intel bus timing: A "Low" pulse on WR selects a write operation when CS
pin is "Low".

Motorola bus timing: A "High" pulse on R/W selects a read operation and a
"Low" pulse on R/W selects a write operation when CS is "Low".

Transmit All "Ones" Channel_0 - Hardware Mode

See "Transmit All Ones for Channel _0 - Hardware mode" on page 8.

OTE

: Internally pulled "Low" with a 50k

resistor.

RD_DS

TAOS_1

Read Input (Data Strobe) - Host Mode

Intel bus timing: A "Low" pulse on RD selects a read operation when the CS
pin is "Low".

Motorola bus timing: A "Low" pulse on DS indicates a read or write opera-
tion when the CS pin is "Low".

Transmit All "Ones" Channel_1 - Hardware Mode

See "Transmit All Ones for Channel _0 - Hardware mode" on page 8.

OTE

: Internally pulled "Low" with a 50k

resistor.

ALE_AS

TAOS_2

Address Latch Input (Address Strobe) - Host Mode

Intel bus timing: The address inputs are latched into the internal register on
the falling edge of ALE.

Motorola bus timing: The address inputs are latched into the internal regis-
ter on the falling edge of AS.

Transmit All "Ones" Channel_2 - Hardware Mode

See "Transmit All Ones for Channel _0 - Hardware mode" on page 8.

OTE

: Internally pulled "Low" with a 50k

resistor.

TAOS_3

Chip Select Input - Host Mode

This signal must be "Low" in order to access the parallel port.

Transmit All "Ones" Channel_3 - Hardware Mode

See "Transmit All Ones for Channel _0 - Hardware mode" on page 8.

OTE

: Internally pulled "Low" with a 50k

resistor.

RDY_DTACK

RXMUTE

Ready Output (Data Transfer Acknowledge Output) - Host Mode

Intel bus timing: RDY is asserted "High" to indicate the device has com-
pleted a read or write operation.

Motorola bus timing: DTACK is asserted "Low" to indicate the device has
completed a read or write cycle.

Receive Muting - Hardware mode

See "Receive Muting - Hardware mode" on page 6.

OTE

: Internally pulled "Low" with a 50k

resistor.

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

PTS1

PTS2

RCLKE

TCLKE

106

107

106

107

Microprocessor Type Select Input Pins - Host Mode:

Microprocessor Type Select Input Bit 1

Microprocessor Type Select Input Bit 2

Receive Clock Edge select - Hardware mode

See "Receive Clock Edge - Hardware Mode" on page 6.

Transmit Clock Edge select - Hardware mode

See "Transmit Clock Edge - Hardware Mode" on page 7.

OTE

: These pins are internally pulled "Low" with a 50k

resistor.

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]/

D[1]/

D[0]/

LOOP1_0

LOOP0_0

LOOP1_1

LOOP0_1

LOOP1_2

LOOP0_2

LOOP1_3

LOOP0_3

I/O

Microprocessor Read/Write Data Bus Pins - Host Mode

Data Bus[7]

Data Bus[6]

Data Bus[5]

Data Bus[4]

Data Bus[3]

Data Bus[2]

Data Bus[1]

Data Bus[0]

Loop-back Control pin, Bits [1:0]_Channel_n - Hardware Mode

Pins 42 - 49 control which Loop-Back mode is selected per channel.

See

"Loop-Back Control Pins - Hardware Mode:" on page 15.

OTE

: Internally pulled "Low" with a 50k

resistor.

PCLK

ATAOS

Microprocessor Clock Input - Host Mode

Input clock for synchronous microprocessor operation. Maximum clock rate
is 54 MHz.

OTE

: This pin is internally pulled "Low" for asynchronous microprocessor

interface when no clock is present.

Automatic Transmit "All Ones" - Hardware mode

This pin functions as an Automatic Transmit "All Ones".

See "Automatic

Transmit "All Ones" Pattern - Hardware Mode" on page 14.

IGNAL

AME

YPE

ESCRIPTION

P T S 2

P T S 1

P T y p e

6 8 H C 1 1 , 8 0 5 1 , 8 0 C 1 8 8 (a syn c.)

M o to ro la 6 8 K (a syn c.)

In te l x8 6 (syn c.)

M o to ro la 8 6 0 (syn c.)

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

A[0]

JASEL1

JASEL0

EQC4

EQC3

EQC2

EQC1

EQC0

Microprocessor Address Pins - Host mode:

Microprocessor Interface Address Bus[6]

Microprocessor Interface Address Bus[5]

Microprocessor Interface Address Bus[4]

Microprocessor Interface Address Bus[3]

Microprocessor Interface Address Bus[2]

Microprocessor Interface Address Bus[1]

Microprocessor Interface Address Bus[0]

Jitter Attenuator Select Pins - Hardware Mode

Jitter Attenuator select pin 1

Jitter Attenuatore select pin 0

See "Jitter Attenuator" on page 12.

Equalizer Control Pins - Hardware Mode

Equalizer Control Input pin 4

Equalizer Control Input pin 3

Equalizer Control Input pin 2

Equalizer Control Input pin 1

Equalizer Control Input pin 0

Pins EQC[4:0] select the Receive Equalizer and Transmitter Line Build Out.

See "Alarm Function//Redundancy Support" on page 14.

OTE

: Internally pulled "Low" with a 50k

resistor.

INT

TRATIO

119

Interrupt Output - Host Mode

This pin goes "Low" to indicate an alarm condition has occurred within the
device. Interrupt generation can be globally disabled by setting the GIE bit to
"0" in the command control register.

Transmitter Transformer Ratio Select - Hardware mode

The function of this pin is to select the transmitter transformer ratio.

See

"Alarm Function//Redundancy Support" on page 14.

OTE

: This pin is an open drain output and requires an external 10k

pull-

up resistor.

IGNAL

AME

YPE

ESCRIPTION

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

CLOCK SYNTHESIZER

IGNAL

AME

YPE

ESCRIPTION

MCLKE1

E1 Master Clock Input

A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty
cycle of 40% to 60% can be provided at this pin.

In systems that have only one master clock source available (E1 or T1), that
clock should be connected to both MCLKE1 and MCLKT1 inputs for proper
operation.

OTES

All channels of the XRT83L34 must be operated at the same clock
rate, either T1, E1 or J1.

Internally pulled "Low" with a 50k

resistor.

CLKSEL0

CLKSEL1

CLKSEL2

Clock Select inputs for Master Clock Synthesizer - Hardware mode

CLKSEL[2:0] are input signals to a programmable frequency synthesizer that
can be used to generate a master clock from an accurate external clock
source according to the following table.

The MCLKRATE control signal is generated from the state of EQC[4:0]
inputs. See Table 4 for description of Transmit Equalizer Control bits.

Host Mode: The state of these pins are ignored and the master frequency
PLL is controlled by the corresponding interface bits. See

Table 35

, register

address 1000001.

OTE

: These pins are internally pulled "Low" with a 50k

resistor.

2048

1544

MCLKE1

(kHz)

128

256

128

2048

1544

MCLKT1

(kHz)

1544

2048

1544

2048

CLKOUT

(KHz)

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

CLKSEL0

CLKSEL1

CLKSEL2

1544

2048

1544

MCLKRATE

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

ALARM FUNCTION//REDUNDANCY SUPPORT

MCLKT1

T1 Master Clock Input

This signal is an independent 1.544MHz clock for T1 systems with required
accuracy of better than ±50ppm and duty cycle of 40% to 60%. MCLKT1
input is used in the T1 mode.

OTES

All channels of the XRT83L34 must be operated at the same clock
rate, either T1, E1 or J1.

See pin 32 description for further explanation for the usage of this
pin.

Internally pulled "Low" with a 50k

resistor.

MCLKOUT

Synthesized Master Clock Output

This signal is the output of the Master Clock Synthesizer PLL which is at T1
or E1 rate based upon the mode of operation.

IGNAL

AME

YPE

ESCRIPTION

GAUGE

Twisted Pair Cable Wire Gauge Select - Hardware mode

Connect this pin "High" to select 26 Gauge wire. Connect this pin "Low" to
select 22 and 24 gauge wire for all channels.

OTE

: Internally pulled "Low" with a 50k

resistor.

DMO_0

DMO_1

DMO_2

DMO_3

Driver Failure Monitor Channel _0

This pin transitions "High" if a short circuit condition is detected in the trans-
mit driver of Channel _0, or no transmit output pulse is detected for more
than 128 TCLK_0 cycles.

Driver Failure Monitor Channel _1

Driver Failure Monitor Channel _2

Driver Failure Monitor Channel _3

ATAOS

PCLK

Automatic Transmit "All Ones" Pattern - Hardware Mode

A "High" level on this pin enables the automatic transmission of an "All Ones"
AMI pattern from the transmitter of any channel that the receiver of that
channel has detected an LOS condition. A "Low" level on this pin disables
this function.

OTE

: All channels share the same ATAOS input control function.

Microprocessor Clock Input - Host Mode

See "Microprocessor Clock Input - Host Mode" on page 10.

OTE

: This pin is internally pulled "Low" for asynchronous microprocessor

interface when no clock is present.

IGNAL

AME

YPE

ESCRIPTION

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

TRATIO

INT

119

Transmitter Transformer Ratio Select - Hardware Mode

In external termination mode (TXSEL = 0), setting this pin "High" selects a
transformer ratio of 1:2 for the transmitter. A "Low" on this pin sets the trans-
mitter transformer ratio to 1:2.45. In the internal termination mode the
transmitter transformer ratio is permanently set to 1:2 and the state of this pin
is ignored.

Interrupt Output - Host Mode

This pin is asserted "Low" to indicate an alarm condition.

See "Microproces-

sor Interface" on page 9.

OTE

: This pin is an open drain output and requires an external 10k

pull-

up resistor.

RESET

121

Hardware Reset (Active "Low")

When this pin is tied "Low" for more than 10µs, the device is put in the reset
state.

Pulling RESET and ICT pins "Low" simultaneously will put the chip in factory
test mode. This condition should not be permitted during normal operation.

OTE

: Internally pulled "High" with a 50k

resistor.

SR/DR

Single-Rail/Dual-Rail Data Format

Connect this pin "Low" to select transmit and receive data format in Dual-rail
mode. In this mode, HDB3 or B8ZS encoder and decoder are not available.

Connect this pin "High" to select single-rail data format.

OTE

: Internally pulled "Low" with a 50k

resistor.

LOOP1_0

LOOP0_0

LOOP1_1

LOOP0_1

LOOP1_2

LOOP0_2

LOOP1_3

LOOP0_3

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

I/O

Loop-Back Control Pins - Hardware Mode:

Loop-back control pin 1 - Channel _0

Loop-back control pin 0 - Channel _0

Loop-back control pin 1 - Channel _1

Loop-back control pin 0 - Channel _1

Loop-back control pin 1 - Channel _2

Loop-back control pin 0 - Channel _2

Loop-back control pin 1 - Channel _3

Loop-back control pin 0 - Channel _3

Microprocessor R/W Data bits [7:0] - Host Mode

These pins are microprocessor data bus pins.

See "Microprocessor Read/

Write Data Bus Pins - Host Mode" on page 10.

OTE

: These pins are internally pulled "Low" with a 50k

resistor.

IGNAL

AME

YPE

ESCRIPTION

LOOP1_n

LOOP0_n

MODE

Normal Mode No Loop-back Channel_n

Local Loop-Back Channel_n

Remote Loop-Back Channel_n

Digital Loop-Back Channel_n

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

EQC4

EQC3

EQC2

EQC1

EQC0

A[4]

A[3]

A[2]

A[1]

A[0]

Equalizer Control Input 4 - Hardware Mode

This pin together with EQC[3:0] are used for controlling the transmit pulse
shaping, transmit line build-out (LBO), receive monitoring and also to select
T1, E1 or J1 Modes of operation. See Table 4 for description of Transmit
Equalizer Control bits.

Equalizer Control Input 3

Equalizer Control Input 2

Equalizer Control Input 1

Equalizer Control Input 0

OTES

In Hardware mode all transmit channels share the same pulse
setting controls function.

All channels of an XRT83L34 must operate at the same clock rate,
either the T1, E1 or J1 modes.

Microprocessor Address bits [4:0] - Host Mode

See "Microprocessor Address Pins - Host mode:" on page 11.

OTE

: Internally pulled "Low" with a 50k

resistor for all channels.

RXTSEL

110

Receiver Termination Select

In Hardware mode, when this pin is "Low" the receive line termination is
determined only by the external resistor. When "High", the receive termina-
tion is realized by internal resistors or the combination of internal and exter-
nal resistors. These conditions are described in the table below.

OTE

: In Hardware mode all channels share the same RXTSEL control

function.

In Host mode, the RXTSEL_n bits in the channel control registers deter-
mines if the receiver termination is external or internal. However the function
of RXTSEL can be transferred to the Hardware pin by setting the TERCNTL
bit (bit 4) to "1" in the register 66 address hex 0x42.

OTE

: Internally pulled "Low" with a 50k

resistor.

TXTSEL

111

Transmit Termination Select - Hardware Mode

When this pin is "Low" the transmit line termination is determined only by an
external resistor. When "High", the transmit termination is realized only by
the internal resistor.

OTES

This pin is internally pulled "Low" with a 50k

resistor.

In Hardware Mode all channels share the same TXTSEL control
function.

IGNAL

AME

YPE

ESCRIPTION

RXTSEL

RX Termination

External

Internal

TXTSEL

TX Termination

External

Internal

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

POWER AND GROUND

IGNAL

AME

YPE

ESCRIPTION

TGND_0

TGND_1

TGND_2

TGND_3

****

Transmitter Analog Ground for Channel _0

Transmitter Analog Ground for Channel _1

Transmitter Analog Ground for Channel _2

Transmitter Analog Ground for Channel _3

TVDD_0

TVDD_1

TVDD_2

TVDD_3

****

Transmitter Analog Positive Supply (3.3V + 5%) for Channel _0

Transmitter Analog Positive Supply (3.3V + 5%) for Channel _1

Transmitter Analog Positive Supply (3.3V + 5%) for Channel _2

Transmitter Analog Positive Supply (3.3V + 5%) for Channel _3

RVDD_0

RVDD_1

RVDD_2

RVDD_3

****

Receiver Analog Positive Supply (3.3V± 5%) for Channel _0

Receiver Analog Positive Supply (3.3V± 5%) for Channel _1

Receiver Analog Positive Supply (3.3V± 5%) for Channel _2

Receiver Analog Positive Supply (3.3V± 5%) for Channel _3

RGND_0

RGND_1

RGND_2

RGND_3

****

Receiver Analog Ground for Channel _0

Receiver Analog Ground for Channel _1

Receiver Analog Ground for Channel _2

Receiver Analog Ground for Channel _3

VDDPLL_1

VDDPLL_2

AVDD

****

Analog Positive Supply for Master Clock Synthesizer PLL (3.3V± 5%)

Analog Positive Supply (3.3V± 5%)

GNDPLL_1

GNDPLL_2

AGND

****

Analog Ground for Master Clock Synthesizer PLL

Analog Ground

DVDD

115

116

****

Digital Positive Supply (3.3V± 5%)

DGND

GND

DGND

114

117

118

****

Digital Ground

Ground

Digital Ground

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

FUNCTIONAL DESCRIPTION

The XRT83L34 is a fully integrated four-channel long-haul and short-haul transceiver intended for T1, J1 or E1
systems. Simplified block diagrams of the device are shown in

Figure 1

, Host mode and

Figure 2

, Hardware

mode. The XRT83L34 can receive signals that have been attenuated from 0 to 36dB at 772kHz (0 to 6000 feet
cable loss) for T1 and from 0 to 43dB at 1024kHz for E1 systems.

In T1 applications, the XRT83L34 can generate five transmit pulse shapes to meet the short-haul Digital Cross-
connect (DSX-1) template requirement as well as four CSU Line Build-Out (LBO) filters of 0dB, -7.5dB, -15dB
and -22.5dB as required by FCC rules. It also provides programmable transmit output pulse generators for
each channel that can be used for output pulse shaping allowing performance improvement over a wide variety
of conditions. The operation and configuration of the XRT83L34 can be controlled through a parallel
microprocessor Host interface or, by Hardware control.

MASTER CLOCK GENERATOR

Using a variety of external clock sources, the on-chip frequency synthesizer generates the T1 (1.544MHz) or
E1 (2.048MHz) master clocks necessary for the transmit pulse shaping and receive clock recovery circuit.

There are two master clock inputs MCLKE1 and MCLKT1. In systems where both T1 and E1 master clocks are
available these clocks can be connected to the respective pins. All channels of a given XRT83L34 must be
operated at the same clock rate, either T1, E1 or J1 modes.

In systems that have only one master clock source available (E1 or T1), that clock should be connected to both
MCLKE1 and MCLKT1 inputs for proper operation. T1 or E1 master clocks can be generated from 8kHz,
16kHz, 56kHz, 64kHz, 128kHz and 256kHz external clocks under the control of CLKSEL[2:0] inputs according
to

Table 1

OTE

: EQC[4:0] determine the T1/E1 operating mode. See

Table 5

for details.

IGURE

4. T

NPUT

LOCK

OURCE

IGURE

5. O

NPUT

LOCK

OURCE

MCLKE1

MCLKT1

MCLKOUT

1.544MHz
or
2.048MHz

2.048MHz

+/-50ppm

1.544MHz

+/-50ppm

Two Input C lock Sources

MCLKE1

MCLKT1

MCLK OUT

1.544MHz
or
2.048MHz

One Input Clock Source

Input Clock Options

8kHz

16kHz
56kHz
64kHz

128kHz
256kHz

1.544MHz
2.048MHz

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

In Host mode the programming is achieved through the corresponding interface control bits, the state of the
CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit.

RECEIVER

RECEIVER INPUT

At the receiver input, a cable attenuated AMI signal can be coupled to the receiver through a capacitor or a 1:1
transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum
equalizer gain is up to 36dB for T1 and 43dB for E1 modes. The equalized signal is subsequently applied to a
peak detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1
and T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital
representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data
subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before
being applied to the RPOS_n/RDATA_n and RNEG_n/LCV_n pins. Clock recovery is accomplished by a digital
phase-locked loop (DPLL) which does not require any external components and can tolerate high levels of
input jitter that meets or exceeds the ITU-G.823 and TR-TSY000499 standards.

In Hardware mode only, all receive channels are turned on upon power-up and are always on. In Host mode,
ach receiver channel can be individually turned on or off with the respective channel RXON_n bit.

See

"Microprocessor Register #0, Bit Description" on page 46.

ABLE

1: M

ASTER

LOCK

ENERATOR

MCLKE1

MCLKT1

CLKSEL2

CLKSEL1

CLKSEL0

MCLKRATE

ASTER

LOCK

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

128

2048

128

1544

256

2048

256

1544

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

RECEIVE MONITOR MODE

In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles
input signals attenuated resistively up to 29dB, along with 0 to 6dB cable attenuation for both T1 and E1
applications, refer to

Table 5

for details. This feature is available in both Hardware and Host modes.

RECEIVER LOSS OF SIGNAL (RLOS)

For compatibility with ITU G.775 requirements, the RLOS monitoring function is implemented using both
analog and digital detection schemes. If the analog RLOS condition occurs, a digital detector is activated to
count for 32 consecutive zeros in E1 (4096 bits in Extended Los mode, EXLOS = "1") or 175 consecutive zeros
in T1 before RLOS is asserted. RLOS is cleared when the input signal rises +3dB (built in hysteresis) above
the point at which it was declared and meets 12.5% ones density of 4 ones in a 32 bit window, with no more
than 16 consecutive zeros for E1. In T1 mode, RLOS is cleared when the input signal rises +3dB (built in
hysteresis) above the point at which it was declared and contains 16 ones in a 128 bit window with no more
than 100 consecutive zeros in the data stream. When loss of signal occurs, RLOS register indication and
register status will change. If the RLOS register enable is set high (enabled), the alarm will trigger an interrupt
causing the interrupt pin (INT) to go low. Once the alarm status register has been read, it will automatically
reset upon read (RUR), and the INT pin will return high.

Analog RLOS

Setting the Receiver Inputs to -15dB T1/E1 Short Haul Mode

By setting the receiver inputs to -15dB T1/E1 short haul mode, the equalizer will detect the incoming amplitude
and make adjustments by adding gain up to a maximum of +15dB normalizing the T1/E1 input signal.

OTE

: This is the only setting that refers to cable loss (frequency), not flat loss (resistive).

Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+15dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
typically -24dB (-15dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total cable attenuation of -21dB. See

Figure 6

for a simplified

diagram.

Setting the Receiver Inputs to -29dB T1/E1 Gain Mode

By setting the receiver inputs to -29dB T1/E1 gain mode, the equalizer will detect the incoming amplitude and
make adjustments by adding gain up to a maximum of +29dB normalizing the T1/E1 input signal.

OTE

: This is the only setting that refers to flat loss (resistive). All other modes refer to cable loss (frequency).

Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is

IGURE

6. S

IMPLIFIED

IAGRAM

-15dB T1/E1 S

HORT

AUL

ODE

AND

RLOS C

ONDITION

Norm alized up to +15dB Max

Declare LOS

Clear LOS

-9dB

+3dB

Clear LOS

Declare LOS

+3dB

-9dB

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total flat loss of -35dB. See

Figure 7

for a simplified diagram.

Setting the Receiver Inputs to -36dB T1/E1 Long Haul Mode

By setting the receiver inputs to -36dB T1/E1 long haul mode, the equalizer will detect the incoming amplitude
and make adjustments by adding gain up to a maximum of +36dB normalizing the T1 input signal. This setting
refers to cable loss (frequency), not flat loss (resistive). Once the T1/E1 input signal has been normalized to
0dB by adding the maximum gain (+36dB), the receiver will declare RLOS if the signal is attenuated by an
additional -9dB. The total cable loss at RLOS declaration is typically -45dB (-36dB + -9dB). A 3dB hysteresis
was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a
total cable attenuation of -42dB. See

Figure 8

for a simplified diagram.

E1 Extended RLOS

E1: Setting the Receiver Inputs to Extended RLOS

By setting the receiver inputs to extended RLOS, the equalizer will detect the incoming amplitude and make
adjustments by adding gain up to a maximum of +43dB normalizing the E1 input signal. This setting refers to
cable loss (frequency), not flat loss (resistive). Once the E1 input signal has been normalized to 0dB by adding
the maximum gain (+43dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB.

IGURE

7. S

IMPLIFIED

IAGRAM

-29dB T1/E1 G

AIN

ODE

AND

RLOS C

ONDITION

IGURE

8. S

IMPLIFIED

IAGRAM

-36dB T1/E1 L

ONG

AUL

ODE

AND

RLOS C

ONDITION

Norm alized up to +29dB Max

Declare LOS

Clear LOS

-9dB

+3dB

Clear LOS

Declare LOS

+3dB

-9dB

Norm alized up to +36dB Max

Declare LOS

Clear LOS

-9dB

+3dB

Clear LOS

Declare LOS

+3dB

-9dB

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

The total cable loss at RLOS declaration is typically -52dB (-43dB + -9dB). A 3dB hysteresis was designed so
that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable
attenuation of -49dB. See

Figure 9

for a simplified diagram.

RECEIVE HDB3/B8ZS DECODER

The Decoder function is available in both Hardware and Host modes on a per channel basis by controlling the
TNEG_n/CODES_n pin or the CODES_n interface bit. The decoder function is only active in single-rail Mode.
When selected, receive data in this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1
systems. Bipolar violations that do not conform to the coding scheme will be reported as Line Code Violation at
the RNEG_n/LCV_n pin of each channel. The length of the LCV pulse is one RCLK cycle for each code
violation. In E1mode only, an excessive number of zeros in the receive data stream is also reported as an error
at the same output pin. If AMI decoding is selected in single rail mode, every bipolar violation in the receive
data stream will be reported as an error at the RNEG_n/LCV_n pin.

RECOVERED CLOCK (RCLK) SAMPLING EDGE

This feature is available in both Hardware and Host modes on a global basis. In Host mode, the sampling
edge of RCLK output can be changed through the interface control bit RCLKE. If a "1" is written in the RCLKE
interface bit, receive data output at RPOS_n/RDATA_n and RNEG_n/LCV_n are updated on the falling edge of
RCLK for all eight channels. Writing a "0" to the RCLKE register, updates the receive data on the rising edge of
RCLK. In Hardware mode the same feature is available under the control of the RCLKE pin.

IGURE

9. S

IMPLIFIED

IAGRAM

XTENDED

RLOS

MODE

(E1 O

NLY

)

IGURE

10. R

ECEIVE

LOCK

AND

UTPUT

ATA

IMING

Norm alized up to +45dB Max

Declare LOS

Clear LOS

-9dB

+3dB

Clear LOS

Declare LOS

+3dB

-9dB

RCLK

RPOS

RNEG

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

JITTER ATTENUATOR

To reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive
signal path. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth that can vary
between 2x32 and 2x64. The jitter attenuator can also be placed in the transmit signal path or disabled
altogether depending upon system requirements. The jitter attenuator, other than using the master clock as
reference, requires no external components. With the jitter attenuator selected, the typical throughput delay
from input to output is 16 bits for 32 bit FIFO size or 32 bits for 64 bit FIFO size. When the read and write
pointers of the FIFO in the jitter attenuator are within two bits of over-flowing or under-flowing, the bandwidth of
the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this
situation occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer's position is outside
the two bits window. Under normal condition, the jitter transfer characteristic meets the narrow bandwidth
requirement as specified in ITU- G.736, ITU- I.431 and AT&T Pub 62411 standards.

In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz. In E1 mode, the bandwidth can be reduced
through the JABW control signal. When JABW is set "High" the bandwidth of the jitter attenuator is reduced
from 10Hz to 1.5Hz. Under this condition the FIFO length is automatically set to 64 bits and the 32 bits FIFO
length will not be available in this mode. Jitter attenuator controls are available on a per channel basis in the
Host mode and on a global basis in the Hardware mode.

GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH)

The XRT83L34 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are removed
which can leave gaps in the incoming data stream. If the jitter attenuator is enabled in the transmit path, the
32-Bit or 64-Bit FIFO is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap
width of the 8-Channel LIU is shown in Table 2.

OTE

: If the LIU is used in a loop timing system, the jitter attenuator should be enabled in the receive path.

ABLE

2: M

AXIMUM

IDTH

FOR

ULTIPLEXER

APPER

PPLICATIONS

FIFO D

EPTH

AXIMUM

IDTH

32-Bit

20 UI

64-Bit

50 UI

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

ARBITRARY PULSE GENERATOR FOR T1 AND E1

The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit
binary word by programming the appropriate channel register. This allows the system designer to set the
overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit is
set to "1", the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is set
to "0", the segment will move in a negative direction relative to a flat line condition. A pulse with numbered
segments is shown in Figure 11.

OTE

: By default, the arbitrary segments are programmed to 0x00h. The transmitter outputs will result in an all zero pattern

to the line.

TRANSMITTER

DIGITAL DATA FORMAT

Both the transmitter and receiver can be configured to operate in dual or single-rail data formats. This feature
is available under both Hardware and Host control modes, on a global basis. The dual or single-rail data
format is determined by the state of the SR/DR pin in Hardware mode or SR/DR interface bit in the Host
mode. In single-rail mode, transmit clock and NRZ data are applied to TCLK_n and TPOS_n/TDATA_n pins
respectively. In single-rail and Hardware mode the TNEG_n/CODES_n input can be used as the CODES
function. With TNEG_n/CODES_n tied "Low", HDB3 or B8ZS encoding and decoding are enabled for E1 and
T1 modes respectively. With TNEG_n/CODES_n tied "High", the AMI coding scheme is selected. In both dual
or single-rail modes of operations, the transmitter converts digital input data to a bipolar format before being
transmitted to the line.

TRANSMIT CLOCK (TCLK) SAMPLING EDGE

Serial transmit data at TPOS_n/TDATA_n and TNEG_n/CODES_n are clocked into the XRT83L34 under the
synchronization of TCLK_n. With a "0" written to the TCLKE interface bit, or by pulling the TCLKE pin "Low",
input data is sampled on the falling edge of TCLK_n. The sampling edge is inverted with a "1" written to TCLKE
interface bit, or by connecting the TCLKE pin "High".

IGURE

11. A

RBITRARY

ULSE

EGMENT

SSIGNMENT

Segment

0xn8

0xn9

0xna

0xnb

0xnc

0xnd

0xne

0xnf

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

TRANSMIT HDB3/B8ZS ENCODER

The Encoder function is available in both Hardware and Host modes on a per channel basis by controlling the
TNEG_n/CODES_n pin or CODES interface bit. The encoder is only available in single-rail mode. In E1 mode
and with HDB3 encoding selected, any sequence with four or more consecutive zeros in the input serial data
from TPOS_n/TDATA_n, will be removed and replaced with 000V or B00V, where "B" indicates a pulse
conforming with the bipolar rule and "V" representing a pulse violating the rule. An example of HDB3 Encoding
is shown in

Table 3

. In a T1 system, an input data sequence with eight or more consecutive zeros will be

removed and replaced using the B8ZS encoding rule. An example of Bipolar with 8 Zero Substitution (B8ZS)
encoding scheme is shown in

Table 4

. Writing a "

" into the CODES_n interface bit or connecting the TNEG_n/

CODES_n pin to a "High" level selects the AMI coding for both E1 or T1 systems.

IGURE

12. T

RANSMIT

LOCK

AND

NPUT

ATA

IMING

ABLE

3: E

XAMPLES

HDB3 E

NCODING

UMBER

PULSE

BEFORE

NEXT

ZEROS

EXT

BITS

Input

0000

HDB3 (case1)

odd

000V

HDB3 (case2)

even

B00V

ABLE

4: E

XAMPLES

B8ZS E

NCODING

ASE

RECEDING

ULSE

EXT

8 B

ITS

Input

00000000

B8ZS

000VB0VB

AMI Output

000+ -0- +

ASE

Input

00000000

B8ZS

000VB0VB

AMI Output

000- +0+ -

TCLK

TPOS/TDATA

TNEG

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

DRIVER FAILURE MONITOR (DMO)

The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING
outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the
transmit input. If the transmitter of a channel has no output for more than 128 clock cycles, the corresponding
DMO pin goes "High" and remains "High" until a valid transmit pulse is detected. In Host mode, the failure of
the transmit channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any
transition on the DMO interface bit will generate an interrupt. The driver failure monitor is supported in both
Hardware and Host modes on a per channel basis.

TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT

The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the
shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a
tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the
transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In Hardware mode, the
state of the A[4:0]/EQC[4:0] pins determine the transmit pulse shape for all eight channels. In Host mode
transmit pulse shape can be controlled on a per channel basis using the interface bits EQC[4:0]. The chip
supports five fixed transmit pulse settings for T1 Short-haul applications plus a fully programmable waveform
generator for arbitrary transmit output pulse shapes. Transmit Line Build-Outs for T1 long-haul application are
supported from 0dB to -22.5dB in three 7.5dB steps. The choice of the transmit pulse shape and LBO under
the control of the interface bits are summarized in

Table 5

. For CSU LBO transmit pulse design information,

refer to ANSI T1.403-1993 Network-to-Customer Installation specification, Annex-E.

OTE

: EQC[4:0] determine the T1/E1 operating mode of the XRT83L34. When EQC4 = "1" and EQC3 = "1", the XRT83L34

is in the E1 mode, otherwise it is in the T1/J1 mode.

ABLE

5: R

ECEIVE

QUALIZER

ONTROL

AND

RANSMIT

INE

UILD

-O

ETTINGS

EQC4 EQC3

EQC2

EQC1

EQC0

E1/T1 M

ODE

& R

ECEIVE

ENSITIVITY

RANSMIT

LBO

ABLE

ODING

T1 Long Haul/36dB

0dB

100

/ TP

B8ZS

T1 Long Haul/36dB

-7.5dB

100

/ TP

B8ZS

T1 Long Haul/36dB

-15dB

100

/ TP

B8ZS

T1 Long Haul/36dB

-22.5dB

100

/ TP

B8ZS

T1 Long Haul/45dB

0dB

100

/ TP

B8ZS

T1 Long Haul/45dB

-7.5dB

100

/ TP

B8ZS

T1 Long Haul/45dB

-15dB

100

/ TP

B8ZS

T1 Long Haul/45dB

-22.5dB

100

/ TP

B8ZS

T1 Short Haul/15dB

0-133 ft./ 0.6dB

100

/ TP

B8ZS

T1 Short Haul/15dB

133-266 ft./ 1.2dB

100

/ TP

B8ZS

T1 Short Haul/15dB

266-399 ft./ 1.8dB

100

/ TP

B8ZS

T1 Short Haul/15dB

399-533 ft./ 2.4dB

100

/ TP

B8ZS

T1 Short Haul/15dB

533-655 ft./ 3.0dB

100

/ TP

B8ZS

T1 Short Haul/15dB

Arbitrary Pulse

100

/ TP

B8ZS

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

TRANSMIT AND RECEIVE TERMINATIONS

The XRT83L34 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide
applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the
use of existing components and/or designs.

RECEIVER (CHANNELS 0 - 3)

NTERNAL

ECEIVE

ERMINATION

ODE

In Hardware mode, RXTSEL (Pin 83) can be tied "High" to select internal termination mode for all receive
channels or tied "Low" to select external termination mode. Individual channel control can only be done in Host
mode. By default the XRT83L34 is set for external termination mode at power up or at Hardware reset.

In Host mode, bit 7 in the appropriate channel register, (

Table 20, "Microprocessor Register #1, Bit

Description," on page 47

), is set "High" to select the internal termination mode for that specific receive channel.

If the internal termination mode (RXTSEL = "1") is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and external resistors as shown in

Table 7

OTE

: In Hardware mode, pins RXRES[1:0] control all channels.

ABLE

6: R

ECEIVE

ERMINATION

ONTROL

RXTSEL

RX TERMINATION

EXTERNAL

INTERNAL

IGURE

13. S

IMPLIFIED

IAGRAM

FOR

THE

NTERNAL

ECEIVE

AND

RANSMIT

ERMINATION

ODE

TTIP

TRING

1:2

, 100

110

or 120

0.68

int

TTIP

TRING

T X

Line Driver

RTIP

RRING

1:1

RTIP

RRIN G

R X

Equalizer

int

Channel _n

TPO S

TN EG

TC LK

RPOS

R N EG

RC LK

, 100

110

or 120

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

TRANSMITTER (CHANNELS 0 - 3)

RANSMIT

ERMINATION

ODE

In Hardware mode, TXTSEL (Pin 84) can be tied "High" to select internal termination mode for all transmit
channels or tied "Low" for external termination. Individual channel control can be done only in Host mode. In
Host mode, bit 6 in the appropriate register for a given channel is set "High" to select the internal termination
mode for that specific transmit channel, see

Table 20, "Microprocessor Register #1, Bit Description," on

page 47

For internal termination, the transformer turns ratio is always 1:2. In internal mode, no external resistors are
used. An external capacitor of 0.68

F is used for proper operation of the internal termination circuitry, see

Figure 13

XTERNAL

RANSMIT

ERMINATION

ODE

By default the XRT83L34 is set for external termination mode at power up or at Hardware reset.

When external transmit termination mode is selected, the internal termination circuitry is disabled. The value of
the external resistors is chosen for a specific application according to the turns ratio selected by TRATIO (Pin
127) in Hardware mode or bit 0 in the appropriate register for a specific channel in Host mode, see

Table 10

and

Table 22, "Microprocessor Register #3, Bit Description," on page 51

Figure 14

is a simplified block

IGURE

15. S

IMPLIFIED

IAGRAM

FOR

XTERNAL

ERMINATION

ODE

(RXTSEL= 0)

ABLE

8: T

RANSMIT

ERMINATION

ONTROL

TXTSEL

TX TERMINATION

RANSFORMER

ATIO

EXTERNAL

1:2.45

INTERNAL

1:2

ABLE

9: T

ERMINATION

ELECT

ONTROL

TERSEL1

TERSEL0

TERMINATION

100

110

120

9 .1

T T IP

T R IN G

R T I P

R R I N G

7 5

X R T 8 3 L 3 4 L IU

7 5

1 :2 .4 5

1 : 1

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

diagram for T1 (100

) in the external termination mode.

Figure 15

is a simplified block diagram for E1 (75

) in

the external termination mode.

Table 11

summarizes the transmit terminations.

REDUNDANCY APPLICATIONS

Telecommunication system design requires signal integrity and reliability. When a T1/E1 primary line card has
a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without
losing data. System designers can achieve this by implementing common redundancy schemes with the
XRT83L34 Line Interface Unit (LIU). The XRT83L34 offers features that are tailored to redundancy
applications while reducing the number of components and providing system designers with solid reference
designs. These features allow system designers to implement redundancy applications that ensure reliability.
The Internal Impedance mode eliminates the need for external relays when using the 1:1 and 1+1 redundancy
schemes.

ABLE

10: T

RANSMIT

ERMINATION

ONTROL

TRATIO

URNS

ATIO

1:2

1:2.45

ABLE

11: T

RANSMIT

ERMINATIONS

TERSEL1

TERSEL0

TXTSEL

TRATIO

int

ext

EXTERNAL

SET

CONTROL

BITS

n, R

ext

AND

ext

ARE

SUGGESTED

SETTINGS

INTERNAL

100

2.45

3.1

12.5

0.68

110

2.45

3.1

13.75

0.68

2.45

6.2

9.1

9.4

0.68

120

2.45

6.2

9.1

0.68

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

PROGRAMMING CONSIDERATIONS

In many applications switching the control of the transmitter outputs and the receiver line impedance to
hardware control will provide faster transmitter ON/OFF switching.

In Host Mode, there are two bits in register 130 (82H) that control the transmitter outputs and the Rx line
impedance select, TXONCNTL (Bit 7) and TERCNTL (Bit 6).

Setting bit-7 (TXONCNTL) to a "1" transfers the control of the Transmit On/Off function to the TXON_n
Hardware control pins. (Pins 90 through 93 and pins 169 through 172).

Setting bit-6 (TERCNTL) to a "1" transfers the control of the Rx line impedance select (RXTSEL) to the
RXTSEL Hardware control pin (pin 83).

Either mode works well with redundancy applications. The user can determine which mode has the fastest
switching time for a unique application.

TYPICAL REDUNDANCY SCHEMES

·1:1 One backup card for every primary card (Facility Protection)

·1+1 One backup card for every primary card (Line Protection)

·N+1One backup card for N primary cards

1:1 REDUNDANCY

A 1:1 facility protection redundancy scheme has one backup card for every primary card. When using 1:1
redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. This eliminates
the need for external relays and provides one bill of materials for all interface modes of operation. The transmit
and receive sections of the LIU device are described separately.

1+1 REDUNDANCY

A 1+1 line protection redundancy scheme has one backup card for every primary card, and the receivers on
the backup card are monitoring the receiver inputs. Therefore, the receivers on both cards need to be active.
The transmit outputs require no external resistors. The transmit and receive sections of the LIU device are
described separately.

TRANSMIT 1:1 & 1+1 REDUNDANCY

For 1:1 and 1+1 redundancy, the transmitters on the primary and backup card should be programmed for
Internal Impedance mode. The transmitters on the backup card should be tri-stated. Select the appropriate
impedance for the desired mode of operation, T1/E1/J1. A 0.68uF capacitor is used in series with TTIP for
blocking DC bias. See

Figure 16

for a simplified block diagram of the transmit section for 1:1 and 1+1

redundancy scheme.

OTE

: For simplification, the over voltage protection circuitry was omitted.

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

RECEIVE 1:1 & 1+1 REDUNDANCY

For 1:1 and 1+1 redundancy, the receivers on the primary card should be programmed for Internal Impedance
mode. The receivers on the backup card should be programmed for External Impedance mode. Since there is
no external resistor in the circuit, the receivers on the backup card will be high impedance. This key design
feature eliminates the need for relays and provides one bill of materials for all interface modes of operation.
Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup
card to Internal Impedance mode, then the primary card to External Impedance mode. See

Figure 17

for a

simplified block diagram of the receive section for a 1:1 and 1+1 redundancy scheme.

OTE

: For simplification, the over voltage protection circuitry was omitted.

IGURE

16. S

IMPLIFIED

LOCK

IAGRAM

THE

RANSMIT

ECTION

FOR

1:1 & 1+1 R

EDUNDANCY

IGURE

17. S

IMPLIFIED

LOCK

IAGRAM

- R

ECEIVE

ECTION

FOR

1:1

AND

1+1 R

EDUNDANCY

T 1 /E 1 L in e

B a ckp la n e In te rfa ce

P rim a ry C a rd

B a cku p C a rd

X R T 8 3 L 3 4

T x

L in e In te rfa ce C a rd

0 .6 8

T xT S E L =1 , In te rn a l

1 :2 o r 1 :2 .4 5

R xT S E L =0 , E xte rn a l

R xT S E L =1 , In te rn a l

B a ckp la n e In te rfa ce

P rim a ry C a rd

B a cku p C a rd

X R T 8 3 L 3 4

R x

L in e In te rfa ce C a rd

T 1 /E 1 L in e

R x

1 :1

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

N+1 REDUNDANCY

N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention,
external relays are necessary when using this redundancy scheme. The advantage of relays is that they create
complete isolation between the primary cards and the backup card. This allows all transmitters and receivers
on the primary cards to be configured in internal impedance mode, providing one bill of materials for all
interface modes of operation. The transmit and receive sections of the XRT83L34 are described separately.

TRANSMIT

For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode
providing one bill of materials for T1/E1/J1. The transmitters on the backup card do not have to be tri-stated. To
swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A
0.68

F capacitor is used in series with TTIP for blocking DC bias. See

Figure 18

for a simplified block diagram

of the transmit section for an N+1 redundancy scheme.

OTE

: For simplification, the over voltage protection circuitry was omitted.

IGURE

18. S

IMPLIFIED

LOCK

IAGRAM

- T

RANSMIT

ECTION

FOR

N+1 R

EDUNDANCY

B a ckp lan e In terfa ce

P rim a ry C a rd

X R T 83 L 4

T x

Lin e In te rfac e C ard

0 .68

T 1/E 1 Lin e

P rim ary C a rd

X R T 83 L3 4

T x

P rim a ry C a rd

X R T 83 L 34

T x

B a cku p C a rd

X R T 83 L 34

T x

T 1 /E 1 L ine

T xT S E L=1 , Internal

T xT S E L = 1 , Inte rn a l

1:2 or 1 :2.45

0 .68

0.6 8

1:2 or 1 :2.45

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

PATTERN TRANSMIT AND DETECT FUNCTION

Several test and diagnostic patterns can be generated and detected by the chip. In Hardware mode each
channel can be independently programmed to transmit an All Ones pattern by applying a "High" level to the
corresponding TAOS_n pin. In Host mode, the three interface bits TXTEST[2:0] control the pattern generation
and detection independently for each channel according to

Table 12

TRANSMIT ALL ONES (TAOS)

This feature is available in both Hardware and Host modes. With the TAOS_n pin connected to a "High" level
or when interface bits TXTEST2="1", TXTEST1="0" and TXTEST0="1" the transmitter ignores input from
TPOS_n/TDATA_n and TNEG_n/CODES_n pins and sends a continuous AMI encoded all "Ones" signal to the
line, using TCLK_n clock as the reference. In addition, when the Hardware pin and interface bit ATAOS is
activated, the chip will automatically transmit the All "Ones" data from any channel that detects an RLOS
condition. This feature is not available on a per channel basis. TCLK_n must NOT be tied "Low".

NETWORK LOOP CODE DETECTION AND TRANSMISSION

This feature is available in Host mode only. When the interface bits TXTEST2="1", TXTEST1="1" and
TXTEST0="0" the chip is enabled to transmit the "00001" Network Loop-Up Code from the selected channel
requesting a Loop-Back condition from the remote terminal. Simultaneously setting the interface bits
NLCDE1="0" and NLCDE0="1" enables the Network Loop-Up code detection in the receiver. If the "00001"
Network Loop-Up code is detected in the receive data for longer than 5 seconds, the NLCD bit in the interface
register is set indicating that the remote terminal has activated remote Loop-Back and the chip is receiving its
own transmitted data. When the interface bits TXTEST2="1", TXTEST1="1" and TXTEST0="1" the chip is
enabled to transmit the Network Loop-Down Code (TLDC) "001" from the selected channel requesting the
remote terminal the removal of the Loop-Back condition.

In the Host mode each channel is capable of monitoring the contents of the receive data for the presence of
Loop-Up or Loop-Down code from the remote terminal. In the Host mode the two interface bits NLCDE[1:0]
control the Loop-Code detection independently for each channel according to

Table 13

Setting the interface bits to NLCDE1="0" and NLCDE0="1" activates the detection of the Loop-Up code in the
receive data. If the "00001" Network Loop-Up code is detected in the receive data for longer than 5 seconds,
the NLCD interface bit is set to "1" and stays in this state for as long as the receiver continues to receive the

ABLE

12: P

ATTERN

TRANSMISSION

CONTROL

TXTEST2

TXTEST1

TXTEST0

EST

ATTERN

None

TDQRSS

TAOS

TLUC

TLDC

ABLE

13: L

OOP

-C

ODE

ETECTION

ONTROL

NLCDE1

NLCDE0

CONDITION

Disable Loop-Code Detection

Detect Loop-Up Code in Receive Data

Detect Loop-Down Code in Receive Data

Automatic Loop-Code detection and Remote Loop-Back Activation

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

Network Loop-Up Code. In this mode if the NLCD interrupt is enabled, the chip will initiate an interrupt on every
transition of NLCD. The host has the option to ignore the request from the remote terminal, or to respond to the
request and manually activate Remote Loop-Back. The host can subsequently activate the detection of the
Loop-Down Code by setting NLCDE1="1" and NLCDE0="0". In this case, receiving the "001" Loop-Down Code
for longer than 5 seconds will set the NLCD bit to "1" and if the NLCD interrupt is enabled, the chip will initiate
an interrupt on every transition of NLCD. The host can respond to the request from the remote terminal and
remove Loop-Back condition. In the manual Network Loop-Up (NLCDE1="0" and NLCDE0="1") and Loop-
Down (NLCDE1="1" and NLCDE0="0") Code detection modes, the NLCD interface bit will be set to "1" upon
receiving the corresponding code in excess of 5 seconds in the receive data. The chip will initiate an interrupt
any time the status of the NLCD bit changes and the Network Loop-code interrupt is enabled.

In the Host mode, setting the interface bits NLCDE1="1" and NLCDE0="1" enables the automatic Loop-Code
detection and Remote Loop-Back activation mode if, TXTEST[2:0] is NOT equal to "110". As this mode is
initiated, the state of the NLCD interface bit is reset to "0" and the chip is programmed to monitor the receive
input data for the Loop-Up Code. If the "00001" Network Loop-Up Code is detected in the receive data for
longer than 5 seconds in addition to the NLCD bit in the interface register being set, Remote Loop-Back is
automatically activated. The chip stays in remote Loop-Back even if it stops receiving the "00001" pattern. After
the chip detects the Loop-Up code, sets the NLCD bit and enters Remote Loop-Back, it automatically starts
monitoring the receive data for the Loop-Down code. In this mode however, the NLCD bit stays set even if the
receiver stops receiving the Loop-Up code, which is an indication to the host that the Remote Loop-Back is still
in effect. Remote Loop-Back is removed if the chip detects the "001" Loop-Down code for longer than 5
seconds. Detecting the "001" code also results in resetting the NLCD interface bit and initiating an interrupt.
The Remote Loop-Back can also be removed by taking the chip out of the Automatic detection mode by
programming it to operate in a different state. The chip will not respond to remote Loop-Back request if Local
Analog Loop-Back is activated locally. When programmed in Automatic detection mode the NLCD interface bit
stays "High" for the whole time the Remote Loop-Back is activated and initiates an interrupt any time the status
of the NLCD bit changes provided the Network Loop-code interrupt is enabled.

TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS)

Each channel of XRT83L34 includes a QRSS pattern generation and detection block for diagnostic purposes
that can be activated only in the Host mode by setting the interface bits TXTEST2="1", TXTEST1="0" and

TXTEST0="0". For T1 systems, the QRSS pattern is a 2

-1pseudo-random bit sequence (PRBS) with no

more than 14 consecutive zeros. For E1 systems, the QRSS pattern is 2

-1 PRBS with an inverted output.

With QRSS and Analog Local Loop-Back enabled simultaneously, and by monitoring the status of the QRPD
interface bit, all main functional blocks within the transceiver can be verified.

When the receiver achieves QRSS synchronization with fewer than 4 errors in a 128 bits window, QRPD
changes from "Low" to "High". After pattern synchronization, any bit error will cause QRPD to go "Low" for one
clock cycle. If the QRPDIE bit is enabled, any transition on the QRPD bit will generate an interrupt.

With TDQRSS activated, a bit error can be inserted in the transmitted QRSS pattern by transitioning the
INSBER interface bit from "0" to "1". Bipolar violation can also be inserted either in the QRSS pattern, or input
data when operating in the single-rail mode by transitioning the INSBPV interface bit from "0" to "1". The state
of INSBER and INSBPV bits are sampled on the rising edge of the TCLK_n. To insure the insertion of the bit
error or bipolar violation, a "0" should be written in these bit locations before writing a "1".

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

LOOP-BACK MODES

The XRT83L34 supports several Loop-Back modes under both Hardware and Host control. In Hardware
mode the two LOOP[1:0] pins control the Loop-Back functions for each channel independently according to

Table 14

In Host mode the Loop-Back functions are controlled by the three LOOP[2:0] interface bits. Each channel can
be programmed independently according to

Table 15

LOCAL ANALOG LOOP-BACK (ALOOP)

With Local Analog Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog
input of the receiver. External inputs at RTIP/RRING in this mode are ignored while valid transmit data
continues to be sent to the line. Local Analog Loop-Back exercises most of the functional blocks of the
XRT83L34 including the jitter attenuator which can be selected in either the transmit or receive paths. Local
Analog Loop-Back is shown in

Figure 20

In this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path.

ABLE

14: L

OOP

BACK

CONTROL

ARDWARE

MODE

LOOP1

LOOP0

OOP

BACK

ODE

None

Analog

Remote

Digital

ABLE

15: L

OOP

BACK

CONTROL

OST

MODE

LOOP2

LOOP1

LOOP0

OOP

BACK

ODE

None

Dual

Analog

Remote

Digital

IGURE

20. L

OCAL

NALOG

OOP

BACK

SIGNAL

FLOW

Data &

Clock

Recovery

Decoder

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

Timing
Control

TTIP

TRING

RTIP

RRING

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

REMOTE LOOP-BACK (RLOOP)

With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is
looped back to the transmit path using RCLK as transmit timing. In this mode transmit clock and data are
ignored, while RCLK and receive data will continue to be available at their respective output pins. Remote
Loop-Back with jitter attenuator selected in the receive path is shown in

Figure 21

In the Remote Loop-Back mode if the jitter attenuator is selected in the transmit path, the receive data from the
Clock and Data Recovery block is looped back to the transmit path and is applied to the jitter attenuator using
RCLK as transmit timing. In this mode the transmit clock and data are also ignored, while RCLK and received
data will continue to be available at their respective output pins. Remote Loop-Back with the jitter attenuator
selected in the transmit path is shown in

Figure 22

IGURE

21. R

EMOTE

OOP

BACK

MODE

WITH

JITTER

ATTENUATOR

SELECTED

RECEIVE

PATH

IGURE

22. R

EMOTE

OOP

BACK

MODE

WITH

JITTER

ATTENUATOR

SELECTED

RANSMIT

PATH

Decoder

Timing
Control

Data &

Clock

Recovery

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

TTIP

TRING

RTIP

RRING

Decoder

Timing

Control

Clock &

Data

Recovery

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

TTIP

TRING

RTIP

RRING

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

DIGITAL LOOP-BACK (DLOOP)

Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the
corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive
data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature
allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is
shown in

Figure 23

DUAL LOOP-BACK

Figure 24

depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit path

will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the
recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without
passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator
to the RCLK and RPOS/RDATA and RNEG pins.

IGURE

23. D

IGITAL

OOP

BACK

MODE

WITH

JITTER

ATTENUATOR

SELECTED

RANSMIT

PATH

IGURE

24. S

IGNAL

FLOW

UAL

LOOP

BACK

MODE

Decoder

Timing
Control

Data &

Clock

Recovery

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

TTIP

TRING

RTIP

RRING

Decoder

Timing
Control

Data &

Clock

Recovery

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

TTIP

TRING

RTIP

RRING

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

MICROPROCESSOR PARALLEL INTERFACE

XRT83L34 is equipped with a microprocessor interface for easy device configuration. The parallel port of the
XRT83L34 is compatible with both Intel and Motorola address and data buses. The XRT83L34 has an 8-bit
address A[7:0] input and 8-bit bi-directional data bus D[7:0]. The signals required for a generic microprocessor
to access the internal registers are described in

Table 16

ABLE

16: M

ICROPROCESSOR

INTERFACE

SIGNAL

DESCRIPTION

D[7:0]

Data Input (Output): 8 bits bi-directional Read/Write data bus for register access.

A[7:0]

Address Input: 8 bit address to select internal register location.

PTS1

PTS2

Microprocessor Type Select:

PCLK

Microprocessor Clock Input: Input clock for synchronous microprocessor operation. Maximum
clock speed is 54MHz. This pin is internally pulled "Low" for asynchronous microprocessor operation
when no clock is present.

ALE_AS

Address Latch Input (Address Strobe):

-Intel bus timing, the address inputs are latched into the internal register on the falling edge of ALE.

-Motorola bus timing, the address inputs are latched into the internal register on the falling edge of
AS.

Chip Select Input: This signal must be "Low" in order to access the parallel port.

RD_DS

Read Input (Data Strobe):

-Intel bus timing, a "Low" pulse on RD selects a read operation when CS pin is "Low".

-Motorola bus timing, a "Low" pulse on DS indicates a read or write operation when CS pin is "Low".

WR_R/W

Write Input (Read/Write):

-Intel bus timing, a "Low" pulse on WR selects a write operation when CS pin is "Low".

-Motorola bus timing, a "High" pulse on R/W selects a read operation and a "Low" pulse on R/W
selects a write operation when CS pin is "Low".

RDY_DTACK

Ready Output (Data Transfer Acknowledge Output):

-Intel bus timing, RDY is asserted "High" to indicate the XRT83L34 has completed a read or write
operation.

-Motorola bus timing, DTACK is asserted "Low" to indicate the XRT83L34 has completed a read or
write operation.

INT

Interrupt Output: This pin is asserted "Low" to indicate an interrupt caused by an alarm condition in
the device status registers. The activation of this pin can be blocked by setting the GIE bit to "0" in the
Command Control register.

P T S 2

P T S 1

P T yp e

6 8 H C 1 1 , 8 0 5 1 , 8 0 C 1 8 8 (a syn c.)

M o to ro la 6 8 K (a syn c.)

In te l x8 6 (syn c.)

In te l i9 6 0 , M o to ro la 8 6 0 (syn c.)

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

MICROPROCESSOR REGISTER TABLES

The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 7 bit
registers for independent programming and control. There are four additional registers for global control of all
channels and two registers for device identification and revision numbers. The remaining registers are for
factory test and future expansion. The control register map and the function of the individual bits are
summarized in

Table 17

and

Table 18

respectively.

ABLE

17: M

ICROPROCESSOR

EGISTER

DDRESS

EGISTER

UMBER

EGISTER

DDRESS

UNCTION

HEX

BINARY

0 - 15

0x00 - 0x0F

0000000 - 0001111

Channel 0 Control Registers

16 - 31

0x10 -0x1F

0010000 - 0011111

Channel 1 Control Registers

32 - 47

0x20 - 0x2F

0100000 - 0101111

Channel 2 Control Registers

48 - 63

0x30 - 0x3F

0110000 - 0111111

Channel 3 Control Registers

64 - 67

0x40 - 0x43

1000000 - 1000011

Command Control Registers for All 4 Channels

68 - 75

0x44 - 0x4B

1000100 - 1001011

R/W registers reserved for testing purpose.

76-125

0x4C - 0x7D

1001100 - 1111101

Reserved

126

0x7E

1111110

Device ID

127

0x7F

1111111

Device Revision ID

ABLE

18: M

ICROPROCESSOR

EGISTER

ESCRIPTION

. #

DDRESS

YPE

Channel 0 Control Registers

0000000

Hex 0x00

R/W

Reserved

RXON_n

EQC4_n

EQC3_n

EQC2_n

EQC1_n

EQC0_n

0000001

Hex 0x01

R/W

RXTSEL_n

TXTSEL_n

TERSEL1_n

TERSEL0_n

JASEL1_n

JASEL0_n

JABW_n

FIFOS_n

0000010

Hex 0x02

R/W

INVQRSS_n

TXTEST2_n

TXTEST1_n

TXTEST0_n

TXON_n

LOOP2_n

LOOP1_n

LOOP0_n

0000011

Hex 0x03

R/W

NLCDE1_n

NLCDE0_n

CODES_n

RXRES1_n

RXRES0_n

INSBPV_n

INSBER_n

TRATIO_n

0000100

Hex 0x04

R/W

Reserved

DMOIE_n

FLSIE_n

LCVIE_n

NLCDIE_n

AISDIE_n

RLOSIE_n

QRPDIE_n

0000101

Hex 0x05

Reserved

DMO_n

FLS_n

LCV_n

NLCD_n

AISD_n

RLOS_n

QRPD_n

0000110

Hex 0x06

RUR

Reserved

DMOIS_n

FLSIS_n

LCVIS_n

NLCDIS_n

AISDIS_n

RLOSIS_n

QRPDIS_n

0000111

Hex 0x07

Reserved

CLOS5_n

CLOS4_n

CLOS3_n

CLOS2_n

CLOS1_n

CLOS0_n

0001000

Hex 0x08

R/W

B6S1_n

B5S1_n

B4S1_n

B3S1_n

B2S1_n

B1S1_n

B0S1_n

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

0001001

Hex 0x09

R/W

B6S2_n

B5S2_n

B4S2_n

B3S2_n

B2S2_n

B1S2_n

B0S2_n

0001010

Hex 0x0A

R/W

B6S3_n

B5S3_n

B4S3_n

B3S3_n

B2S3_n

B1S3_n

B0S3_n

0001011

Hex 0x0B

R/W

B6S4_n

B5S4_n

B4S4_n

B3S4_n

B2S4_n

B1S4_n

B0S4_n

0001100

Hex 0x0C

R/W

B6S5_n

B5S5_n

B4S5_n

B3S5_n

B2S5_n

B1S5_n

B0S5_n

0001101

Hex 0x0D

R/W

B6S6_n

B5S6_n

B4S6_n

B3S6_n

B2S6_n

B1S6_n

B0S6_n

0001110

Hex 0x0E

R/W

B6S7_n

B5S7_n

B4S7_n

B3S7_n

B2S7_n

B1S7_n

B0S7_n

0001111

Hex 0x0F

R/W

B6S8_n

B5S8_n

B4S8_n

B3S8_n

B2S8_n

B1S8_n

B0S8_n

Reset = 0

Command Control Global Registers for all 8 channels

16-31

001xxxx

Hex 0x10-

0x1F

R/W

Channel 1Control Register (see Registers 0-15 for description)

32-47

010xxxx

Hex 0x20-

ox2F

R/W

Channel 2 Control Register (see Registers 0-15 for description)

48-63

011xxxx

Hex 0x30-

0x3F

R/W

Channel 3 Control Register (see Registers 0-15 for description)

Command Control Global Registers

1000000

Hex 0x40

R/W

SR/DR

ATAOS

RCLKE

TCLKE

DATAP

Reserved

GIE

SRESET

1000001

Hex 0x41

R/W

E1arben

CLKSEL2

CLKSEL1

CLKSEL0

MCLKRATE

RXMUTE

EXLOS

ICT

1000010

Hex 0x42

R/W

GAUGE1

Gauge2

TXONCNTL

TERCNTL

SL_1

SL_0

EQG_1

EQG_0

1000011

Hex 0x43

R/W

Reserved

Test Registers for channels 0 - 3

1000100

Hex 0x44

R/W

Test byte 0

1000101

Hex 0x45

R/W

Test byte 1

1000110

Hex 0x46

R/W

Test byte 2

1000111

Hex 0x47

R/W

Test byte 3

1001000

Hex 0x48

R/W

Test byte 4

1001001

Hex 0x49

R/W

Test byte 5

ABLE

18: M

ICROPROCESSOR

EGISTER

ESCRIPTION

. #

DDRESS

YPE

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

ABLE

20: M

ICROPROCESSOR

EGISTER

#1, B

ESCRIPTION

EGISTER

DDRESS

0000001

0010001

0100001

0110001

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

RXTSEL_n

Receiver Termination Select: In Host mode, this bit is used
to select between the internal and external line termination
modes for the receiver according to the following table;

R/W

TXTSEL_n

Transmit Termination Select: In Host mode, this bit is used
to select between the internal and external line termination
modes for the transmitter according to the following table;

R/W

TERSEL1_n

Termination Impedance Select1:

In Host mode and in internal termination mode, (TXTSEL = "1"
and RXTSEL = "1") TERSEL[1:0] control the transmit and
receive termination impedance according to the following
table;

In the internal termination mode, the receiver termination of
each receiver is realized completely by internal resistors or by
the combination of internal and one fixed external resistor.

In the internal termination mode, the transmitter output should
be AC coupled to the transformer.

R/W

TERSEL0_n

Termination Impedance Select bit 0:

See description of bit D5 for the function of this bit.

R/W

RXTSEL

RX Termination

External

Internal

TXTSEL

TX Termination

External

Internal

TERSEL1 TERSEL0

Termination

100

110

120

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

ABLE

21: M

ICROPROCESSOR

EGISTER

#2, B

ESCRIPTION

EGISTER

DDRESS

0000010

0010010

0100010

0110010

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

INVQRSS_n Invert QRSS Pattern: When TQRSS is active, Writing a "1" to

this bit inverts the polarity of transmitted QRSS pattern. Writing
a "0" sends the QRSS pattern with no inversion.

R/W

TXTEST2_n

Transmit Test Pattern bit 2: This bit together with TXTEST1
and TXTEST0 are used to generate and transmit test patterns
according to the following table:

TDQRSS (Transmit/Detect Quasi-Random Signal): This
condition when activated enables Quasi-Random Signal
Source generation and detection for the selected channel

number n. In a T1 system QRSS pattern is a 2

-1 pseudo-

random bit sequence (PRBS) with no more than 14 consecu-

tive zeros. In a E1 system, QRSS is a 2

-1 PRBS pattern.

TAOS (Transmit All Ones): Activating this condition enables
the transmission of an All Ones Pattern from the selected
channel number n.

TLUC (Transmit Network Loop-Up Code): Activating this
condition enables the Network Loop-Up Code of "00001" to be
transmitted to the line for the selected channel number n.
When Network Loop-Up code is being transmitted, the
XRT83L34 will ignore the Automatic Loop-Code detection and
Remote Loop-Back activation (NLCDE1 ="1", NLCDE0 ="1", if
activated) in order to avoid activating Remote Digital Loop-
Back automatically when the remote terminal responds to the
Loop-Back request.

TLDC (Transmit Network Loop-Down Code): Activating this
condition enables the network Loop-Down Code of "001" to be
transmitted to the line for the selected channel number n.

R/W

TXTEST1_n

Transmit Test pattern bit 1: See description of bit D6 for the
function of this bit.

R/W

TXTEST0_n

Transmit Test Pattern bit 0: See description of bit D6 for the
function of this bit.

R/W

No Pattern

TDQRSS

TAOS

TLUC

Test Pattern

TLDC

TXTEST1

TXTEST0

TXTEST2

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

ABLE

22: M

ICROPROCESSOR

EGISTER

#3, B

ESCRIPTION

EGISTER

DDRESS

0000011

0010011

0100011

0110011

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

NLCDE1_n

Network Loop Code Detection Enable Bit 1:

This bit together with NLCDE0_n control the Loop-Code detec-
tion of each channel.

When NLCDE1 ="0" and NLCDE0 = "1" or NLCDE1 = "1" and
NLCDE0 = "0", the chip is manually programmed to monitor
the receive data for the Loop-Up or Loop-Down code respec-
tively.When the presence of the "00001" or "001" pattern is
detected for more than 5 seconds, the status of the NLCD bit is
set to "1" and if the NLCD interrupt is enabled, an interrupt is
initiated.The Host has the option to control the Loop-Back
function manually.

Setting the NLCDE1 = "1" and NLCDE0 = "1" enables the
Automatic Loop-Code detection and Remote Loop-Back acti-
vation mode. As this mode is initiated, the state of the NLCD
interface bit is reset to "0" and the chip is programmed to mon-
itor the receive data for the Loop-Up code. If the "00001" pat-
tern is detected for longer than 5 seconds, the NLCD bit is set
"1", Remote Loop-Back is activated and the chip is automati-
cally programmed to monitor the receive data for the Loop-
Down code. The NLCD bit stays set even after the chip stops
receiving the Loop-Up code. The Remote Loop-Back condition
is removed when the chip receives the Loop-Down code for
more than 5 seconds or if the Automatic Loop-Code detection
mode is terminated.

R/W

NLCDE0_n

Network Loop Code Detection Enable Bit 0:

See description of D7 for function of this bit.

R/W

CODES_n

Encoding and Decoding Select:

Writing a "0" to this bits selects HDB3 or B8ZS encoding and
decoding for channel number n. Writing "1" selects an AMI
coding scheme. This bit is only active when single rail mode is
selected.

R/W

NLCDE1

NLCDE0

Function

Disable Loop-code
detection
Detect Loop-Up code
in receive data
Detect Loop-Down
code in receive data
Automatic Loop-Code
detection

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

RXRES1_n

Receive External Resistor Control Pin 1: In Host mode, this bit
along with the RXRES0_n bit selects the value of the external
Receive fixed resistor according to the following table;

R/W

RXRES0_n

Receive External Resistor Control Pin 0: For function of this
bit see description of D4 the RXRES1_n bit.

R/W

INSBPV_n

Insert Bipolar Violation: When this bit transitions from "0" to
"1", a bipolar violation is inserted in the transmitted data
stream of the selected channel number n. Bipolar violation can
be inserted either in the QRSS pattern, or input data when
operating in single-rail mode. The state of this bit is sampled
on the rising edge of the respective TCLK_n.

OTE

: To ensure the insertion of a bipolar violation, a "0"

should be written in this bit location before writing a
"1".

R/W

INSBER_n

Insert Bit Error: With TDQRSS enabled, when this bit transi-
tions from "0" to "1", a bit error will be inserted in the transmit-
ted QRSS pattern of the selected channel number n. The state
of this bit is sampled on the rising edge of the respective
TCLK_n.

OTE

: To ensure the insertion of bit error, a "0" should be

written in this bit location before writing a "1".

R/W

TRATIO_n

Transformer Ratio Select: In the external termination mode,
writing a "1" to this bit selects a transformer ratio of 1:2 for the
transmitter. Writing a "0" sets the transmitter transformer ratio
to 1:2.45. In the internal termination mode the transmitter
transformer ratio is permanently set to 1:2 and the state of this
bit has no effect.

R/W

ABLE

22: M

ICROPROCESSOR

EGISTER

#3, B

ESCRIPTION

R XR E S1_n

R equired Fixed E xternal

R X R esistor

N o external Fixed

R esistor

240

R XR E S0_n

210

150

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

ABLE

23: M

ICROPROCESSOR

EGISTER

#4, B

ESCRIPTION

EGISTER

DDRESS

0000100

0010100

0100100

0110100

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

DMOIE_n

DMO Interrupt Enable: Writing a "1" to this bit enables DMO
interrupt generation, writing a "0" masks it.

R/W

FLSIE_n

FIFO Limit Status Interrupt Enable: Writing a "1" to this bit
enables interrupt generation when the FIFO limit is within to 3
bits, writing a "0" to masks it.

R/W

LCVIE_n

Line Code Violation Interrupt Enable: Writing a "1" to this bit
enables Line Code Violation interrupt generation, writing a "0"
masks it.

R/W

NLCDIE_n

Network Loop-Code Detection Interrupt Enable: Writing a
"1" to this bit enables Network Loop-code detection interrupt
generation, writing a "0" masks it.

R/W

AISDIE_n

AIS Interrupt Enable: Writing a "1" to this bit enables Alarm
Indication Signal detection interrupt generation, writing a "0"
masks it.

R/W

RLOSIE_n

Receive Loss of Signal Interrupt Enable: Writing a "1" to this
bit enables Loss of Receive Signal interrupt generation, writing
a "0" masks it.

R/W

QRPDIE_n

QRSS Pattern Detection Interrupt Enable: Writing a "1" to
this bit enables QRSS pattern detection interrupt generation,
writing a "0" masks it.

R/W

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

NLCD_n

Network Loop-Code Detection:

This bit operates differently in the Manual or the Automatic
Network Loop-Code detection modes.

In the Manual Loop-Code detection mode, (NLCDE1 = "0"
and NLCDE0 = "1" or NLCDE1 = "1" and NLCDE0 = "0") this
bit gets set to "1" as soon as the Loop-Up ("00001") or Loop-
Down ("001") code is detected in the receive data for longer
than 5 seconds. The NLCD bit stays in the "1" state for as long
as the chip detects the presence of the Loop-code in the
receive data and it is reset to "0" as soon as it stops receiving
it. In this mode, if the NLCD interrupt is enabled, the chip will
initiate an interrupt on every transition of the NLCD.

When the Automatic Loop-code detection mode, (NLCDE1
= "1" and NLCDE0 ="1") is initiated, the state of the NLCD
interface bit is reset to "0" and the chip is programmed to mon-
itor the receive input data for the Loop-Up code. This bit is set
to a "1" to indicate that the Network Loop Code is detected for
more than 5 seconds. Simultaneously the Remote Loop-Back
condition is automatically activated and the chip is pro-
grammed to monitor the receive data for the Network Loop
Down code. The NLCD bit stays in the "1" state for as long as
the Remote Loop-Back condition is in effect even if the chip
stops receiving the Loop-Up code. Remote Loop-Back is
removed if the chip detects the "001" pattern for longer than 5
seconds in the receive data.Detecting the "001" pattern also
results in resetting the NLCD interface bit and initiating an
interrupt provided the NLCD interrupt enable bit is active.

When programmed in Automatic detection mode, the
NLCD interface bit stays "High" for the entire time the Remote
Loop-Back is active and initiate an interrupt anytime the status
of the NLCD bit changes. In this mode, the Host can monitor
the state of the NLCD bit to determine if the Remote Loop-
Back is activated.

AISD_n

Alarm Indication Signal Detect: This bit is set to a "1" to indi-
cate All Ones Signal is detected by the receiver. The value of
this bit is based on the current status of Alarm Indication Sig-
nal detector of channel n. If the AISDIE bit is enabled, any
transition on this bit will generate an Interrupt.

RLOS_n

Receive Loss of Signal: This bit is set to a "1" to indicate that
the receive input signal is lost. The value of this bit is based on
the current status of the receive input signal of channel n. If the
RLOSIE bit is enabled, any transition on this bit will generate
an Interrupt.

QRPD_n

Quasi-random Pattern Detection: This bit is set to a "1" to
indicate the receiver is currently in synchronization with QRSS
pattern. The value of this bit is based on the current status of
Quasi-random pattern detector of channel n. If the QRPDIE bit
is enabled, any transition on this bit will generate an Interrupt.

ABLE

24: M

ICROPROCESSOR

EGISTER

#5, B

ESCRIPTION

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

ABLE

25: M

ICROPROCESSOR

EGISTER

#6, B

ESCRIPTION

EGISTER

DDRESS

0000110

0010110

0100110

0110110

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

DMOIS_n

Driver Monitor Output Interrupt Status: This bit is set to a
"1" every time the DMO status has changed since last read.

OTE

: This bit is reset upon read.

RUR

FLSIS_n

FIFO Limit Interrupt Status: This bit is set to a "1" every time
when FIFO Limit (Read/Write pointer with +/- 3 bits apart) sta-
tus has changed since last read.

OTE

: This bit is reset upon read.

RUR

LCVIS_n

Line Code Violation Interrupt Status: This bit is set to a "1"
every time when LCV status has changed since last read.

OTE

: This bit is reset upon read.

RUR

NLCDIS_n

Network Loop-Code Detection Interrupt Status: This bit is
set to a "1" every time when NLCD status has changed since
last read.

OTE

: This bit is reset upon read.

RUR

AISDIS_n

AIS Detection Interrupt Status: This bit is set to a "1" every
time when AISD status has changed since last read.

OTE

: This bit is reset upon read.

RUR

RLOSIS_n

Receive Loss of Signal Interrupt Status: This bit is set to a
"1" every time RLOS status has changed since last read.

OTE

: This bit is reset upon read.

RUR

QRPDIS_n

Quasi-Random Pattern Detection Interrupt Status: This bit
is set to a "1" every time when QRPD status has changed
since last read.

OTE

: This bit is reset upon read.

RUR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

ABLE

27: M

ICROPROCESSOR

EGISTER

#8, B

ESCRIPTION

EGISTER

DDRESS

0001000

0011000

0101000

0111000

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S1_n -

B0S1_n

Arbitrary Transmit Pulse Shape, Segment 1:The shape of
each channel's transmitted pulse can be made independently
user programmable by selecting "Arbitrary Pulse" mode in

Table 5

. The arbitrary pulse is divided into eight time seg-

ments whose combined duration is equal to one period of
MCLK.

This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the first time segment. B6S1_n-
B0S1_n is in signed magnitude format with B6S1_n as the
sign bit and B0S1_n as the least significant bit (LSB).

R/W

ABLE

28: M

ICROPROCESSOR

EGISTER

#9, B

ESCRIPTION

EGISTER

DDRESS

0001001

0011001

0101001

0111001

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S2_n -

B0S2_n

Arbitrary Transmit Pulse Shape, Segment 2

The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in

Table 5

. The arbitrary pulse is divided into

eight time segments whose combined duration is equal to one
period of MCLK.

This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the second time segment. B6S2_n-
B0S2_n is in signed magnitude format with B6S2_n as the
sign bit and B0S2_n as the least significant bit (LSB).

R/W

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

ABLE

29: M

ICROPROCESSOR

EGISTER

#10, B

ESCRIPTION

EGISTER

DDRESS

0001010

0011010

0101010

0111010

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S3_n -

B0S3_n

Arbitrary Transmit Pulse Shape, Segment 3

The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in

Table 5

. The arbitrary pulse is divided into

eight time segments whose combined duration is equal to one
period of MCLK.

This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the third time segment. B6S3_n-
B0S3_n is in signed magnitude format with B6S3_n as the
sign bit and B0S3_n as the least significant bit (LSB).

R/W

ABLE

30: M

ICROPROCESSOR

EGISTER

#11, B

ESCRIPTION

EGISTER

DDRESS

0001011

0011011

0101011

0111011

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S4_n -

B0S4_n

Arbitrary Transmit Pulse Shape, Segment 4

The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in

Table 5

. The arbitrary pulse is divided into

eight time segments whose combined duration is equal to one
period of MCLK.

This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the fourth time segment. B6S4_n-
B0S4_n is in signed magnitude format with B6S4_n as the
sign bit and B0S4_n as the least significant bit (LSB).

R/W

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

ABLE

31: M

ICROPROCESSOR

EGISTER

#12, B

ESCRIPTION

EGISTER

DDRESS

0001100

0011100

0101100

0111100

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S5_n -

B0S5_n

Arbitrary Transmit Pulse Shape, Segment 5

The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in

Table 5

. The arbitrary pulse is divided into

eight time segments whose combined duration is equal to one
period of MCLK.

This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the fifth time segment. B6S5_n-
B0S5_n is in signed magnitude format with B6S5_n as the
sign bit and B0S5_n as the least significant bit (LSB).

R/W

ABLE

32: M

ICROPROCESSOR

EGISTER

#13, B

ESCRIPTION

EGISTER

DDRESS

0001101

0011101

0101101

0111101

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S6_n -

B0S6_n

Arbitrary Transmit Pulse Shape, Segment 6

The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in

Table 5

. The arbitrary pulse is divided into

eight time segments whose combined duration is equal to one
period of MCLK.

This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the sixth time segment. B6S6_n-
B0S6_n is in signed magnitude format with B6S6_n as the
sign bit and B0S6_n as the least significant bit (LSB).

R/W

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

ABLE

33: M

ICROPROCESSOR

EGISTER

#14, B

ESCRIPTION

EGISTER

DDRESS

0001110

0011110

0101110

0111110

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S7_n -

B0S7_n

Arbitrary Transmit Pulse Shape, Segment 7

The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in

Table 5

. The arbitrary pulse is divided into

eight time segments whose combined duration is equal to one
period of MCLK.

This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the seventh time segment.
B6S7_n-B0S7_n is in signed magnitude format with B6S7_n
as the sign bit and B0S7_n as the least significant bit (LSB).

R/W

ABLE

34: M

ICROPROCESSOR

EGISTER

#15, B

ESCRIPTION

EGISTER

DDRESS

0001111

0011111

0101111

0111111

HANNEL

UNCTION

EGISTER

YPE

ESET

ALUE

AME

Reserved

R/W

D6-D0

B6S8_n -

B0S8_n

Arbitrary Transmit Pulse Shape, Segment 8

The shape of each channel's transmitted pulse can be made
independently user programmable by selecting "Arbitrary
Pulse" mode in

Table 5

. The arbitrary pulse is divided into

eight time segments whose combined duration is equal to one
period of MCLK.

This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the eighth time segment. B6S8_n-
B0S8_n is in signed magnitude format with B6S8_n as the
sign bit and B0S8_n as the least significant bit (LSB).

R/W

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

ABLE

35: M

ICROPROCESSOR

EGISTER

#64, B

ESCRIPTION

EGISTER

DDRESS

1000000

AME

UNCTION

EGISTER

YPE

ESET

ALUE

SR/DR

Single-rail/Dual-rail Select: Writing a "1" to this bit configures
all 8 channels in the XRT83L34 to operate in the Single-rail
mode.

Writing a "0" configures the XRT83L34 to operate in Dual-rail
mode.

R/W

ATAOS

Automatic Transmit All Ones Upon RLOS: Writing a "1" to
this bit enables the automatic transmission of All "Ones" data
to the line for the channel that detects an RLOS condition.

Writing a "0" disables this feature.

R/W

RCLKE

Receive Clock Edge: Writing a "1" to this bit selects receive
output data of all channels to be updated on the negative edge
of RCLK.

Wring a "0" selects data to be updated on the positive edge of
RCLK.

R/W

TCLKE

Transmit Clock Edge: Writing a "0" to this bit selects transmit
data at TPOS_n/TDATA_n and TNEG_n/CODES_n of all
channels to be sampled on the falling edge of TCLK_n.

Writing a "1" selects the rising edge of the TCLK_n for sam-
pling.

R/W

DATAP

DATA Polarity: Writing a "0" to this bit selects transmit input
and receive output data of all channels to be active "High".

Writing a "1" selects an active "Low" state.

R/W

Reserved

GIE

Global Interrupt Enable: Writing a "1" to this bit globally
enables interrupt generation for all channels.

Writing a "0" disables interrupt generation.

R/W

SRESET

Software Reset

P Registers: Writing a "1" to this bit longer

than 10µs initiates a device reset through the microprocessor
interface. All internal circuits are placed in the reset state with
this bit set to a "1" except the microprocessor register bits.

R/W

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

CLOCK SELECT REGISTER

The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits and
the Master Clock Rate in register 0x41h. Therefore, if the clock selection bits or the MCLRATE bit are being
programmed, the frequency of the PLL output will be adjusted accordingly. During this adjustment, it is
important to "Not" write to any other bit location within the same register while selecting the input/output clock
frequency. For best results, when bits D[6:3] are being changed, the other bits D[7] and D[2:0] as shown in
Figure 25. should retain their previous values.

IGURE

25. R

EGISTER

EGISTERS

Programming Examples:

Example 1: Changing bits D[6:3]

If bits D[6:3] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.

Example 2: Changing bits D[7] and D[2:0]

If bits D[7] and D[2:0] are the only values within the register that will change in a WRITE process, the
microprocessor only needs to initiate ONE write operation.

Example 3: Changing bits within D[6:3] and the other bits

In this scenario, one must initiate TWO write operations such that bits D[6:3] and the other bits do not change
within ONE write cycle. It is recommended that bits D[6:0] and the other bits be treated as two independent
sub-registers. One can either change the clock selection bits and then change bits D[7] and D[2:0] on the
SECOND write, or vice-versa. No order or sequence is necessary.

Clock Selection Bits

ExLOS, ICT

E1arben

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

ABLE

36: M

ICROPROCESSOR

EGISTER

#65, B

ESCRIPTION

EGISTER

DDRESS

1000001

AME

UNCTION

EGISTER

YPE

ESET

ALUE

E1arben

E1 Arbitrary Pulse Enable

This bit is used to enable the Arbitrary Pulse Generators for
shaping the transmit pulse shape when E1 mode is selected.
If this bit is set to "1", all 8 channels will be configured for the
Arbitrary Mode. However, each channel is individually con-
trolled by programming the channel registers 0xn8 through
0xnF, where n is the number of the channel.

"0" = Disabled (Normal E1 Pulse Shape ITU G.703)

"1" = Arbitrary Pulse Enabled

R/W

CLKSEL2

Clock Select Inputs for Master Clock Synthesizer bit 2:

In Host mode, CLKSEL[2:0] are input signals to a programma-
ble frequency synthesizer that can be used to generate a mas-
ter clock from an external accurate clock source according to
the following table;

In Hardware mode, the state of these signals are ignored and
the master frequency PLL is controlled by the corresponding
Hardware pins.

R/W

CLKSEL1

Clock Select inputs for Master Clock Synthesizer bit 1:

See description of bit D6 for function of this bit.

R/W

CLKSEL0

Clock Select inputs for Master Clock Synthesizer bit 0:

See description of bit D6 for function of this bit.

R/W

2048

1544

M C LKE1

kH z

128

256

128

2048

1544

M CLKT1

kH z

1544

2048

1544

2048

C LK OUT/

kH z

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

C LK SEL0

C LK SEL1

CLKSEL2

1544

2048

1544

M C LK RATE

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

MCLKRATE

Master clock Rate Select: The state of this bit programs the
Master Clock Synthesizer to generate the T1/J1 or E1 clock.
The Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = "0", and the T1/J1 clock when MCLKRATE =
"1".

R/W

RXMUTE

Receive Output Mute: Writing a "1" to this bit, mutes receive
outputs at RPOS/RDATA and RNEG/LCV pins to a "0" state for
any channel that detects an RLOS condition.

OTE

: RCLK is not muted.

R/W

EXLOS

Extended LOS: Writing a "1" to this bit extends the number of
zeros at the receive input of each channel before RLOS is
declared to 4096 bits. Writing a "0" reverts to the normal mode
(175+75 bits for T1 and 32 bits for E1).

R/W

ICT

In-Circuit-Testing: Writing a "1" to this bit configures all the
output pins of the chip in high impedance mode for In-Circuit-
Testing. Setting the ICT bit to "1" is equivalent to connecting
the Hardware ICT pin 88 to ground.

R/W

ABLE

37: M

ICROPROCESSOR

EGISTER

#66, B

ESCRIPTION

EGISTER

DDRESS

1000010

AME

UNCTION

EGISTER

YPE

ESET

ALUE

GAUGE1

Wire Gauge Selector Bit 1:

This bit together with bit D6 are used to select wire gauge size
as shown in the table below.

R/W

GAUGE0

Wire Gauge Selector Bit 0:

See bit D7.

R/W

TXONCNTL

Transmit On Control:

In Host mode, setting this bit to "1" transfers the control of the
Transmit On/Off function to the TXON_n Hardware control
pins.

OTE

: This provides a faster On/Off capability for redundancy

application.

R/W

TERCNTL

Termination Control.

In Host mode, setting this bit to "1" transfers the control of the
RXTSEL to the RXTSEL Hardware control pin.

OTE

: This provides a faster On/Off capability for redundancy

application.

R/W

ABLE

36: M

ICROPROCESSOR

EGISTER

#65, B

ESCRIPTION

GAUGE1

GAUGE0

Wire Size

22 and 24 Gauge

26 Gauge

24 Gauge

22 Gauge

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

ELECTRICAL CHARACTERISTICS

ABLE

38: A

BSOLUTE

AXIMUM

ATINGS

Storage Temperature...................-65°C to + 150°C

Operating Temperature.............-40°C to + 85°C

Supply Voltage..........................-0.5V to + 3.8V

.................................................-0.5V to + 5.5V

ABLE

39: DC D

IGITAL

NPUT

AND

UTPUT

LECTRICAL

HARACTERISTICS

VDD=3.3V±5%,

=25°C,

UNLESS

OTHERWISE

SPECIFIED

ARAMETER

YMBOL

NITS

Power Supply Voltage

VDD

3.13

3.3

3.46

Input High Voltage

2.0

5.0

Input Low Voltage

-0.5

0.8

Output High Voltage @ IOH = 2.0mA

2.4

Output Low Voltage @IOL = 2mA.

0.4

Input Leakage Current (except Input pins
with Pull-up or Pull- down resistor).

±10

Input Capacitance

5.0

Output Load Capacitance

ABLE

40: XRT83L34 P

OWER

ONSUMPTION

VDD=3.3V±5%,

=25°C,

UNLESS

OTHERWISE

SPECIFIED

ODE

UPPLY

OLTAGE

MPEDANCE

TERMINATION

ESISTOR

RANSFORMER

ATIO

NIT

EST

ONDITIONS

ECEIVER

RANSMITTER

3.3V

6.2

1:1

1:2.45

510

740

50% "1's"

100% "1's"

3.3V

9.1

1:1

1:2

500

625

50% "1's"

100% "1's"

3.3V

120

6.2

1:1

1:2.45

455

480

50% "1's"

100% "1's"

3.3V

120

9.1

1:1

1:2

420

440

50% "1's"

100% "1's"

3.3V

100

1:1

1:2.45

720

1050

50% "1's"

100% "1's"

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

3.3V

100

1:1

1:2

820

1050

50% "1's"

100% "1's"

---

3.3V

---

230

All transmitters off

ABLE

41: E1 R

ECEIVER

LECTRICAL

HARACTERISTICS

VDD=3.3V±5%,

= -40°

85°C,

UNLESS

OTHERWISE

SPECIFIED

ARAMETER

NIT

EST

ONDITIONS

Receiver loss of signal:

Number of consecutive zeros before
RLOS is set

Input signal level at RLOS

RLOS De-asserted

12.5

% ones

Cable attenuation @1024kHz

ITU-G.775, ETSI 300 233

Receiver Sensitivity

(Short Haul with cable loss)

With nominal pulse amplitude of 3.0V
for 120

and 2.37V for 75

applica-

tion. With -18dB interference signal
added.

Receiver Sensitivity

(Long Haul with cable loss)

With nominal pulse amplitude of 3.0V
for 120

and 2.37V for 75

applica-

tion. With -18dB interference signal
added.

Input Impedance

Input Jitter Tolerance:

1 Hz

10kHz-100kHz

0.2

UIpp

ITU G.823

Recovered Clock Jitter

Transfer Corner Frequency

Peaking Amplitude

-0.5

kHz

ITU G.736

Jitter Attenuator Corner Fre-
quency (-3dB curve) (JABW=0)

(JABW=1)

1.5

ITU G.736

Return Loss:

51kHz - 102kHz

102kHz - 2048kHz

2048kHz - 3072kHz

ITU-G.703

ABLE

40: XRT83L34 P

OWER

ONSUMPTION

VDD=3.3V±5%,

=25°C,

UNLESS

OTHERWISE

SPECIFIED

ODE

UPPLY

OLTAGE

MPEDANCE

TERMINATION

ESISTOR

RANSFORMER

ATIO

NIT

EST

ONDITIONS

ECEIVER

RANSMITTER

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

ABLE

44: E1 T

RANSMITTER

LECTRICAL

HARACTERISTICS

VDD=3.3V±5%,

=-40°

85°C,

UNLESS

OTHERWISE

SPECIFIED

ARAMETER

NIT

EST

ONDITIONS

AMI Output Pulse Amplitude:

Application

120

Application

2.13

2.70

2.37

3.00

2.60

3.30

Transformer with 1:2 ratio and 9.1

resistor in series with each end of pri-
mary.

Output Pulse Width

224

244

264

Output Pulse Width Ratio

0.95

1.05

ITU-G.703

Output Pulse Amplitude Ratio

0.95

1.05

ITU-G.703

Jitter Added by the Transmitter Out-
put

0.025

0.05

UIpp

Broad Band with jitter free TCLK
applied to the input.

Output Return Loss:

51kHz -102kHz

102kHz-2048kHz

2048kHz-3072kHz

ETSI 300 166, CHPTT

ABLE

45: T1 T

RANSMITTER

LECTRICAL

HARACTERISTICS

VDD=3.3V±5%,

=-40°

85°C,

UNLESS

OTHERWISE

SPECIFIED

ARAMETER

NIT

EST

ONDITIONS

AMI Output Pulse Amplitude:

2.4

3.0

3.60

Use transformer with 1:2.45 ratio and
measured at DSX-1

Output Pulse Width

338

350

362

ANSI T1.102

Output Pulse Width Imbalance

ANSI T1.102

Output Pulse Amplitude Imbalance

+200

ANSI T1.102

Jitter Added by the Transmitter Out-
put

0.025

0.05

UIpp

Broad Band with jitter free TCLK
applied to the input.

Output Return Loss:

51kHz -102kHz

102kHz-2048kHz

2048kHz-3072kHz

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

OTOROLA

SYCHRONOUS

NTERFACE

IMING

The signals used in the Motorola microprocessor interface mode are: Address Strobe (AS), Data Strobe (DS),
Read/Write Enable (R/W), Chip Select (CS), Address and Data bits. The interface is compatible with the timing
of a Motorola 68000 microprocessor family with up to 16.67 MHz clock frequency. The interface timing is
shown in

Figure 31

and

Figure 32

. The I/O specifications are shown in

Table 50

IGURE

31. M

OTOROLA

68K A

SYNCHRONOUS

ROGRAMMED

I/O I

NTERFACE

IMING

ABLE

50: A

SYNCHRONOUS

- M

OTOROLA

68K - I

NTERFACE

IMING

PECIFICATION

YMBOL

ARAMETER

NITS

Valid Address to CS Falling Edge

CS Falling Edge to DS Assert

DS Assert to DTACK Assert

DS Pulse Width (t2)

CS Falling Edge to AS Falling Edge

Reset pulse width - both Motorola and Intel Operations (see

Figure 32

)

Reset pulse width

IGURE

32. M

ICROPROCESSOR

NTERFACE

IMING

- R

ESET

ULSE

IDTH

C S

A D D R [6 :0 ]

D A T A [7 :0 ]

R D _ D S

W R _ R /W

R D Y _ D TA C K

V a lid D a ta fo r R e a d b a c k

D a ta A v a ila b le to W rite In to th e L IU

R E A D O P E R A T IO N

W R IT E O P E R A TIO N

V a lid A d d re ss

A L E _ A S

Reset

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.3.4

PRELIMINARY

REVISIONS

EVISION

ESCRIPTION

A1.0.1

thru

A1.0.7

Advanced Versions

P1.1.0

Preliminary release version

P1.2.0

Added GHCI_n, SL_1, SL_0, EQG_1 and EQG_0 to Control Global Register 131. Separated Micropro-
cessor description table by register number. Moved absolute maximum and Dc electrical characteristics
before AC electrical characteristics. Replaced TBD's in electrical ables. Reformated table of contents.

P1.2.1

Added GAUGE1 and GAUGE0 to Control Global Register 131. Corrected control register binary bits.

P1.2.2

Renamed FIFO pin to GAUGE, edited definition and edited defintion of JASEL[1:0] to reflect the FIFO size
is selected by the jitter attenuator select.

P1.2.3

Redefined bits D3, D2 and D0 of register 1, in combination these bits set the jitter attenuator path and
FIFO size.

P1.2.4

Corrected typos in figures 6 and 8. Added Jitter attenuator tables in microprocessor register tables. Mod-
ified microprocessor descrptions, timing diagrams and electrical characteristics.

P1.2.5

Replaced GCHIE with Reserved in Tables 18, 23, 24,25. In the pin list description for INT, replace IMASK
bit to a "1" with GIE bit to a "0".

P1.2.6

New description for bits D6 - D0 in Tables 27 - 34 Microprocessor Registers.

P1.2.7

Revised Microprocessor interface timing diagrams and data.

P1.2.8

Corrected microprocessor timing information and edited Redundancy section.

P1.2.9

Edited section on RLOS for more detailed explanation.

P1.3.0

Changed definition of TXON_n pin. RXON_n bit included in register tables. Rx transformer ratio changed
from 2:1 to 1:1. Description of Arbitrary Pulse and Gap Clock support added.

P1.3.1

Minor edits to block diagram, changed issue date to January, corrected register 67 in table 18, corrected
table 37.

P1.3.2

Swapped the function of µPTS1 and µPTS2. Replaced µProcessor timing diagrams and timing informa-
tion, (Figures 29 and 30 -- Tables 49 and 50).

P1.3.3

Updated the Power Consumption numbers.

P1.3.4

Added the New E1 Arbitrary Pulse Feature. Added descriptions to the global registers.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XRT83L34

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XRT83L34