ChipFind - документация

Электронный компонент: XRT7234

Скачать:  PDF   ZIP

Document Outline

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
u
(510) 668-7000
u
(510) 668-7010
xr
xr
PRELIMINARY
XRT7234
E3 UNI FOR ATM
NOVEMBER `999
REV. P1.0.0
1.0 SYSTEM DESCRIPTION
The XR-T7234 E3 UNI IC for ATM consists of the following
functional sections/blocks.
Transmit Section
Transmit Utopia Interface Block
Transmit Cell Processor Block
Transmit E3 Framer Block
Receive Section
Receive Utopia Interface Block
Receive Cell Processor Block
Receive E3 Framer Block
Microprocessor Interface Section
Performance Monitor Section
Test and Diagnostic Section
Line Interface Drive and Scan Section
Each of these functional sections (and the blocks, within
these sections) combine to make a single chip device
that is capable of transmitting and receiving ATM cell
data via a E3 Transport Medium.
1.1 SYSTEM LEVEL INTERFACING
OF THE XR-T7234 E3 UNI
1.2
The system designer, when using the XR-T7234 E3
UNI IC for ATM, must (at a minimum) interface this
chip to the following entities.
The ATM Switch (or ATM Layer Processor)
A local (housekeeping) microprocessor
The E3 line
Figures 1 and 2 presents two illustrations of the UNI being
interfaced to these three entities. A brief discussion on
how to interface the UNI to these entities follows.
Interfacing to the ATM Switch
(ATM Layer Processor)
Whenever an ATM switch needs to transmit and receive
ATM cells to and from the UNI, it will typically use some
sort of "ATM Layer" processing entity to accomplish this
processing of cell data. This "ATM Switch Processing"
entity will be referred as the "ATM Layer Processor"
throughout this data sheet. The ATM Layer processor
interfaces with the XR-T7234 E3 UNI via the "Utopia
Bus" and will write in ATM cell data (in an 8-bit or 16-bit
wide parallel format) into the Transmit Utopia Interface
block (of the UNI). Additionally, the ATM Layer processor
will also receive ATM cells (in this same 8-bit or 16-bit
wide parallel format) from the Receive Utopia Interface
block (within the UNI IC).
Interfacing to the Local Microprocessor
In contrast to the ATM Layer Processor, the "local"
microprocessor (
P) interfaces with the UNI via the Micro-
processor Interface. This local "housekeeping" micropro-
cessor will typically read and write "configuration
information" from or into the on-chip registers within the
UNI IC. Further, the local microprocessor will respond to
UNI-generated interrupts, read and write PMDL (Path
Maintenance Data Link) Messages and OAM cell data
into and from the UNI IC. Finally, the local microprocessor
will "monitor" the performance of the overall system by peri-
odically reading the contents of the "Performance Monitor"
registers.
Note: The local
should not be confused with the ATM
Layer processor. The terms "local
P" and "ATM Layer
Processor" will be used throughout this data sheet in
order to make the distinction between these two "enti-
ties".
Interfacing the UNI to the E3 Line
The UNI can be interfaced to a E3 line that is operating
over a copper or optical medium. If the user intends to
interface the UNI to a copper E3 line, (e.g., over coaxial
cable), then he/she must connect the dual rail inputs
(RxPOS and RxNEG) and the dual rail outputs (TxPOS
and TxNEG) to a E3 Line Interface Unit (LIU) IC, (which is
transformer-coupled to the E3 line) in order to reliably
transmit and receive this data over the copper medium.
An example of such an LIU are the XR-T7295E (E3 Line
8
xr
xr
E3 UNI FOR ATM
XRT7234
PRELIMINARY
REV. P1.0.0
Receiver IC) and the XR-T7296 (E3 Line Transmitter IC). Figure 1 presents an illustration of the "System-Level" interfac-
ing of the XR-T7234 E3 UNI, when the E3 line signal is transmitted over a copper medium.
Figure 1. System Level Interfacing of the XR-T7234 E3 UNI (E3 Data is transmitted over Copper Medium).
Additionally, the user would connect the single-rail output pin of the UNI (TxPOS) to the "Electrical" input of an
"Electrical to Optical" converter; and connect the single-rail input pin of the UNI (RxPOS) to the "Electrical" output
of an "Optical to Electrical" converter. The "Electrical to Optical" and "Optical to Electrical" converters are "entities"
that handle the translation between the electronic and photonic modes. Figure 2 presents an illustration of the "Sys-
tem Level" interfacing of the XR-T7234 E3 UNI, when the E3 line signal is transmitted over an optical medium.
The remainder of this text will frequently refer to each of these "entities" as:
The ATM Layer Processor
The Local Microprocessor
The Line Interface Unit (LIU) IC
1.2 Internal Operation of the XR-T7234 E3 UNI device
Whenever an ATM switch, that has access to an E3 line, needs to transmit ATM cell data to a "Far-End" Terminal over
the E3 line, it will write the ATM cell data into the Transmit Utopia Interface block of the XR-T7234 E3 UNI device.
Afterwards, the Transmit Utopia Interface block will ultimately write this cell data to an internal FIFO (referred to as
Tx FIFO throughout this document); where it can be read and further processed by the Transmit Cell Processor. The
Transmit Utopia Interface block will also perform some parity checking on the data that it receives from the ATM
Layer processor. Finally, the Transmit Utopia Interface block will provide signaling to support data-flow control
ATM
Layer
Processor
Line
Interface
Unit
Microprocessor
Interface
XR-T7234
TxData
[15:0]
RxData
[15:0]
To/From
Far End
E3 UNI
TxPOS
TxNEG
RxPOS
RxNEG
ATM Switch
Local "Housekeeping" Processor
D[15:0] WRB_R
W
ALE_AS
RDS_D
S
Rdy_Dtck
TxClav
RxClav
Transmit
Utopia
Interface
Block
Transmit
Cell
Processor
Transmit
E3
Framer
Receive
Cell
Processor
Receive
Utopia
Interface
Block
Receive
E3
Framer
9
xr
xr
E3 UNI FOR ATM
XRT7234
PRELIMINARY
REV. P1.0.0
between the ATM Layer Processor and the UNI IC.
Figure 2. System Level Interfacing of the XR-T7234 E3 UNI (E3 data is transmitted over Optical Fiber).
The Transmit Cell Processor block will read in the ATM cell from the Tx FIFO. It will then (optionally) proceed to take
the first four octets of this cell and compute the HEC byte from these bytes. Afterwards the Transmit Cell Processor will insert
this HEC byte into the 5th octet position within the cell. The Transmit Cell Processor will also (optionally) scramble the
payload portion of the cell (bytes 6 through 53) in order to prevent the user data from mimicking framing or control
bits/bytes. Once the cell has gone through this process it will then be transferred to the Transmit E3 Framer.
If the Tx FIFO (within the Transmit Utopia Interface block) is depleted and has no (user) cells available, then the
Transmit Cell Processor will automatically generate Idle cells. These Idle cells will be processed in the exact same
manner as are the user cells, prior to transmission to the Transmit E3 Framer block. The Transmit Cell Processor gen-
erates these Idle Cells for "Cell-Rate" decoupling purposes. The Transmit Cell Processor also has provisions to allow
the user to generate an OAM cell via software control. Note: the OAM cells will be subjected to the same processing
(e.g., HEC Byte Calculation/Insertion and Cell Payload Scrambling) as are user and Idle cells.
The Transmit E3 Framer block will take these ATM cells (from the Transmit Cell Processor), and insert this data into
the payload portions of each outbound E3 frame. The Transmit E3 Framer will also generate overhead (OH) bytes
that support framing, performance monitoring (the EM byte), path maintenance data link as well as alarm and status
information originating from the "Near-End" Receiver section of the UNI. The purpose of these alarm and status
information bits is to alert the "Far-End" Terminal Equipment that the "Near-End" UNI Receiver has detected some
problems in receiving data from it. The Transmit E3 Framer will output this E3 data stream to an off-chip LIU (Line
Interface Unit) chip via the TxPOS, TxNEG, and TxLineClk output pins. The LIU chip will take on the responsibility of
driving the E3 data out on the E3 Transport Medium to the "Far-End" Terminal.
Likewise, whenever ATM cell data arrives to the UNI, over the E3 line, the Receive E3 Framer block will synchronize itself
to this incoming E3 Data Stream (containing ATM cells) via the RxPOS, RxNEG, and RxLineClk input pins, and pro-
ceed to "strip off" and process the OH bytes of the E3 frame. Once all of the OH bytes have been removed, the payload
portion of the received E3 Frame should consist of ATM cells.
ATM
Layer
Processor
Electrical
to
Optical
Converter
Microprocessor
Interface
XR-T7234
TxData
[15:0]
To/From
Far End
E3 UNI
TxPOS
RxPOS
ATM Switch
Local "Housekeeping" Processor
D[15:0]
WRB_RW
ALE_AS
RDS_DS
Rdy_Dtck
TxClav
RxClav
Transmit
Utopia
Interface
Block
Transmit
Cell
Processor
Transmit
E3
Framer
Receive
Cell
Processor
Receive
Utopia
Interface
Block
Receive
E3
Framer
Optical
to
Electrical
Converter
RxDa
[15:0]
10
xr
xr
E3 UNI FOR ATM
XRT7234
PRELIMINARY
REV. P1.0.0
The Receive Cell Processor takes this unframed data-stream of ATM cells from the Receive E3 Framer and performs
the following operations:
Cell Delineation
HEC Byte Verification
The Receive Cell Processor takes the first four octets of the cell (the header) and computes a HEC byte. The Receive
Cell Processor will then compare this computed HEC value with that of the fifth octet, within the cell. If the two HEC values
are equal, then the cell is then retained for further processing. If the two HEC values are not equal, then the cells with
single-bit errors are typically corrected. However, the cell is optionally discarded if multiple-bit errors are detected.
Cell Filtering
The Receive Cell Processor will optionally detect and remove Idle Cells. And can be configured to filter User and
OAM cells based upon their header byte patterns.
Cell De-Scrambling
The Receive Cell Processor will de-scramble the payload portion of the cell (the 6th through the 53rd octet), and pack
these octets in with the cell header bytes, and the HEC byte for transmission to the Receive Utopia Interface block.
Once the ATM cells have gone through the cell delineation, HEC Byte Verification, cell payload de-scrambling, and cell
filtering processes, then they will be written into the Rx FIFO, within the Receive Utopia Interface Block.
The Receive Utopia Interface block (like its Transmit counterpart) provides the industry standard ATM/PHY interface
functions. The Receive Utopia Interface Block will inform the ATM Layer Processor when it is holding ATM cell data
within the RxFIFO that needs to be read. The ATM Layer Processor can then read out this cell data, from the Receive
Utopia Interface block, and route it to the remainder of the ATM switch for further processing.
DC ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25C, VCC = 5.0V 5% unless otherwise specified
Symbol
Parameter
Min.
Typ
Max.
Units
Conditions
ICC
Power Supply Current
mA
ILL
Data Bus Tri-State Bus Leakage Current
mA
VIL
Input Low Voltage
V
VIH
Input High Voltage
VCC
V
11
xr
xr
E3 UNI FOR ATM
XRT7234
PRELIMINARY
REV. P1.0.0
VOL
Output Low Voltage
V
VOH
Output High Voltage
VCC
V
IOC
Open Drain Output Leakage Current
mA
AC ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25C, VCC = 5.0V 5% unless otherwise specified
Symbol
Parameter
Min.
Typ
Max.
Units
Conditions
Transmit Utopia Interface Block (See Figure 91)
t1
TxData[15:0] to rising edge of TxClk Setup
Time
ns
t2
TxData[15:0] Hold Time from rising edge of
TxClk
ns
t3
TxUtopia Write Enable Setup Time to rising edge
of TxClk
ns
t4
TxUtopia Write Enable Hold Time from rising
edge of TxClk
ns
t5
TxPrty Setup Time to rising edge of TxClk
ns
t6
TxPrty Hold Time from rising edge of TxClk
ns
t7
TxSoC Setup Time to rising edge of TxClk
ns
t8
TxSoC Hold Time from rising edge of TxClk
ns
t9
TxAddr[4:0] Setup Time to rising edge of TxClk
ns
t10
TxAddr[4:0] Hold Time from rising edge of TxClk
ns
t11
TxClav signal valid (not Hi-Z) from first TxClk
rising edge of valid and correct TxAddr[4:0]
ns
t12
TxClav signal Hi-Z from first TxClk rising edge
of different TxAddr[4:0]
ns
Transmit Cell Processor (GFC Serial Input Port)
--
See Figure 92
t13
Clock Period of TxGFCClk
ns
fGFCClk
Frequency of TxGFCClk
Hz
t14
Delay from rising edge of TxGFCClk to rising edge
of TxGFCMSB pin
ns
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Test Conditions: TA = 25C, VCC = 5.0V 5% unless otherwise specified
Symbol
Parameter
Min.
Typ
Max.
Units
Conditions