DM8108
8 port 10/100M Fast Ethernet Switching Controller
Preliminary
1
Version: DM8108-DS-P02
November 25, 1999
General Description
The DM8108 is an 8 port 10/100Mbit/s nonblocking
Ethernet switch with on-chip address-lookup engine. The
DM8108 provides a low-cost, high-performance switch
solution with PHYs and single SGRAM.
The DM8108 provides eight 10/100Mbit/s Fast Ethernet
interface. In half-duplex mode, all ports support back-
pressure capability to reduce the risk of data loss for a long
burst of activity. In the full-duplex mode of operation, the
device uses IEEE std. 802.3 frame-based pause protocol
for flow control. With full-duplex capability, port 0 7 support
1.6Gbit/s aggregate bandwidth connections. The DM8108
also supports port trunking/load balancing on the
10/100Mbit ports. This can be used to group ports on inter-
switch links to increase the effective bandwidth between the
systems.
The internal address-lookup engine supports up to 16.25K
unicast and unlimited multicast and broadcast addresses.
This engine performs destination and source addresses
book-keeping and comparison which also forwards
unknown destination address packets to all ports.
The DM8108 is fabricated with a .35um technology.
Working at 3.3V, the inputs are 5V tolerant and the outputs
are capable of directly driving at TTL levels.
Block Diagram
Expansion
Address
Learning
MEM
Controller
LED Control
Unit
Switching
Engine
Control &
Status
DM8108
8 port 10/100M Fast Ethernet Switching Controller
2
Preliminary
Version: DM8108-DS-P02
November 25, 1999
Features
T
Low cost Fast Ethernet Switching Controller.
O
Provide packet switching functions between
eight
10/100Mbps, auto-negotiated on-chip Fast
Ethernet ports and a proprietary Full-duplex
Expansion port.
O
Cascade max. 8 DM8108s without extra glue
logic for 64-port configuration.
T
Incorporates three 802.3 compliant 10/100Mbps
Media Access Controllers
O
Direct interface to MII (Media Independent
Interface)
O
Half/Full Duplex Support for individual port (up-
to
200Mbps/port)
O
IEEE 802.3 100Base-TX, T4.FX compatible
T
Auto-negotiation supported through Serial MII
interface
T
High-performance Distributed Switching Engine
O
Performs packet forwarding and filtering at full
wire-speed
O
148,800 packets/sec. on each Ethernet port
T
Direct support for packet buffering
O
Glue-less interface with 1 or 2 Mbytes of SDRAM
(SGRAM)
O
32 bit memory bus configuration
O
66 Mhz 90Mhz memory bus speed
O
Up-to 1.1K buffers, 1536-byte each, allocated to
receive ports
T
Support Store and Forward switching approach
O
Low last-bit to first-bit out delay
O
Allow mixed speed Ethernet packet switching
O
Allow conversion between different protocols
T
Flow control
O
Support partitioning function
O
Support back-pressure while lack of internal
resources
O
Support 802.3x PAUSE function in full duplex
mode
O
Support up to 4-port trunking for 800Mbps
bandwidth
T
Advanced Address Learning and Searching
O
Self learning mechanism
O
Cache 128 address entries internally
O
Record up-to 16K Uni-cast MAC addresses and
unlimited Multicast and Broadcast addresses
O
Automatic aging scheme
O
Broadcast filtering rate control
T
Expansion Bus
O
Up-to 8 SW devices can be cascaded via
expansion bus without extra logic
O
Full duplex mode transfer
O
Less Bus overhead
O
Automatic flow control
T
Complete status report to a simple LED interface
T
Suitable for low cost Switch market to replace
Hub
T
0.35
m process, 3.3V with 5V tolerant I/O
T
208-pin PQFP package
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Preliminary 3
Version: DM8108-DS-P02
November 25, 1999
Application Example: Low cost 8 to 64 ports 10/100 Mbps auto-sensing switch
8 8
8
10/100 BaseTx
Cascaded up-to 64 10/100Mbps Fast Ethernet ports
Application Example: Low cost auto-sensing switching hub implementation
MII MII
#1 Hub Module #4 Hub Module
10/100 BaseTx
DM8108
MEM
PHY
DM8108
PHY
DM8108
PHY
MEM
MEM
DM8108
MEM
PHY with
repeater
PHY with
repeater
PHY with
repeater
PHY with
repeater
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Preliminary 5
Version: DM8108-DS-P02
November 25, 1999
Pin Configuration
D M 8 1 0 8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
52
51
50
49
53
55
54
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
109
108
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
V S S
LEDCLK
L E D S T B
L E D D
R S T #
T E S T E N
V S S
R X E R 0
R X D V 0
COL0
C R S 0
RXCLK0
RXD0[0]
RXD0[1]
RXD0[2]
RXD0[3]
TXCLK0
T X E N 0
TXD0[0]
TXD0[1]
TXD0[2]
TXD0[3]
V D D
R X E R 1
R X D V 1
COL1
C R S 1
RXCLK1
RXD1[0]
RXD1[1]
RXD1[2]
RXD1[3]
TXCLK1
T X E N 1
TXD1[0]
TXD1[1]
TXD1[2]
TXD1[3]
V S S
R X E R 2
R X D V 2
COL2
C R S 2
RXCLK2
RXD2[0]
RXD2[1]
RXD2[2]
RXD2[3]
TXCLK2
T X E N 2
TXD2[0]
TXD2[1]
VDD
RXER3
RXDV3
TXD2[2]
TXD2[3]
COL3
RXCLK3
RXD3[0]
CRS3
RXD3[1]
RXD8[2]
RXD8[1]
RXD8[0]
RXD8[3]
RXCLK8
VSS
TXD8[3]
RXER5
SBA
SDDQM#
TXD8[2]
TXD8[1]
TXD8[0]
VDD
TXCLK8
VSS
DMA0
DMA1
DMA8
DMA3
DMA4
VSS
DMA5
DMA6
DMA7
VDD
TXD4[3]
VDD
TXCLK3
TXEN3
TXD3[0]
TXD3[3]
VSS
MIICLK
MIID
VSS
RXER4
RXDV4
COL4
CRS4
TXD3[2]
DMA2
DMA9
SDCS#
RAS#
SCLK
VSS
DMD0
COL5
CRS5
RXCLK5
RXD5[0]
RXD5[2]
RXD5[3]
RXD5[1]
TXCLK5
TXEN5
TXD5[0]
TXD5[1]
TXD5[2]
TXCLK6
RXD6[3]
T X E N 6
TXD6[0]
D M D 3 0
D M D 2 9
D M D 3 1
V S S
DMD9
DMD11
DMD10
DMD12
DMD4
DMD5
DMD3
DMD2
C R S 7
COL7
R X D V 7
R X E R 7
D M D 2 2
D M D 2 3
V S S
D M D 2 4
DMD1
DMD6
DMD7
VSS
DWE#
VSS
DMD15
V D D
D M D 1 6
D M D 1 8
D M D 1 9
D M D 2 0
TXD7[2]
DMD8
D M D 1 7
DMD14
D M D 2 1
D M D 2 5
D M D 2 6
D M D 2 7
D M D 2 8
DMD13
TXD7[3]
TXD7[0]
T X E N 7
TXCLK7
RXD7[2]
RXD7[1]
RXD7[0]
RXD7[3]
TXD6[3]
TXD6[2]
RXD6[0]
RXCLK6
C R S 6
R X D V 6
R X E R 6
V S S
RXD6[2]
RXDV5
TXD6[1]
RXD6[1]
COL6
VSS
RXCLK4
TXEN4
RXD4[2]
RXD4[1]
TXD4[0]
TXCLK4
RXD4[0]
TXD4[1]
RXD4[3]
TXD4[2]
V D D
RXCLK7
TXD5[3]
RXD3[3]
RXD3[2]
TXD7[1]
CAS#
TXD3[1]
PDF 
ZIP