1
Master
2-layer Metal
SLA4028
SLA4046
SLA4078
SLA4115
SLA4162
SLA4239
SLA4318
SLA4411
Features
3-layer Metal
SLA402T
SLA404T
SLA407T
SLA411T
SLA416T
SLA423T
SLA431T
SLA441T
Total BCs (Raw Gates)
28,260
46,864
78,600
115,388
162,864
239,468
318,308
411,257
Usable BCs
2-layer Metal
14,130
22,026
35,370
51,924
70,031
95,787
127,323
164,502
3-layer Metal
24,868
39,834
62,880
86,541
122,148
167,627
222,815
287,879
Number of PADs
116
144
184
216
256
308
352
400
(In Case of Micro Pitch)
(128)
(164)
(212)
(256)
(304)
(368)
(424)
(480)
Propagation
Internal Gates
tpd = 0.160ns (standard at 3.3V)
Delay
Input Gates
tpd = 0.400ns (standard at 5.0V) level shifter, tpd = 0.420ns (standard at 3.3V)
Output Buffers
tpd = 1.99ns (standard at 5.0V) level shifter, tpd = 1.89ns (standard at 3.3V) CL = 50pF
I/O Level
CMOS, TTL, PCI, USB*, LVDS*
Input Mode
LVTTL, TTL, CMOS, Pull-up/Pull-down, Schmitt, 2.0/3.0/3.3/5.0V Level interface (Level shifter)
Output Mode
Normal, Open drain, 3-state, Bi-directional, 2.0/3.0/3.3/5.0V Level interface (Level shifter)
* Under development
PF842-02
SLA40000 Series
s
OVERVIEW
The SLA 40000 series are super-high-density/speed, Sea-of-gate type CMOS gate arrays adopting the 0.45 m
process.
They consume less electricity, a feature of ASICs dedicated to 3.3V, while enabling high-speed-operation as well
as 3V/5V full swing I/F in the level shifter.
There are 2- and 3-metal layer for each of 8 models from 28,260 to 411,257 gates, satisfying customer needs for
a wide range of circuit size.
In addition, the series can be used with various I/F devices such as low noise output cells, PCI I/F revision 2.0, GTL
I/F*, JTAG*, fail/safe output* and test control input*, and have diverse applications such as small information
instrument and for image processing.
To develop high-speed/high-density circuits in a shorter period of time, the series enable diverse design techniques
to be used during development such as high accuracy simulation of interconnection resistance and blunted
waveform in addition to the conventional interconnection capacity components, and provide a new layout tool for
reducing clock skew.
s
FEATURES
q
Super-high density (adopting 0.45
m silicon gate CMOS with 2- and 3-metal layers)
q
High-speed operation (operation delay of internal gate = 0.160ns at 3.3V, 2-input power NAND standard)
q
Internal gate = 3.3 and 3.0V (2.0V single), I/O buffer = 5.0, 3.3 and 3.0V (2.0V single) (built-in level shifter)
q
Low power consumption (0.80
W/MHz/BC when internal cell = 3.0V)
q
Output drivability (I
OL
= 100
, 1, 3, 6, 12, 24 mA when PCI = 5.0V, I
OL
= 100
, 1, 2, 6, 12mA when PCI = 3.3V,
I
OL
= 50
, 300
, 600
, 2, 4mA when 2.0V)
q
RAM, PLL, IrDA*, and various function cells available
q
Low noise output cell, PCI I/F, USB I/F*, LVDS*, JTAG
s
PRODUCT LINEUP
q
Super-high-density/speed gate array
q
Operates on 3.3 and 3.0V power source
(level shifter is pre-installed)
q
Raw of gates: 28 to 411k gates
(sea of gates)
High Density Gate Array
2
SLA40000
Series
ELECTRONIC DEVICES MARKETING DIVISION
Electronic Device Marketing Department
IC Marketing & Engineering Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5816
Fax: +81-(0)42-587-5624
ED International Marketing Department
I
(Europe & U.S.A.)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5812
Fax: +81-(0)42-587-5564
ED International Marketing Department
II
(Asia)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5814
Fax: +81-(0)42-587-5110
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