EL2142C
January
1996
Rev
A
EL2142C
Differential Line Receiver
Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ``controlled document'' Current revisions if any to these
specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation
1996 Elantec Inc
Features
Differential input range
g
2 3V
150 MHz 3 dB bandwidth
400 V ms slewrate
g
5V supplies or single supply
50 mA minimum output current
Output swing (100X load) to
within 1 5V of supplies
Low power
b
11 mA typical
Applications
Twisted pair receiver
Differential line receiver
VGA over twisted pair
ADSL HDSL receiver
Differential to single ended
amplification
Reception of analog signals in a
noisy environment
Ordering Information
Part No
Temp Range
Package
Outline
EL2142CN
b
40 C to
a
85 C
8-pin DIP
MDP0031
EL2142CS
b
40 C to
a
85 C
8-pin SOIC
MDP0027
General Description
The EL2142C is a very high bandwidth amplifier designed to
extract the difference signal from noisy environments and is
thus primarily targeted for applications such as receiving sig-
nals from twisted pair lines or any application where common
mode noise injection is likely to occur
The EL2142C is stable for a gain of one and requires two exter-
nal resistors to set the voltage gain
The output common mode level is set by the reference pin
(V
REF
) which has a
b
3 dB bandwidth of over 100 MHz Gen-
erally this pin is grounded but it can be tied to any voltage
reference
The output can deliver a minimum of
g
50 mA and is short
circuit protected to withstand a temporary overload condition
Connection Diagrams
EL2142C SO P-DIP
2142-1
EL2142C
Differential Line Receiver
Absolute Maximum Ratings
(T
A
e
25 C)
Supply Voltage (V
CC
V
EE
)
0V to 12 6V
Maximum Output Current
g
60 mA
Storage Temperature Range
b
65 C to
a
150 C
Operating Junction Temperature
a
150 C
Lead Temperature (
k
5 sec)
a
300 C
Recommended Operating Temperature
b
40 C to
a
85 C
Important Note
All parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually
performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test
equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore T
J
e
T
C
e
T
A
Test Level
Test Procedure
I
100% production tested and QA sample tested per QA test plan QCX0002
II
100% production tested at T
A
e
25 C and QA sample tested at T
A
e
25 C
T
MAX
and T
MIN
per QA test plan QCX0002
III
QA sample tested per QA test plan QCX0002
IV
Parameter is guaranteed (but not tested) by Design and Characterization Data
V
Parameter is typical value at T
A
e
25 C for information purposes only
DC Electrical Characteristics
(V
CC
e a
5V V
EE
e b
5V T
A
e
25C V
IN
e
0V R
L
e
100 unless otherwise specified)
Parameter
Description
Min
Typ
Max
Test
Units
Level
V
supply
Supply Operating Range (V
CC
V
EE
)
g
3 0
g
5 0
g
6 3
I
V
I
S
Power Supply Current (no load)
11
14
I
mA
V
OS
Input Referred Offset Voltage
b
25
10
40
I
mV
I
IN
Input Bias Current (V
IN
V
INB
V
REF
)
b
20
6
20
I
mA
Z
IN
Differential Input Resistance
400
V
K
X
C
IN
Differential Input Capacitance
1
V
pF
V
DIFF
Differential Input Range
g
2 0
g
2 3
I
V
A
VOL
Open Loop Voltage Gain
75
V
dB
V
IN
Input Common Mode Voltage Range
b
2 6
a
4 0
I
V
V
OUT
Output Voltage Swing (50
X load to GND)
g
2 9
g
3 1
I
V
I
OUT
(min)
Minimum Output Current
50
60
I
mA
V
N
Input Referred Voltage Noise
36
V
nV
S
Hz
V
REF
Output Voltage Control Range
b
2 5
a
3 3
I
V
PSRR
Power Supply Rejection Ratio
60
70
I
dB
CMRR2
Input Common Mode Rejection Ratio (V
IN
e
g
2V)
60
70
I
dB
CMRR1
Input Common Mode Rejection Ratio (full V
IN
range)
50
60
I
dB
2
TD
is
33in
EL2142C
Differential Line Receiver
AC Electrical Characteristics
(V
CC
e a
5V V
EE
e b
5V T
A
e
25C V
IN
e
0V R
LOAD
e
100 unless otherwise specified)
Parameter
Description
Min
Typ
Max
Test
Units
Level
BW(
b
3dB)
b
3 dB Bandwidth (Gain
e
1)
150
V
MHz
SR
Slewrate
400
V
V
ms
T
stl
Settling time to 1%
15
V
ns
GBWP
Gain bandwidth product
200
V
MHz
V
REF
BW(
b
3 dB)
V
REF
b
3dB Bandwidth
130
V
MHz
V
REF
SR
V
REF
Slewrate
100
V
V
msec
dG
Differential gain at 3 58 MHz
0 2
V
%
d
i
Differential phase at 3 58 MHz
0 2
V
Pin Description
Pin Number
Pin Name
Function
1
V
FB
Feedback input
2
V
IN
Non-inverting input
3
V
INB
Inverting input
4
V
REF
Sets output voltage level to V
REF
when V
IN
e
V
INB
5
NC
6
V
CC
Positive supply voltage
7
V
EE
Negative supply voltage
8
V
OUT
Output voltage
3
TD
is
18in
EL2142C
Differential Line Receiver
Typical Performance Curves
I
S
vs Supply Voltage
2142 2
(Gain e 1)
Frequency Response
2142 3
vs Resistor R1 (Gain e 4)
Frequency Response
2142 4
CMRR vs Frequency
2142 5
V
REF
Frequency Response
2142 6
V
IN
e
2V pk pk
(GAIN e 3 R
LOAD
e
100X)
Distortion vs Frequency
2142 7
4
EL2142C
Differential Line Receiver
Applications Information
2142-8
Gain Equation
V
OUT
e
((R2
a
R1) R1)
c
(V
IN
-V
INB
a
V
REF
) when R1 tied to GND
V
OUT
e
((R2
a
R1) R1)
c
(V
IN
-V
INB
) when R1 tied to V
REF
Choice of Feedback Resistor
For a gain of one V
OUT
may be shorted back to
V
FB
but 100
X 200X improves the bandwidth
For gains greater than one there is little to be
gained from choosing resistor R1 value below
200
X for it would only result in increased power
dissipation and potential signal distortion Above
200
X the bandwidth response will develop some
peaking (for a gain of one) but substantially
higher R1 values may be used for higher voltage
gains such as up to 1 k
X at a gain of four before
peaking will develop
Capacitance Considerations
As with many high bandwidth amplifiers the
EL2142C prefers not to drive highly capacitive
loads It is best if the capacitance on V
OUT
is
kept below 10 pF if the user does not want gain
peaking to develop The V
FB
node forms a poten-
tial pole in the feedback loop so capacitance
should be minimized on this node for maximum
bandwidth
The amount of capacitance tolerated on any of
these nodes in an actual application will also be
dependent on the gain setting and the resistor
values in the feedback network
5
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