EL2021C
November
1993
Rev
F
EL2021C
Monolithic Pin Driver
Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ``controlled document'' Current revisions if any to these
specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation Patent pending
1988 Elantec Inc
Features
Wide range of programmable
analog output levels
0 5 Ampere output drive with
external transistors
Programmable Slew Rate
Low overshoot with large
capacitive loads-stable with
500 pF
3-state output
Power-down capability
Wide supply range
Overcurrent sense
Applications
Loaded circuit board testers
Digital testers
Programmable 4-quadrant power
supplies
Ordering Information
Part No
Temp Range Package Outline
EL2021CJ 0 C to a75 C
CerDIP
MDP0031
Connection Diagram
18-Pin DIP Package
2021 1
Top View
General Description
The EL2021 is designed to drive programmed voltages into dif-
ficult loads It has the required circuitry to be used as the pin
driver electronics in board test systems Capable of overpower-
ing logic outputs the part can accurately drive independently
set high and low levels with programmed Slew Rates into reac-
tive loads It can also be placed into high impedance to monitor
the load without having to disconnect Previous board testers
had multiplexing schemes to reduce the number of pin drivers
required With the small size and power consumption of the
monolithic EL2021 a driver per node with little or no multi-
plexing becomes practical Since only a few pins of ``bed-of-
nails'' board testers need be active at any given time the power-
down feature saves substantial power in large systems
Block Diagram
2021 2
Truth Table
E
OE
Data
V
OUT
Comments
0
0
0
V
CL
Active
0
0
1
V
CH
Active
0
1
X
High-Z
Third State
1
X
X
Undefined
Power-down
EL2021C
Monolithic Pin Driver
Absolute Maximum Ratings
(T
A
e
25 C)
V
a
Supply Voltage
b
0 3V to
a
16V
V
b
Supply Voltage
0 03V to
b
16V
B
a
B
b
Supply Voltages
V
b
to V
a
Sense
a
Input Voltages
(
b
2V
a
B
a
) to (0 3V
a
B
a
)
Sense
b
Input Voltages
(
b
0 3V
a
B
b
) to (2V
a
B
b
)
E VSR
OE Data
Input Voltages
b
0 3 to
a
6V
V
CH
V
CL
Input Voltages
B
b
to B
a
and V
b
to V
a
Sense Out
Output Current
b
10 mA to
a
10 mA
V
OUT
Drive
a
Drive
b
Output Currents
b
45 mA to
a
45 mA
T
J
Junction Temperature
150 C
T
A
Operating Ambient
Temperature Range
0 C to
a
75 C
T
ST
Storage Temperature
b
65 C to
a
150 C
P
D
Power Dissipation (T
A
e
25 C)
(See Curves)
1 8W
Important Note
All parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually
performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test
equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore T
J
e
T
C
e
T
A
Test Level
Test Procedure
I
100% production tested and QA sample tested per QA test plan QCX0002
II
100% production tested at T
A
e
25 C and QA sample tested at T
A
e
25 C
T
MAX
and T
MIN
per QA test plan QCX0002
III
QA sample tested per QA test plan QCX0002
IV
Parameter is guaranteed (but not tested) by Design and Characterization Data
V
Parameter is typical value at T
A
e
25 C for information purposes only
DC Electrical Characteristics
T
A
e
25 C V
a e
15 V
b e b
10V B
a e
V
CH
a
3 6V B
b e
V
CL
b
3 6V No Load Data and OE levels are L
e
2 0V and
H
e
3 0V (CMOS thresholds) E levels are L
e
1 5V and H
e
3 5V All tests done using 2N2222 and 2N2907 output transistors
with Beta
l
40
I
C
e
400 mA and Beta
l
27
I
C
e
500 mA and V
CE
e
3 1V OE and E low
Parameter
Description
Conditions
Min Typ Max
Test
Units
Level
I
S
V
a
-Supply Currents
V
CH
e
5V V
CL
e
0 VSR
e
2 5V Data
e
H or L
15
25
30
I
mA
V
CH
e
11V V
CL
e b
6V VSR
e
5V Data
e
H or L
21
33
45
IV
mA
V
CH
e b
6V V
CL
e
11V VSR
a
2 5V Data
e
H or L
15
25
30
IV
mA
I
S
disabled V
a
-Supply Currents
V
CH
e
5V V
CL
e
0V VSR
e
2 5V Data
e
H or L E
e
H
0
0 5
2 5
I
mA
I
VCH
V
CH
Input Current
V
CH
e b
1V to
a
7 5V V
CL
e
0V VSR
e
5V
b
20
5
20
I
mA
Data
e
H or L
I
VCL
V
CL
Input Current
V
CL
e b
3 5V to
a
3 5V V
CH
e
0V VSR
e
5V
b
20
b
5
20
I
mA
Data
e
H or L
I
Data
Data Input Current
V
CH
e
5V V
CL
e
0V VSR
e
5V Data
e
0 or 5V
b
50
5
50
I
mA
I
OE
OE Input Current
V
CH
e
5V V
CL
e
0V VSR
e
5V Data
e
L OE
e
0V or 5V
b
20
5
20
I
mA
I
E
E Input Current
V
CH
e
5V V
CL
e
0V VSR
e
5V Data
e
L E
e
0V or 5V
b
20
2
20
I
mA
I
VSR
VSR Input Current
V
CH
e
5V V
CL
e
0V Data
e
L VSR
e
0V or 5V
b
20
2
20
I
mA
g
I
sense
Sense Input Currents
V
CH
e
5V V
CL
e
0V VSR
e
5V Data
e
0V or 5V
b
20
5
20
IV
mA
I
B
a
I
B
b
B
a
B
b
Input Currents V
CH
e
5V V
CL
e
0V Data
e
L VSR
e
5V
b
20
5
20
IV
mA
2
TD
is
11in
TD
is
27in
EL2021C
Monolithic Pin Driver
DC Electrical Characteristics
T
A
e
25 C V
a e
15 V
b e b
10V B
a e
V
CH
a
3 6V B
b e
V
CL
b
3 6V No Load Data and OE levels are L
e
2 0V and
H
e
3 0V (CMOS thresholds) E levels are L
e
1 5V and H
e
3 5V All tests done using 2N2222 and 2N2907 output transistors
with Beta
l
40
I
C
e
400 mA and Beta
l
27
I
C
e
500 mA and V
CE
e
3 1V OE and E low
Contd
Parameter
Description
Conditions
Min
Typ
Max
Test
Units
Level
V
O
Output Voltage
V
a e
14 5V V
b e b
9 5V
V
CH
e
5V V
CL
e
0 VSR
e
1V Data
e
L
Output Current
e b
100 mA 0 mA or
a
100 mA
b
50
50
I
mV
Output Current
e b
400 mA or
a
400 mA
b
300
300
I
mV
Output Current
e b
500 mA or
a
500 mA
b
600
600
I
mV
V
CH
e
5V V
CL
e
0 VSR
e
1V Data
e
H
Output Current
e b
100 mA 0 mA or
a
100 mA
4 95
5 05
I
V
Output Current
e b
400 mA or
a
400 mA
4 7
5 3
I
V
Output Current
e b
500 mA or
a
500 mA
4 4
5 6
I
V
V
CH
e
11V V
CL
e b
6V VSR
e
1V I
OUT
e
0 Data
e
L
b
6 1
b
5 9
I
V
V
CH
e
11V V
CL
e b
6V VSR
e
1V I
OUT
e
0 Data
e
H
10 9
11 1
I
V
I
sensea
a
I
sense
Threshold V
CH
e
5V V
CL
e
0 VSR
e
2 5V R
sense
e
1
X Data
e
H
400
450
600
I
mA
I
senseb
b
I
sense
Threshold V
CH
e
5V V
CL
e
0 VSR
e
2 5V R
sense
e
1
X Data
e
L
b
400
b
450
b
600
I
mA
V
O sense
Sense Out Levels
V
CH
e
5V V
CL
e
0 VSR
e
2 5V Data L or H
Output Current
e b
350 mA or
a
350 mA
0
0 6
I
V
Output Current
e b
550 mA or
a
550 mA
3 5
5 0
I
V
I
OUT TRI
High-Impedance
V
CH
e
5V V
CL
e
0 VSR
e
2 5V Data
e
L OE
e
H
Output Leakage
Output Voltage
e b
2 5V or
a
7 5V
b
100
5
100
I
mA
AC Electrical Characteristics
DC test conditions apply except where noted For AC tests R
L
e
1k C
L
e
200 pF Delay times are measured from OE or Data
crossing 2 5V V
CH
e
5V V
CL
e
0
Parameter
Description
Conditions
Min
Typ
Max
Test
Units
Level
SR
a
a
Slew Rate
Data L to H Output from 0 5V to 4 5V VSR
e
1V
80
100
120
I
V
ms
VSR
e
3V
150
240
360
I
V
ms
SR
b
b
Slew Rate
Data H to L Output from 4 5V to 0 5V VSR
e
1V
b
80
b
100
b
120
I
V
ms
VSR
e
3V
b
150
b
240
b
360
I
V
ms
SRSYM
Slew Rate Symmetry
(SR
a
)
b
(SR
b
)
(SR
a
)
a
(SR
b
)
(
VSR
e
1V
VSR
e
2V
b
10
10
I
%
b
20
20
IV
%
T
pd
Propagation Delay
Data L to H Output to 0 2V VSR
e
2 5V
6 5
9
11 5
I
ns
Data H to L Output to 4 8V VSR
e
2 5V
6 5
9
11 5
I
ns
T
s
Settling Time
VSR
e
5V Data L to H Output 4 5V to 5V
g
0 2V
30
IV
ns
VSR
e
5V Data H to L Output 0 5V to
g
0 2V
30
IV
ns
OS
Overshoot
VSR
e
1V Data L to H or H to L
b
300
300
I
mV
VSR
e
1V OE H to L Data
e
L R
L
to 5V
b
300
300
I
mV
VSR
e
1V OE H to L Data
e
H R
L
to 0V
b
300
300
I
mV
T
pda
Propagation Delay
VSR
e
2 5V OE H to L C
L
e
50 pF
High-Z to Active
R
L
to 5V Data
e
L Output to 3 5V
50
I
ns
R
L
to 0V Data
e
H Output to 1 5V
50
I
ns
T
pdh
Propagation Delay
VSR
e
2 5V OE L to H C
L
e
50 pF
Active to High-Z
Data
e
L R
L
to 5V Output to 0 5V
50
I
ns
Data
e
H R
L
to 0V Output to 4 5V
50
I
ns
3
TD
is
27in
TD
is
32in
EL2021C
Monolithic Pin Driver
Pin Description Table
Pin
Name
Description
1
GND
System ground
2
E
Enable control input A logic low allows normal operation a logic high puts the device into
power down mode No output levels are defined in powerdown nor does the output behave
as a high impedance
3
OE
Output Enable input A logic low sets the output to low-impedance driver mode a logic high
places the output into a high-impedance state
4
V
CL
Lower analog control input When Data
e
OE
e
E
e
L the V
CL
level is output as V
OUT
(assuming V
CL
k
V
CH
)
5
B
b
System power supply The EL2021 uses this pin as a negative output current monitor connection
Little current is drawn from this pin transient or static
6
I
sense
b
Negative output current monitor input
7
V
b
Negative power supply Because all negative output drive currents come from this pin
(as much as 60 mA transiently) good bypassing is essential
8
Drive
b
Output to external pnp transistor base
9
V
OUT
High-current input and output depending on OE
10
Drive
a
Output to external npn transistor base
11
Sense Out
Logic output which signals that a high
a
or
b
output current is flowing
12
V
a
Positive power supply Like V
b
it should be well bypassed
13
I
sense
a
Positive output current monitor input
14
B
a
System power supply similar to B
b
15
V
CH
Higher analog control input When Data
e
H and OE
e
E
e
L the V
CH
level is output as
V
OUT
(assuming V
CH
l
V
CL
)
16
VSR
Slew rate control input A 1V level on this pin causes the output to slew at 100 V
ms 0 5V
causes a slew rate of 50 V
ms etc
17
Data
Output level control input This pin digitally selects V
CL
or V
CH
as the output voltage
when OE
e
E
e
L
18
N C
Not Connected
4
EL2021C
Monolithic Pin Driver
Typical Performance Curves
2021 3
Family of output waveshapes
ECL TTL CMOS HCMOS
with C1 e 50 pF VSR e 1V
2021 4
Family of output waveshapes
ECL TTL CMOS HCMOS
with C1 e 200 pF VSR e 1V
2021 5
Output waveshapes with
5 MHz data rate C1 e 50 pF
VSR e 4V
2021 6
Family of output waveshapes
ECL TTL CMOS HCMOS
with C1 e 200 pF VSR e 1V
and overcompensated with
22 pF from each drive pin
to ground
2021 7
Family of output waveshapes
from active H L to
high-impedance H L
2021 8
Family of output waveshapes
from high-impedance H L
to active H L
2021 9
Family of a output edges
0V to 5V for VSR e 0 5V 1V
2V 3V 5V
2021 10
Family of
output edges
5V to 0V or VSR e 0 5V 1V
2V 3V 5V
5
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