1 of 11

080499

FEATURES

Integrated NV SRAM, real time clock,
crystal, power fail control circuit and lithium
energy source

Standard JEDEC bytewide 2K x 8 static RAM
pinout

Clock registers are accessed identically to the
static RAM. These registers are resident in the
eight top RAM locations

Totally nonvolatile with over 10 years of
operation in the absence of power

Access times of 70 ns and 100 ns

Quartz accuracy ±1 minute a month @ 25°C,
factory calibrated

BCD coded year, month, date, day, hours,
minutes, and seconds with leap year
compensation valid up to 2100

Power-fail write protection allows for ±10%
V

power supply tolerance

Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time

PIN ASSIGNMENT

PIN DESCRIPTION

A0-A10

- Address Input

- Chip Enable

- Output Enable

- Write Enable

- +5 Volts

GND

- Ground

DQ0-DQ7

- Data Input/Output

ORDERING INFORMATION

DS1642-70

70 ns access

DS1642-100 100 ns access

DESCRIPTION

The DS1642 is a 2K x 8 nonvolatile static RAM and a full-function real time clock which are both
accessible in a bytewide format. The nonvolatile time keeping RAM is pin- and function-equivalent to
any JEDEC standard 2K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and
EEPROM sockets, providing read/write nonvolatility and the addition of the real time clock function. The
real time clock information resides in the eight uppermost RAM locations. The RTC registers contain
year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day
of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid
access of incorrect data that can occur during clock update cycles. The double-buffered system also

DS1642

Nonvolatile Timekeeping RAM

www.dalsemi.com

A10

A4
A3

DQ0

DQ1

DQ2

GND

DQ7

DQ6

DQ5

DQ4

DQ3

4
5

DS1642

2 of 11

prevents time loss as the timekeeping countdown continues unabated by access to time register data. The
DS1642 also contains its own power-fail circuitry which deselects the device when the V

supply is in

an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation
brought on by low V

as errant access and update cycles are avoided.

CLOCK OPERATIONS-READING THE CLOCK

While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1642 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1642 registers are updated simultaneously after the clock
status is reset. Updating is within a second after the read bit is written to 0.

DS1642 BLOCK DIAGRAM Figure 1

DS1642 TRUTH TABLE Table 1

MODE

POWER

DESELECT

HIGH Z

STANDBY

WRITE

DATA IN

ACTIVE

READ

DATA OUT

ACTIVE

5 VOLTS ± 10%

READ

HIGH Z

ACTIVE

<4.5 VOLTS >V

BAT

DESELECT

HIGH Z

CMOS STANDBY

BAT

DESELECT

HIGH Z

DATA RETENTION

MODE

DS1642

3 of 11

SETTING THE CLOCK

The 8th bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts
updates to the DS1642 registers. The user can then load them with the correct day, date and time data in
24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters
and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The

OSC

bit is the MSB for the seconds registers. Setting it to

a 1 stops the oscillator.

FREQUENCY TEST BIT

Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid
(i.e.,

low, and

low) and address for seconds register remain valid and stable.

CLOCK ACCURACY

The DS1642 is guaranteed to keep time accuracy to within

1 minute per month at 25

C. The clock is

calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements.
The DS1642 does not require additional calibration and temperature deviations will have a negligible
effect in most applications. For this reason, methods of field clock calibration are not available and not
necessary.

DS1642 REGISTER MAP BANK1 Table 2

DATA

ADDRESS

FUNCTION

7FF

YEAR

00-99

7FE

MONTH

01-12

7FD

DATE

01-31

7FC

DAY

00-23

7FB

HOUR

00-59

7FA

MINUTES

00-59

7F9

OSC

SECONDS

00-59

7F8

CONTROL

OSC

= STOP BIT

R = READ BIT

FT = FREQUENCY TEST

W = WRITE BIT

X = UNUSED

NOTE:

All indicated "X" bits are not dedicated to any particular function and can be used as normal RAM bits.

DS1642

4 of 11

RETRIEVING DATA FROM RAM OR CLOCK

The DS1642 is in the read mode whenever

(write enable) is high, and

(chip enable) is low. The

device architecture allows ripplethrough access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t

after the last address input is stable, providing that the

and

access times and states are satisfied. If

access times are not met, valid data will be

available at the latter of chip enable access (t

CEA

) or at output enable access time (t

OEA

). The state of the

data input/output pins (DQ) is controlled by

and

. If the outputs are activated before t

, the data

lines are driven to an intermediate state until t

. If the address inputs are changed while

and

remain valid, output data will remain valid for output data hold time (t

) but will then go indeterminate

until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1642 is in the write mode whenever

and

are in their active state. The start of a write is

referenced to the latter occurring transition of

. The addresses must be held valid throughout

the cycle.

must return inactive for a minimum of t

prior to the initiation of another read or

write cycle. Data in must be valid t

prior to the end of write and remain valid for t

afterward. In a

typical application, the

signal will be high during a write cycle. However,

can be active provided

that care is taken with the data bus to avoid bus contention. If

is low prior to

transitioning low

the data bus can become active with read data defined by the address inputs. A low transition on

will

then disable the outputs t

WEZ

after

goes active.

DATA RETENTION MODE

When V

is within nominal limits (V

> 4.5 volts) the DS1642 can be accessed as described above by

read or write cycles. However, when V

is below the power-fail point V

(point at which write

protection occurs) the internal clock registers and RAM is blocked from access. This is accomplished
internally by inhibiting access via the

signal. When V

falls below the level of the internal battery

supply, power input is switched from the V

pin to the internal battery and clock activity, RAM, and

clock data are maintained from the battery until V

is returned to nominal level.

BATTERY LONGEVITY

The DS1642 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the V

supply is not present. The capability of this internal power supply

is sufficient to power the DS1642 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25

C with the internal clock oscillator running in

the absence of V

power. Each DS1642 is shipped from Dallas Semiconductor with its lithium energy

source disconnected, guaranteeing full energy capacity. When V

is first applied at a level greater than

, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the

DS1642 will be much longer than 10 years since no lithium battery energy is consumed when V

present.

DS1642

5 of 11

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground

0.3V to +7.0V

Operating Temperature

C to 70

Storage Temperature

C to +70

Soldering Temperature

260

C for 10 seconds (See Note 6)

* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

(0°C to 70°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Logic 1 Voltage All Inputs

2.2

+0.3

Logic 0 Voltage All Inputs

-0.3

0.8

DC ELECTRICAL CHARACTERISTICS

(0°C < t

< 70°C; V

(MAX) < V

< V

(MIN)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Active Supply Current

2, 3

TTL Standby Current
(

= V

)

CC1

2, 3

CMOS Standby Current
(

< V

-0.2V)

CC2

2, 3

Input Leakage Current
(any input)

-1

µA

I/O Leakage Current
(any output)

-1

µA

Output Logic 1 Voltage
(I

OUT

= -1.0 mA)

2.4

Output Logic 0 Voltage
(I

OUT

= +2.1 mA)

0.4

Write Protection Voltage

4.25

4.37

4.50

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DS1642

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DS1642