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Электронный компонент: Z9972

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3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Z9972
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07088 Rev. *D
Revised December 21, 2002
Features
Output frequency up to 125 MHz
12 clock outputs: frequency configurable
350 ps max output-to-output skew
Configurable output disable
Two reference clock inputs for dynamic toggling
Oscillator or crystal reference input
Spread Spectrum-compatible
Glitch-free output clocks transitioning
3.3V power supply
Pin-compatible with MPC972
Industrial temperature range: 40C to +85C
52-pin TQFP package
Table 1. Frequency Table
[1]
VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0
F
VCO
0
0
0
0
8x
0
0
0
1
12x
0
0
1
0
16x
0
0
1
1
20x
0
1
0
0
16x
0
1
0
1
24x
0
1
1
0
32x
0
1
1
1
40x
1
0
0
0
4x
1
0
0
1
6x
1
0
1
0
8x
1
0
1
1
10x
1
1
0
0
8x
1
1
0
1
12x
1
1
1
0
16x
1
1
1
1
20x
Note:
1.
x = the reference input frequency, 200 MHz < F
VCO
< 480 MHz.
Block Diagram
Pin Configuration
REF_SEL
0
1
0
1
Phase
Detector
VCO
LPF
Sync
Frz
D Q
QA0
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
0
1
/2
Power-On
Reset
Output Disable
Circuitry
Data Generator
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
XIN
XOUT
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
SCLK
SDATA
INV_CLK
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
12
VCO_SEL
PLL_EN
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
XIN
XOUT
VDD
F
B
_
SEL
1
SYNC
VS
S
QC
0
VDD
C
QC
1
SEL
C0
SEL
C1
QC
2
VDD
C
QC
3
VS
S
IN
V
_
C
L
K
SE
L
B
1
SE
L
B
0
SE
L
A
1
SE
L
A
0
QA
3
VDD
C
QA
2
VS
S
QA
1
VDD
C
QA
0
VS
S
VC
O
_
SE
L
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
Z9972
Z9972
Document #: 38-07088 Rev. *D
Page 2 of 9
Pin Descriptions
Pin
Name
PWR
I/O
Type
Description
11
XIN
I
Oscillator Input. Connect to a crystal.
12
XOUT
O
Oscillator Output. Connect to a crystal.
9
TCLK0
I
PU
External Reference/Test Clock Input.
10
TCLK1
I
PU
External Reference/Test Clock Input.
44, 46, 48, 50
QA(3:0)
VDDC
O
Clock Outputs. See Table 2 for frequency selections.
32, 34, 36, 38
QB(3:0)
VDDC
O
Clock Outputs. See Table 2 for frequency selections.
16, 18, 21, 23
QC(3:0)
VDDC
O
Clock Outputs. See Table 2 for frequency selections.
29
FB_OUT
VDDC
O
Feedback Clock Output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass
delay capacitor at this output will control Input Reference/ Output Banks
phase relationships.
25
SYNC
VDDC
O
Synchronous Pulse Output. This output is used for system synchroni-
zation. The rising edge of the output pulse is in sync with both the rising
edges of QA (0:3) and QC(0:3) output clocks regardless of the divider
ratios selected.
42, 43
SELA(1,0)
I
PU
Frequency Select Inputs. These inputs select the divider ratio at QA(0:3)
outputs. See Table 2.
40, 41
SELB(1,0)
I
PU
Frequency Select Inputs. These inputs select the divider ratio at QB(0:3)
outputs. See Table 2.
19, 20
SELC(1,0)
I
PU
Frequency Select Inputs. These inputs select the divider ratio at QC(0:3)
outputs. See Table 2.
5, 26, 27
FB_SEL(2:0)
I
PU
Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See Table 2.
52
VCO_SEL
I
PU
VCO Divider Select Input. When set LOW, the VCO output is divided by
2. When set HIGH, the divider is bypassed. See Table 1.
31
FB_IN
I
PU
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
6
PLL_EN
I
PU
PLL Enable Input. When asserted HIGH, PLL is enabled. And when
LOW, the phase-lock loop (PLL) is bypassed.
7
REF_SEL
I
PU
Reference Select Input. When HIGH, the crystal oscillator is selected.
And when LOW, TCLK (0,1) is the reference clock.
8
TCLK_SEL
I
PU
TCLK Select Input. When LOW, TCLK0 is selected and when HIGH
TCLK1 is selected.
2
MR#/OE
I
PU
Master Reset/Output Enable Input. When asserted LOW, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
HIGH, releases the internal flip-flops from reset and enables all of the
outputs.
14
INV_CLK
I
PU
Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted.
When set LOW, the inverter is bypassed.
3
SCLK
I
PU
Serial Clock Input. Clocks data at SDATA into the internal register.
4
SDATA
I
PU
Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
17, 22, 28,
33,37, 45, 49
VDDC
[2]
3.3V Power Supply for Output Clock Buffers.
13
VDD
[2]
3.3V Supply for PLL.
1, 15, 24, 30,
35, 39, 47, 51
VSS
Common Ground.
Note:
2.
A bypass capacitor (0.1
F) should be placed as close as possible to each positive power (< 0.2"). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Z9972
Document #: 38-07088 Rev. *D
Page 3 of 9
Description
The Z9972 has an integrated PLL that provides low-skew and
low-jitter clock outputs for high-performance microprocessors.
Three independent banks of four outputs as well as an
independent PLL feedback output, FB_OUT, provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 480 MHz. This allows a wide range
of output frequencies up to125 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select
inputs (see Table 1). The VCO frequency is then divided to
provide the required output frequencies. These dividers are
set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see
Table 2). For situations in which the VCO needs to run at
relatively low frequencies and therefore might not be stable,
assert VCO_SEL LOW to divide the VCO frequency by 2. This
will maintain the desired output relationships, but will provide
an enhanced PLL lock range.
The Z9972 is also capable of providing inverted output clocks.
When INV_CLK is asserted HIGH, QC2 and QC3 output
clocks are inverted. These clocks could be used as feedback
outputs to the Z9972 or a second PLL device to generate early
or late clocks for a specific design. This inversion does not
affect the output-to-output skew.
Glitch-Free Output Frequency Transitions
Customarily when output buffers have their internal counter's
changed "on the fly' their output clock periods will:
1. contain short or "runt" clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the
old or new frequency to which they are being transitioned.
2. contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old
or new frequency to which they are being transitioned.
This device specifically includes logic to guarantee that runt
and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed "on the fly"
while it is operating: SELA, SELB, SELC, and VCO_SEL.
SYNC Output
[3]
In situations where output frequency relationships are not
integer multiples of each other the SYNC output provides a
signal for system synchronization. The Z9972 monitors the
relationship between the QA and the QC output clocks. It
provides a low going pulse, one period in duration, one period
prior to the coincident rising edges of the QA and QC outputs.
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. The following
timing diagram illustrates various waveforms for the SYNC
output.
Note:.
3.
The SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be
used as a synchronizing signal.
Table 2. Frequency Select Inputs
VCO_SEL
SELA1
SELA0
QA
SELB1
SELB0
QB
SELC1
SELC0
QC
0
0
0
VCO/8
0
0
VCO/8
0
0
VCO/4
0
0
1
VCO/12
0
1
VCO/12
0
1
VCO/8
0
1
0
VCO/16
1
0
VCO/16
1
0
VCO/12
0
1
1
VCO/24
1
1
VCO/20
1
1
VCO/16
1
0
0
VCO/4
0
0
VCO/4
0
0
VCO/2
1
0
1
VCO/6
0
1
VCO/6
0
1
VCO/4
1
1
0
VCO/8
1
0
VCO/8
1
0
VCO/6
1
1
1
VCO/12
1
1
VCO/10
1
1
VCO/8
Z9972
Document #: 38-07088 Rev. *D
Page 4 of 9
SYNC
QC
QA
SYNC
QC
QA
SYNC
QA
QC
SYNC
QC
QA
SYNC
QA
QC
SYNC
QC
QA
SYNC
QC
QA
VCO
1:1 Mode
2:1 Mode
3:1 Mode
3:2 Mode
4:1 Mode
4:3 Mode
6:1 Mode
Figure 1. Sync Output Waveforms
Z9972
Document #: 38-07088 Rev. *D
Page 5 of 9
Power Management
The individual output enable/freeze control of the Z9972
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic
"0" state when the freeze control bits are activated. The serial
input register contains one programmable freeze enable bit for
12 of the 14 output clocks. The QC0 and FB_OUT outputs can
not be frozen with the serial port, this avoids any potential lock
up situation should an error occur in the loading of the serial
data. An output is frozen when a logic "0" is programmed and
enabled when a logic "1" is written. The enabling and freezing
of individual outputs is done in such a manner as to eliminate
the possibility of partial "runt" clocks.
The serial input register is programmed through the SDATA
input by writing a logic "0" start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equals the period of
the free running SCLK signal. The SDATA is sampled on the
rising edge of SCLK.
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Start
Bit
Figure 2. SDATA Input Register