Frequency-multiplying, Peak-reducing
EMI Solution
W530-02
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07190 Rev. *A
Revised January 7, 2003
Features
Cypress PREMISTM SMARTSPREADTM family offering
Generates an electromagnetic-interference
(EMI)-optimized clocking signal at the output
Selectable frequency range and multiplication factor
Single 1.25%, 2.5%, 5%, or 10%, down or center spread
output
Integrated loop filter components
Operates with a 3.3V or 5V supply
Low-power CMOS design
Higher drive strength, higher frequency support than
W530
Available in 20-pin SSOP
Key Specifications
Supply Voltages:....................................... V
DD
= 3.3V 0.3V
or V
DD
= 5V 10%
Frequency Range:......................... 13 MHz
F
out
166 MHz
Cycle to Cycle Jitter: ........................................ 250 ps (max.)
Output Duty Cycle: ............................... 40/60% (worst case)
Table 1. Output Frequency Range Selection
OR
2
OR
1
Output Range
(Multiplication Factor Selection)
0
0
reserved
0
1
13 MHz
F
OUT
30 MHz
1
0
25 MHz
F
OUT
60 MHz
1
1
50 MHz
F
OUT
166 MHz
Table 2. Modulation Width Selection
MW2
MW1
MW0
Output
0
0
0
F
in
F
out
F
in
1.25%
0
0
1
F
avg
+
0.625%
F
out
F
avg
0.625%
0
1
0
F
in
F
out
F
in
2.5%
0
1
1
F
avg
+
1.25%
F
out
F
avg
1.25%
1
0
0
F
in
F
out
F
in
5%
1
0
1
F
avg
+
2.5%
F
out
F
avg
2.5%
1
1
0
F
in
F
out
F
in
10%
1
1
1
F
avg
+
5%
F
out
F
avg
5%
Table 3. Input Frequency Range Selection
IR2
IR1
Input Range
0
0
reserved
0
1
13 MHz
F
IN
30 MHz
1
0
25 MHz
F
IN
60 MHz
1
1
50 MHz
F
IN
166 MHz
W530-02
Document #: 38-07190 Rev. *A
Page 2 of 8
Overview
The W530-02 product is one of a series of devices in the
Cypress PREMIS family. The PREMIS family incorporates the
latest advances in phase-locked loop (PLL) spread spectrum
frequency synthesizer techniques. By frequency modulating
the output with a low frequency carrier, peak EMI is greatly
reduced. Use of this technology allows systems to pass
increasingly difficult EMI testing without resorting to costly
shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The
Simplified Block Diagram on page 1 shows a simple imple-
mentation.
Note:
1.
Pins that are marked with [*] have internal pull-up resistors. Pins that are marked with [^] have internal pull-down resistors.
W
530
-02
20
19
18
17
1
2
3
4
X1
X2
AVDD
MW0^
REFOUT
VDD
GND
IR1*
5
6
7
14
15
16
IR2*
SSOUT
MW1*
STOP^
OR1^
NC
8
9
10
11
12
13
VDD
MW2^
OR2*
SSON#
GND
GND
Simplified Block Diagram
Pin Configuration
[1]
SSOP
Spread Spectrum
W530-02
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Spread Spectrum
W530-02
(EMI suppressed)
3.3V or 5.0V
XTAL
X1
X2
Reference Input
Input
Output
Output
X1
Pin Definitions
Pin Name
Pin No.
Pin Type
Pin Description
SSOUT
15
O
Output Modulated Frequency. Frequency modulated signal. Frequency of the output is
selected as shown in Table 1.
REFOUT
20
O
Non-modulated Output. This pin provides a copy of the reference frequency. This output
will not have the Spread Spectrum feature regardless of the state of logic input SSON#.
CLKIN or X1
1
I
Crystal Connection or External Reference Frequency Input. This pin has dual functions.
It may either be connected to an external crystal, or to an external reference clock.
NC or X2
2
I
Crystal Connection: Input connection for an external crystal. If using an external reference
signal, this pin must be left unconnected.
SSON#
10
I
Spread Spectrum Control (Active LOW). Asserting this signal (active LOW) turns the
internal modulation waveform on. This pin has an internal pull-down resistor.
MW0:2
4, 14, 11
I
Modulation Width Selection. When the Spread Spectrum feature is turned on, these pins
are used to select the amount of variation and peak EMI reduction that is desired on the
output signal (see Table 2). MW0: DOWN, MW1: UP, MW2: DOWN.
IR1:2
17,16
I
Reference Frequency Selector. The logic level provided at this input indicates to the internal
logic what range the reference frequency is in and determines the factor by which the device
multiplies the input frequency. Refer to Table 3. These pins have internal pull-up resistors.
NC
7
NC
No Connection. Leave this pin unconnected.
STOP
5
I
Output Disable. When pulled HIGH, stops all outputs at logic low voltage level. This pin has
an internal pull-down.
OR1:2
6,9
I
Output Frequency Selection Bits. These pins select the frequency of operation for the
output. Refer to Table 1. OR1: DOWN, OR2: UP.
VDD
3, 12, 19
P
Power Connection. Connected to 3.3V or 5V power supply.
GND
8, 13, 18
G
Ground Connection. Connect all ground pins to the common ground plane.
W530-02
Document #: 38-07190 Rev. *A
Page 3 of 8
The W530-02 also allows for frequency multiplication in order
to determine the relationship between the input and output
frequencies. Simply compare the min. frequency of the input
and output ranges selected (use 12.5 instead of 13 for this
calculation, though). The multiplication options are: 0.25,
0.5,1.0, 2.0, and 4.0.
Functional Description
The W530-02 uses a PLL to frequency modulate an input
clock. The result is an output clock whose frequency is slowly
swept over a narrow band near the input signal. The basic
circuit topology is shown in Figure 1. The input reference
signal is divided by Q and fed to the phase detector. A signal
from the VCO is divided by P and fed back to the phase
detector also. The PLL will force the frequency of the VCO
output signal to change until the divided output signal and the
divided reference signal match at the phase detector input.
The output frequency is then equal to the ratio of P/Q times the
reference frequency. The unique feature of the Spread
Spectrum Frequency Timing Generator is that a modulating
waveform is superimposed at the input to the VCO. This
causes the VCO output to be slowly swept across a predeter-
mined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum
process has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI
reduction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (IR1:2, OR1:2 pins), the frequency
range can be set (see Table 1 and Table 3). Spreading
percentage is set with pins MW0:2, as shown in Table 2.
A larger spreading percentage improves EMI reduction.
However, large spread percentages may either exceed
system maximum frequency ratings or lower the average
frequency to a point where performance is affected. For these
reasons, spreading percentages between 0.5% and 2.5% are
most common.
Spread Spectrum Frequency Timing Generation
The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in Figure 2. An EMI emission profile
of a clock harmonic is shown.
Contrast the typical clock EMI with the Cypress Spread
Spectrum Frequency Timing Generation EMI. Notice the spike
in the typical clock. This spike can make systems fail
quasi-peak EMI testing. The FCC and other regulatory
agencies test for peak emissions. With spread spectrum
enabled, the peak energy is much lower (at least 8 dB)
because the energy is spread out across a wider bandwidth.
Modulating Waveform
The shape of the modulating waveform is critical to EMI
reduction. The modulation scheme used to accomplish the
maximum reduction in EMI is shown in Figure 3. The period of
the modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.
Cypress frequency selection tables express the modulation
percentage in two ways. The first method displays the
spreading frequency band as a percent of the programmed
average output frequency, symmetric about the programmed
average frequency. This method is always shown using the
expression f
Center
X
MOD
% in the frequency spread selection
table.
The second approach is to specify the maximum operating
frequency and the spreading band as a percentage of this
frequency. The output signal is swept from the lower edge of
the band to the maximum frequency. The expression for this
approach is f
MAX
X
MOD
%. Whenever this expression is used,
Cypress has taken care to ensure that f
MAX
will never be
exceeded. This is important in applications where the clock
drives components with tight maximum clock speed specifica-
tions.
Freq.
Phase
Modulating
VCO
Post
CLKOUT
Detector
Charge
Pump
Waveform
Dividers
Divider
Feedback
Divider
PLL
GND
V
DD
Q
P
Clock Input
Reference Input
(EMI suppressed)
Figure 1. Conceptual Block Diagram
W530-02
Document #: 38-07190 Rev. *A
Page 4 of 8
SSON# Pin
An internal pull-down resistor defaults the chip into spread
spectrum mode. When the SSON# pin is asserted (active
LOW) the spreading feature is enabled. Spreading feature is
disabled when SSON# is set HIGH (V
DD
).
Frequency Span (MHz) Center Spread
Figure 2. Typical Clock and SSFTG Comparison
100%
60%
20%
80%
40%
0%
20%
40%
60%
80%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Time
Fr
e
que
n
c
y
S
h
if
t
Figure 3. Modulation Waveform Profile
W530-02
Document #: 38-07190 Rev. *A
Page 5 of 8
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Parameter
Description
Rating
Unit
V
DD
, V
IN
Voltage on any Pin with Respect to GND
0.5 to +7.0
V
T
STG
Storage Temperature
65 to +150
C
T
A
Operating Temperature
0 to +70
C
T
B
Ambient Temperature under Bias
55 to +125
C
P
D
Power Dissipation
0.5
W
DC Electrical Characteristics
: 0C < T
A
< 70C, V
DD
= 3.3V 0.3V
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
I
DD
Supply Current
18
32
mA
t
ON
Power-Up Time
First locked clock cycle after Power
Good
5
ms
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.4
V
V
OL
Output Low Voltage
0.4
V
V
OH
Output High Voltage
2.4
V
I
IL
Input Low Current
Note 2
100
A
I
IH
Input High Current
Note 2
10
A
I
OL
Output Low Current
@ 0.4V, V
DD
= 3.3V
15
mA
I
OH
Output High Current
@ 2.4V, V
DD
= 3.3V
15
mA
C
I
Input Capacitance
7
pF
R
P
Input Pull-Up Resistor
80
k
Z
OUT
Clock Output Impedance
25
DC Electrical Characteristics:
0C < T
A
< 70C, V
DD
= 5V 10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
I
DD
Supply Current
30
50
mA
t
ON
Power-Up Time
First locked clock cycle after
Power Good
5
ms
V
IL
Input Low Voltage
0.15V
DD
V
V
IH
Input High Voltage
0.7V
DD
V
V
OL
Output Low Voltage
0.4
V
V
OH
Output High Voltage
2.4
V
I
IL
Input Low Current
Note 2
100
A
I
IH
Input High Current
Note 2
10
A
I
OL
Output Low Current
@ 0.4V, V
DD
= 5V
24
mA
I
OH
Output High Current
@ 2.4V, V
DD
= 5V
24
mA
C
I
Input Capacitance
7
pF
R
P
Input Pull-Up Resistor
80
k
Z
OUT
Clock Output Impedance
25
Note:
2.
Inputs OR1:2 and IR1:2 have a pull-up resistor, Input SSON# has a pull-down resistor.
W530-02
Document #: 38-07190 Rev. *A
Page 6 of 8
AC Electrical Characteristics:
T
A
= 0C to +70C, V
DD
= 3.3V 0.3V
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
f
IN
Input Frequency
Input Clock
14
166
MHz
f
OUT
Output Frequency
Spread Off
13
166
MHz
t
R
Output Rise Time
V
DD
, 15-pF load, 0.8V2.4V
2
5
ns
t
F
Output Fall Time
V
DD
, 15-pF load, 2.4V0.8V
2
5
ns
t
OD
Output Duty Cycle
15-pF load
40
60
%
t
ID
Input Duty Cycle
40
60
%
t
JCYC
Jitter, Cycle-to-Cycle
250
300
ps
AC Electrical Characteristics:
T
A
= 0C to +70C, V
DD
= 5V10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
f
IN
Input Frequency
Input Clock
14
166
MHz
f
OUT
Output Frequency
Spread Off
13
166
MHz
t
R
Output Rise Time
V
DD
, 15-pF load, 0.8V2.4V
2
5
ns
t
F
Output Fall Time
V
DD
, 15-pF load, 2.4V0.8V
2
5
ns
t
OD
Output Duty Cycle
15-pF load
45
55
%
t
ID
Input Duty Cycle
40
60
%
t
JCYC
Jitter, Cycle-to-Cycle
100
200
ps
Ordering Information
Ordering Code
Package Type
Product Flow
W530-02H
20-pin Plastic SSOP (209-mil)
Commercial, 0C to 70C
W530-02HT
20-pin Plastic SSOP (209-mil) - Tape and Reel
Commercial, 0C to 70C
W530-02
Document #: 38-07190 Rev. *A
Page 7 of 8
Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Drawing and Dimension
PREMIS and SMARTSPREAD are trademarks of Cypress Semiconductor. All product and company names mentioned in this
document are the trademarks of their respective holders.
20-pin (5.3 mm) Shrunk Small Outline Package O20
51-85077-*C
W530-02
Document #: 38-07190 Rev. *A
Page 8 of 8
Document History Page
Document Title: W530-02 Frequency-multiplying, Peak-reducing EMI Solution
Document Number: 38-07190
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110591
01/07/02
DSG
Changed from Spec number: 38-01062 to 38-07190
*A
122549
01/08/03
RGL
Added a SMARTSPREADTM in the features area.
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