USE ULTRA37000TM FOR
ALL NEW DESIGNS
Flash-Erasable Reprogrammable
CMOS PAL
Device
PALCE16V8
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-03025 Rev. *A
Revised April 22, 2004
Features
Active pull-up on data input pins
Low power version (16V8L)
-- 55 mA max. commercial (10, 15, 25 ns)
-- 65 mA max. industrial (10, 15, 25 ns)
-- 65 mA military (15 and 25 ns)
Standard version has low power
-- 90 mA max. commercial (10, 15, 25 ns)
-- 115 mA max. commercial (7 ns)
-- 130 mA max. military/industrial (10, 15, 25 ns)
CMOS Flash technology for electrical erasability and
reprogrammability
PCI-compliant
User-programmable macrocell
-- Output polarity control
-- Individually selectable for registered or combina-
torial operation
Up to 16 input terms and eight outputs
7.5 ns com'l version
5 ns t
CO
5 ns t
S
7.5 ns t
PD
125-MHz state machine
10 ns military/industrial versions
7 ns t
CO
10 ns t
S
10 ns t
PD
62-MHz state machine
High reliability
-- Proven Flash technology
-- 100% programming and functional testing
Functional Description
The Cypress PALCE16V8 is a CMOS Flash Electrical
Erasable second-generation programmable array logic
device. It is implemented with the familiar sum-of-product
(AND-OR) logic structure and the programmable macrocell.
8
8
8
8
8
8
8
8
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
PROGRAMMABLE
AND ARRAY
(64 x 32)
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
GND
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
CLK/I
0
OE/I
9
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
V
CC
Logic Block Diagram (PDIP/CDIP)
Pin Configurations
PLCC/LCC
Top View
18
17
16
15
14
4
5
6
7
8
9 10111213
3 2 1
19
I
I
CLK/I
I/O
20
V
CC
OE/I
I/O
I/O
CLK/I
0
I
1
I
2
I
3
I
4
I
8
GND
OE/I
9
V
CC
I/O
7
I/O
6
I/O
4
I/O
3
I/O
2
I/O
0
I/O
5
I
5
I
6
I
7
I/O
1
1
2
3
4
5
6
7
8
9
10
11
12
16
15
14
13
17
20
19
18
DIP
I
3
I
4
I
5
I
6
I
7
2
1
0
7
I/O
6
I/O
4
I/O
3
I/O
2
I/O
5
8
I
GND
9
0
1
Top View
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE16V8
Document #: 38-03025 Rev. *A
Page 2 of 13
Functional Description
The PALCE16V8 is executed in a 20-pin 300-mil molded DIP,
a 300-mil cerdip, a 20-lead square ceramic leadless chip
carrier, and a 20-lead square plastic leaded chip carrier.
The device provides up to 16 inputs and 8 outputs. The
PALCE16V8 can be electrically erased and reprogrammed.
The programmable macrocell enables the device to function
as a superset to the familiar 20-pin PLDs such as 16L8, 16R8,
16R6, and 16R4.
The PALCE16V8 features 8 product terms per output and 32
input terms into the AND array. The first product term in a
macrocell can be used either as an internal output enable
control or as a data product term.
There are a total of 18 architecture bits in the PALCE16V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are
selectable from either the input/output pin associated with the
macrocell, the input/output pin associated with an adjacent
pin, or from the macrocell register itself.
Power-Up Reset
All registers in the PALCE16V8 power-up to a logic LOW for
predictable system initialization. For each register, the
associated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
An electronic signature word is provided in the PALCE16V8
that consists of 64 bits of programmable memory that can
contain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the
internal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE16V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each
product term. The PTD fuses allow each product term to be
individually disabled.
Selection Guide
Generic Part Number
t
PD
ns
t
S
ns
t
CO
ns
I
CC
mA
Com'l/Ind
Mil
Com'l/Ind
Mil
Com'l/Ind
Mil
Com'l
Mil/Ind
PALCE16V8-5
5
3
4
115
PALCE16V8-7
7.5
7
5
115
PALCE16V8-10
10
10
10
10
7
10
90
130
PALCE16V8-15
15
15
12
12
10
10
90
130
PALCE16V8-25
25
25
15
20
12
12
90
130
PALCE16V8L-15
15
15
12
12
10
12
55
65
PALCE16V8L-25
25
25
15
20
12
20
55
65
Shaded areas contain preliminary information.
Configuration Table
CG
0
CG
1
CL0
x
Cell Configuration
Devices Emulated
0
1
0
Registered Output
Registered Med PALs
0
1
1
Combinatorial I/O
Registered Med PALs
1
0
0
Combinatorial Output
Small PALs
1
0
1
Input
Small PALs
1
1
1
Combinatorial I/O
16L8 only
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE16V8
Document #: 38-03025 Rev. *A
Page 3 of 13
Macrocell
Q
Q
D
CLK
1
1
0
0
1
X
CL1
x
0
1
X
0
1 1
I/O
x
From
Adjacent
Pin
CL0
x
CG
1
for pin 13 to 18
CG
0
for pin 12 and 19
1
0
0
1
1 1
0 0
0
1
X
0
1 1
OE
V
CC
To
Adjacent
Macrocell
CL0
x
CG
1
V
CC
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE16V8
Document #: 38-03025 Rev. *A
Page 4 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................65
C to +150
C
Ambient Temperature with
Power Applied.............................................55
C to +125
C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State ............................................... 0.5V to +7.0V
DC Input Voltage ............................................0.5V to +7.0V
Output Current into Outputs (LOW)............................. 24 mA
DC Programming Voltage............................................. 12.5V
Latch-Up Current .................................................... > 200 mA
Operating Range
Range
Ambient Temperature
V
CC
Commercial
0
C to +75
C 5V
5%
Military
[1]
55
C to +125
C 5V
10%
Industrial
40
C to +85
C
5V
10%
Electrical Characteristics
Over the Operating Range
[2]
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.,
V
IN
= V
IH
or V
IL
I
OH
= 3.2 mA
Com'l
2.4
V
I
OH
= 2 mA
Mil/Ind
V
OL
Output LOW Voltage
V
CC
= Min.,
V
IN
= V
IH
or V
IL
I
OL
= 24 mA
Com'l
0.5
V
I
OL
= 12 mA
Mil/Ind
V
IH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
[3]
2.0
V
V
IL
[4]
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs
[3]
0.5
0.8
V
I
IH
Input or I/O HIGH Leakage
Current
3.5V < V
IN
< V
CC
10
A
I
IL
[5]
Input or I/O LOW Leakage
Current
0V < V
IN
< V
IN
(Max.)
100
A
I
SC
Output Short Circuit Current V
CC
= Max., V
OUT
= 0.5V
[6, 7]
30
150
mA
I
CC
Operating Power Supply
Current
V
CC
= Max.,
V
IL
= 0V, V
IH
= 3V,
Output Open,
f = 15 MHz
(counter)
5, 7 ns
Com'l
115
mA
10, 15, 25 ns
90
mA
15L, 25L ns
55
mA
10, 15, 25 ns
Mil/Ind
130
mA
15L, 25L ns
Mil.
65
mA
15L, 25L ns
Ind.
65
mA
Capacitance
[7]
Parameter
Description
Test Conditions
Typ.
Unit
C
IN
Input Capacitance
V
IN
= 2.0V @ f = 1 MHz
5
pF
C
OUT
Output Capacitance
V
OUT
= 2.0V @ f = 1 MHz
5
pF
Endurance Characteristics
[7]
Parameter
Description
Test Conditions
Min.
Max.
Unit
N
Minimum Reprogramming Cycles
Normal Programming Conditions
100
Cycles
Notes:
1. T
A
is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. V
IL
(Min.) is equal to 3.0V for pulse durations less than 20 ns.
5. The leakage current is due to the internal pull-up resistor on all pins.
6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
7. Tested initially and after any design or process changes that may affect these parameters.
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE16V8
Document #: 38-03025 Rev. *A
Page 5 of 13
AC Test Loads and Waveforms
Specification
S
1
C
L
Commercial
Military
Measured Output Value
R
1
R
2
R
1
R
2
t
PD
, t
CO
Closed
50 pF
200
390
390
750
1.5V
t
PZX
, t
EA
Z
H: Open
Z
L: Closed
1.5V
t
PXZ
, t
ER
H
Z: Open
L
Z: Closed
5 pF
H
Z: V
OH
0.5V
L
Z: V
OL
+ 0.5V
Commercial and Industrial Switching Characteristics
[2]
Parameter
Description
16V8-5
16V8-7
16V8-10
16V8-15
16V8-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
t
PD
Input to Output
Propagation Delay
[8, 9]
1
5
3
7.5
3
10
3
15
3
25
ns
t
PZX
OE to Output Enable
1
6
6
10
15
20
ns
t
PXZ
OE to Output Disable
1
5
6
10
15
20
ns
t
EA
Input to Output
Enable Delay
[7]
1
6
9
10
15
25
ns
t
ER
Input to Output
Disable Delay
[7, 10]
1
5
9
10
15
25
ns
t
CO
Clock to Output Delay
[8, 9]
1
4
2
5
2
7
2
10
2
12
ns
t
S
Input or Feedback
Set-up Time
3
5
7.5
12
15
ns
t
H
Input Hold Time
0
0
0
0
0
ns
t
P
External Clock
Period (t
CO
+ t
S
)
7
10
14.5
22
27
ns
Shaded areas contain preliminary information.
Notes:
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. This specification is guaranteed for all device outputs changing state in a given access cycle.
10. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH
level has fallen to 0.5 volts below V
OH
min. or a previous LOW level has risen to 0.5 volts above V
OL
max.
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f
MAX
internal (1/f
MAX3
) as measured (see Note 7 above) minus t
S
.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
< 2 ns
< 2 ns
OUTPUT
R2
R1
C
L
S1
5V
TEST POINT
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