Universal Synchronous EPLD
CY7C335
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-03017 Rev. **
Revised March 26, 1997
Features
100-MHz output registered operation
Twelve I/O macrocells, each having:
-- Registered, three-state I/O pins
-- Input and output register clock select multiplexer
-- Feed back multiplexer
-- Output enable (OE) multiplexer
Bypass on input and output registers
All twelve macrocell state registers can be hidden
User configurable I/O macrocells to implement JK or
RS flip-flops and T or D registers
Input multiplexer per pair of I/O macrocells allows I/O
pin associated with a hidden macrocell state register to
be saved for use as an input
Four dedicated hidden registers
Twelve dedicated registered inputs with individually
programmable bypass option
Three separate clocks--two input clocks, two output
clocks
Common (pin 14-controlled) or product term-controlled
output enable for each I/O pin
256 product terms--32 per pair of macrocells, variable
distribution
Global, synchronous, product term-controlled, state
register set and reset--inputs to product term are
clocked by input clock
-- 2-ns input set-up and 9-ns output register clock to
output
-- 10-ns input register clock to state register clock
28-pin, 300-mil DIP, LCC, PLCC
Erasable and reprogrammable
Programmable security bit
Functional Description
The CY7C335 is a high-performance, erasable, programma-
ble logic device (EPLD) whose architecture has been opti-
mized to enable the user to easily and efficiently construct very
high performance state machines.
The architecture of the CY7C335, consisting of the user-con-
figurable output macrocell, bidirectional I/O capability, input
registers, and three separate clocks, enables the user to de-
sign high-performance state machines that can communicate
either with each other or with microprocessors over bidirec-
tional parallel buses of user-definable widths.
The four clocks permit independent, synchronous state ma-
chines to be synchronized to each other.
The user-configurable macrocells enable the designer to des-
ignate JK-, RS-, T-, or D-type devices so that the number of
product terms required to implement the logic is minimized.
The CY7C335 is available in a wide variety of packages includ-
ing 28-pin, 300-mil plastic and ceramic DIPs, PLCCs, and
LCCs.
Logic Block Diagram
C3351
14
13
12
11
10
9
7
6
5
4
3
2
1
8
15
16
17
18
19
20
23
24
25
26
27
28
22
21
V
SS
V
CC
PROGRAMMABLE AND ARRAY
(258x68)
17
11
15
13
19
9
11
17
9
19
13
15
13
17
11
19
I/O
11
I/O
10
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
V
SS
I
5
OE/I
11
I
10
I
9
I
8
I
7
I
6
I
4
I
3
I
2
I
1
/CLK3
I
0
/CLK2
CLK1
NO
DE
4
3
NO
DE
4
2
NO
DE
4
1
CY7C335
Document #: 38-03017 Rev. **
Page 2 of 18
Architecture Configuration Bits
The architecture configuration bits are used to program the
multiplexers. The function of the architecture bits is outlined in
Table 1.
Pin Configurations
10
Top View
PLCC
LCC
Top View
5
6
7
8
9
10
11
4 3 2
282726
12131415161718
25
24
23
22
21
20
19
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
2827 26
I
I
I/O
I/O
0
1
9
8
I/O
I/O
I
I
1
1
CL
K1
C3352
C3353
2
1
/CLK
3
I 0
/CLK
2
I/O
2
I
I
I/O
I/O
0
1
CL
k1
2
1
/CLK
3
I 0
/CLK
2
I/O
2
I
3
I
4
I
5
I
6
I
7
I
8
V
SS
I
3
I
4
I
5
I
6
I
7
I
8
V
SS
I/O
3
I/O
4
I/O
5
V
CC
V
SS
I/O
6
I/O
7
I/O
3
I/O
4
I/O
5
V
CC
V
SS
I/O
6
I/O
7
10
I/O
11
I/O
11
OE
/I
9
10
9
8
I/O
I/O
I
I
10
I/O
11
I/O
11
OE
/I
9
Selection Guide
CY7C335100
CY7C33583
CY7C33566
CY7C33550
Maximum Operating
Frequency (MHz)
Commercial
100
83.3
66.6
50
Military
83.3
66.6
50
I
CC1
(mA)
Commercial
140
140
140
140
Military
160
160
160
Table 1. Architecture Configuration Bits
Architecture
Configuration Bit
Number of Bits
Value
Function
C0
Output Enable
Select MUX
12 Bits, 1 Per
I/O Macrocell
0--Virgin State
Output Enable Controlled by Product Term
1--Programmed
Output Enable Controlled by Pin 14
C1
State Register
Feed Back MUX
12 Bits, 1 Per
I/O Macrocell
0--Virgin State
State Register Output is Fed Back to Input Array
1--Programmed
I/O Macrocell is Configured as an Input and
Output of Input Path is Fed to Array
C2
I/O Macrocell
Input Register
Clock Select
MUX
12 Bits, 1 Per
I/O Macrocell
0--Virgin State
ICLK1 Controls the Input Register I/O Macrocell
Input Register Clock Input
1--Programmed
ICLK2 Controls the Input Register I/O Macrocell
Input Register Clock Input
C3
Input Register
Bypass MUX--
I/O Macrocell
12 Bits, 1 Per
I/O Macrocell
0--Virgin State
Selects Input to Feedback MUX from Input
Register
1--Programmed
Selects Input to Feedback MUX from I/O pin
C4
Output Register
Bypass MUX
12 Bits, 1 Per
I/O Macrocell
0--Virgin State
Selects Output from the State Register
1--Programmed
Selects Output from the Array, Bypassing the
State Register
C5
State Clock MUX
16 Bits, 1 Per I/O
Macrocell and 1 Per
Hidden Macrocell
0--Virgin State
State Clock 1 Controls the State Register
1--Programmed
State Clock 2 Controls the State Register
CY7C335
Document #: 38-03017 Rev. **
Page 3 of 18
C6
Dedicated Input
Register Clock
Select MUX
12 Bits, 1 Per
Dedicated Input
Cell
0--Virgin State
ICLK1 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
1--Programmed
ICLK2 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
C7
Input Register
Bypass MUX--
Input Cell
12 Bits, 1 Per
Dedicated Input
Cell
0--Virgin State
Selects Input to Array from Input Register
1--Programmed
Selects Input to Array from Input Pin
C8
ICLK2 Select
MUX
1 Bit
0--Virgin State
Input Clock 2 Controlled by Pin 2
1--Programmed
Input Clock 2 Controlled by Pin 3
C9
ICLK1 Select
MUX
1 Bit
0--Virgin State
Input Clock 1 Controlled by Pin 2
1--Programmed
Input Clock 1 Controlled by Pin 1
C10
SCLK2 Select
MUX
1 Bit
0--Virgin State
State Clock 2 Grounded
1--Programmed
State Clock 2 Controlled by Pin 3
CX
(1116)
I/O Macrocell
Pair Input
Select MUX
6 Bits, 1 Per
I/O Macrocell
Pair
0--Virgin State
Selects Data from I/O Macrocell Input Path of
Macrocell A of Macrocell Pair
1--Programmed
Selects Data from I/O Macrocell Input Path of
Macrocell B of Macrocell Pair
Table 1. Architecture Configuration Bits (continued)
Architecture
Configuration Bit
Number of Bits
Value
Function
Figure 1. CY7C335 Input Macrocell
C3354
ICLK1
ICLK2
Q
D
C6
1
0
INPUTREGISTER
INPUT
CLOCK
MUX
TO ARRAY
INPUT
PIN
C7
1
0
INPUT
REG
BYPASS
MUX
CY7C335
Document #: 38-03017 Rev. **
Page 4 of 18
Figure 2. CY7C335 Input/Output Macrocell
PIN 14: OE
C0
OUTPUT
ENABLE
MUX
1
0
I/O
PIN
S
Q
D
Q
R
C1
1
0
OUTPUT REG
BYPASS MUX
FEED
BACK
MUX
TO ARRAY
C3355
OUTPUT ENABLE PRODUCT TERM
SET PRODUCT TERM
C4
1
0
EX OR PRODUCT TERM
RESET PRODUCT TERM
C5
1
0
STATE
CLK
MUX
SCLK1
SCLK2
C2
1
0
INPUT
CLOCK
MUX
ICLK1
ICLK2
C3
1
0
INPUT
REG
BYPASS
MUX
Q
D
INPUT REGISTER
CX (11 16)
1
0
SHARED
INPUT
MUX
TO ARRAY
FROM ADJACENT MACROCELL
CY7C335
Document #: 38-03017 Rev. **
Page 5 of 18
Figure 3. CY7C335 Hidden Macrocell
S
Q
D
Q
R
TO ARRAY
SET PRODUCT TERM
RESET PRODUCT TERM
1
0
STATE
CLK
MUX
SCLK1
SCLK2
C5
C3356
Figure 4. CY7C335 Input Clocking Scheme
C3357
0
1
0
1
ICLK1 ICLK2
SCLK2 TO OUTPUT MACROCELLS AND HIDDEN MACROCELLS
SCLK1 TO OUTPUT MACROCELLS AND HIDDEN
0
1
C9
1
0
C8
0
1
0
1
0
1
C10
PIN 1
PIN 2
PIN 3
MUX
MUX
MUX
MUX
MUX
MUX
MUX
TO ARRAY
TO ARRAY
MACROCELLS
PDF 
ZIP