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PRELIMINARY
1M x 4 Static RAM
CY7C1046BV33
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05170 Rev. **
Revised September 21, 2001
046BV33
Features
High speed
-- t
AA
= 10 ns
Low active power for 10 ns speed
-- 540 mW (max.)
Low CMOS standby power (L version)
-- 1.8 mW (max.)
2.0V Data Retention (400
W at 2.0V retention)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
The CY7C1046BV33 is a high-performance CMOS static
RAM organized as 1,048,576 words by 4 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. Writ-
ing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the four I/O pins
(I/O
0
through I/O
3
) is then written into the location specified on
the address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The four input/output pins (I/O
0
through I/O
3
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1046BV33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolution-
ary) pinout.
14
15
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DE
CODER
SE
NSE A
M
P
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
1M x 4
ARRAY
I/O
3
I/O
2
A
0
A
11
A
13
A
12
A
CE
A
A
16
A
17
1
2
3
4
5
6
7
8
9
10
12
21
22
25
24
23
28
27
26
Top View
SOJ
11
29
32
31
30
14
13
19
20
GND
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
WE
V
CC
A
18
A
15
A
12
A
14
I/O
2
1046BV331
A
9
A
0
I/O
0
I/O
1
OE
A
17
A
16
A
13
CE
1046BV332
A
9
A
18
16
15
17
18
GND
I/O
3
V
CC
A
10
A
11
A
19
NC
A
10
A
19
Selection Guide
7C1046BV33-10
7C1046BV33-12
7C1046BV33-15
Maximum Access Time (ns)
10
12
15
Maximum Operating Current (mA)
150
140
130
Maximum CMOS Standby
Current (mA)
Com'l
8
8
8
L version
0.5
0.5
0.5
Shaded areas contain advance information.
CY7C1046BV33
PRELIMINARY
Document #: 38-05170 Rev. **
Page 2 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage on V
CC
to Relative GND
[1]
.... 0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial
0
C to +70
C
3.0V - 3.6V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
7C1046BV33-10
7C1046BV33-12
7C1046BV33-15
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage V
CC
= Min., I
OH
= 4.0 mA
2.4
2.4
2.4
V
V
OL
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.5
2.2
V
CC
+ 0.5
2.2
V
CC
+ 0.5
V
V
IL
Input LOW Voltage
[1]
0.5
0.8
0.5
0.8
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
1
+1
A
I
OZ
Output Leakage
Current
GND < V
OUT
< V
CC
,
Output Disabled
1
+1
1
+1
1
+1
A
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
f = f
MAX
= 1/t
RC
150
140
130
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
20
20
20
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V,
or V
IN
< 0.3V,
f = 0
Com'l
8
8
8
mA
L version
0.5
0.5
0.5
Shaded areas contain advance information.
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 3.3V
6
pF
C
OUT
I/O Capacitance
6
pF
Notes:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
T
A
is the "Instant On" case temperature.
3.
Tested initially and after any design or process changes that may affect these parameters.
CY7C1046BV33
PRELIMINARY
Document #: 38-05170 Rev. **
Page 3 of 8
AC Test Loads and Waveforms
Switching Characteristics
[4]
Over the Operating Range
7C1046BV33-10
7C1046BV33-12
7C1046BV33-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
10
12
15
ns
t
AA
Address to Data Valid
10
12
15
ns
t
OHA
Data Hold from Address Change
3
3
3
ns
t
ACE
CE LOW to Data Valid
10
12
15
ns
t
DOE
OE LOW to Data Valid
4
6
7
ns
t
LZOE
OE LOW to Low Z
[6]
0
0
0
ns
t
HZOE
OE HIGH to High Z
[5, 6]
5
6
7
ns
t
LZCE
CE LOW to Low Z
[6]
3
3
3
ns
t
HZCE
CE HIGH to High Z
[5, 6]
5
6
7
ns
t
PU
CE LOW to Power-Up
0
0
0
ns
t
PD
CE HIGH to Power-Down
10
12
15
ns
WRITE CYCLE
[7, 8]
t
WC
Write Cycle Time
10
12
15
ns
t
SCE
CE LOW to Write End
7
10
12
ns
t
AW
Address Set-Up to Write End
7
10
12
ns
t
HA
Address Hold from Write End
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
ns
t
PWE
WE Pulse Width
7
10
12
ns
t
SD
Data Set-Up to Write End
5
7
8
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
LZWE
WE HIGH to Low Z
[6]
3
3
3
ns
t
HZWE
WE LOW to High Z
[5, 6]
5
6
7
ns
Shaded areas contain advance information.
Notes:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
6.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7.
The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8.
The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
1046BV333
1046BV334
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R1 317
R1 317
R2
351
R2
351
167
Equivalent to:
VENIN EQUIVALENT
1.73V
TH
Rise Time: 1 V/ns
Fall Time: 1 V/ns
CY7C1046BV33
PRELIMINARY
Document #: 38-05170 Rev. **
Page 4 of 8
s
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
[10]
Min.
Max
Unit
V
DR
V
CC
for Data Retention
2.0
V
I
CCDR
Data Retention Current
Com'l
V
CC
= V
DR
= 2.0V,
CE > V
CC
0.3V
V
IN
> V
CC
0.3V or V
IN
< 0.3V
200
A
t
CDR
[3]
Chip Deselect to Data Retention Time
0
ns
t
R
[9]
Operation Recovery Time
10
s
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1
[11, 12]
Read Cycle No. 2 (OE Controlled)
[12, 13]
Notes:
9.
t
r
< 3 ns for the -10, -12, and -15 speeds.
10. No input may exceed V
CC
+ 0.5V.
11. Device is continuously selected. OE, CE = V
IL
.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
1046BV335
3.0V
3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
1046BV336
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
I
CC
I
SB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
1046BV33-7
CY7C1046BV33
PRELIMINARY
Document #: 38-05170 Rev. **
Page 5 of 8
Write Cycle No. 1 (CE Controlled)
[14, 15]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[14, 15]
Notes:
14. Data I/O is high impedance if OE = V
IH
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
16. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms
(continued)
1046BV338
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
ADDRESS
WE
DATA I/O
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE
16
1046BV339
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