CY7C09349A
CY7C09359A
4K/8K x 18
Synchronous Dual-Port Static RAM
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-06048 Rev. **
Revised September 19, 2001
25/0251
Features
True dual-ported memory cells which allow simulta-
neous access of the same memory location
Two Flow-Through/Pipelined devices
-- 4K x 18 organization (CY7C09349A)
-- 8K x 18 organization (CY7C09359A)
Three Modes
-- Flow-Through
-- Pipelined
-- Burst
Pipelined output mode on both ports allows fast
100-MHz cycle time
0.35-micron CMOS for optimum speed/power
High-speed clock to data access 6.5
[1]
/7.5/9/12 ns
(max.)
Low operating power
-- Active = 200 mA (typical)
-- Standby = 0.05 mA (typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally
-- Shorten cycle times
-- Minimize bus noise
-- Supported in Flow-Through and Pipelined modes
Dual Chip Enables for easy depth expansion
Upper and lower byte controls for bus matching
Automatic power-down
Commercial and Industrial temperature ranges
Available in 100-pin TQFP
Notes:
1.
See page 6 for Load Conditions.
2.
A
0
A
11
for 4K; A
0
A
12
for 8K devices.
v
Logic Block Diagram
R/W
L
1
0
0/1
CE
0L
CE
1L
LB
L
OE
L
UB
L
1b
0/1
0b 1a 0a
b
a
FT/Pipe
L
I/O
9L
I/O
17L
I/O
0L
I/O
8L
I/O
Control
Counter/
Address
Register
Decode
A
0L
A
11/12L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
True Dual-Ported
RAM Array
R/W
R
1
0
0/1
CE
0R
CE
1R
LB
R
OE
R
UB
R
1b
0/1
0b
1a
0a
b
a
FT/Pipe
R
I/O
Control
Counter/
Address
Register
Decode
12/13
9
9
I/O
9R
I/O
17R
I/O
0R
I/O
8R
A
0R
A
11/12R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
12/13
9
9
[2]
[2]
For the most recent information, visit the Cypress web site at www.cypress.com
CY7C09349A
CY7C09359A
Document #: 38-06048 Rev. **
Page 2 of 17
Functional Description
The CY7C09349A and CY7C09359A are high-speed synchro-
nous CMOS 4K and 8K x 18 dual-port static RAMs. Two ports
are provided, permitting independent, simultaneous access
for reads and writes to any location in memory.
[3]
Registers on
control, address, and data lines allow for minimal set-up and
hold times. In pipelined output mode, data is registered for
decreased cycle time. Clock to data valid t
CD2
= 6.5 ns
[1]
(pipe-
lined). Flow-through mode can also be used to bypass the
pipelined output register to eliminate access latency. In flow-
through mode data will be available t
CD1
= 15 ns after the
address is clocked into the device. Pipelined output or flow-
through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port's burst counter is loaded with the port's Address Strobe
(ADS). When the port's Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port's clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
3.
When simultaneously writing to the same location, final value cannot be determined.
CY7C09349A
CY7C09359A
Document #: 38-06048 Rev. **
Page 3 of 17
Pin Configuration
Note:
4.
This pin is NC for CY7C09349A.
Selection Guide
CY7C09349A
CY7C09359A
-6
[1]
CY7C09349A
CY7C09359A
-7
CY7C09349A
CY7C09359A
-9
CY7C09349A
CY7C09359A
-12
f
MAX2
(MHz) (Pipelined)
100
83
67
50
Max. Access Time (ns) (Clock to Data, Pipelined)
6.5
7.5
9
12
Typical Operating Current I
CC
(mA)
250
235
215
195
Typical Standby Current for I
SB1
(mA)
(Both Ports TTL Level)
45
40
35
30
Typical Standby Current for I
SB3
(mA)
(Both Ports CMOS Level)
0.05
0.05
0.05
0.05
1
3
2
92 91 90
84
85
87 86
88
89
83 82 81
76
78 77
79
80
93
94
95
96
97
98
99
100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A8R
A9R
A10R
A11R
A12R
NC
CE0R
NC
UBR
CNTRSTR
R/WR
FT/PIPER
I/O17R
LBR
NC
GND
OER
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
CE1R
58
57
56
55
54
53
52
51
A9L
A10L
A11L
A12L
NC
NC
CE1L
LBL
CE0L
R/WL
OEL
I/O17L
I/O16L
UBL
NC
VCC
FT/PIPEL
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O11L
I/O10L
CNTRSTL
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8
L
A7
L
A6
L
A5
L
A4
L
A3
L
CL
KL
A1
L
CNT
E
N
L
GND
GND
CNT
E
N
R
A0
R
A0
L
A2
L
ADS
R
CL
KR
A1
R
A2
R
A3
R
A4
R
A5
R
A6
R
A7
R
ADS
L
34 35 36
42
41
39 40
38
37
43 44 45
50
48 49
47
46
I/10R
I/O9R
I/O8R
I/O7R
VC
C
I/O6R
I/01R
I/O4R
I/O2R
GND
I/
O0L
I/
O2L
I/
O3L
I/O3R
I/O5R
I/
O1L
GND
I/
O4L
I/
O5L
I/
O6L
I/
O7L
VC
C
I/
O8L
I/
O9L
I/O0R
33
32
31
30
29
28
27
26
100-Pin TQFP (Top View)
[3]
[3]
CY7C09349A (4K x 18)
CY7C09359A (8K x 18)
CY7C09349A
CY7C09359A
Document #: 38-06048 Rev. **
Page 4 of 17
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with Power Applied ..55
C to +125
C
Supply Voltage to Ground Potential ............... 0.3V to +7.0V
DC Voltage Applied to
Outputs in High Z State ................................. 0.5V to +7.0V
DC Input Voltage............................................ 0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
Latch-Up Current ..................................................... >200 mA
Note:
5.
Industrial Parts are available in CY7C09359A only.
Pin Definitions
Left Port
Right Port
Description
A
0L
A
12L
A
0R
A
12R
Address Inputs (A
0
A
11
for 4K, A
0
A
12
for 8K devices).
ADS
L
ADS
R
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address
counter with data present on the I/O pins.
CE
0L
,CE
1L
CE
0R
,CE
1R
Chip Enable Input. To select either the left or right port, both CE
0
AND CE
1
must be asserted
to their active states (CE
0
V
IL
and CE
1
V
IH
).
CLK
L
CLK
R
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
MAX
.
CNTEN
L
CNTEN
R
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRST
L
CNTRST
R
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec-
tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O
0L
I/O
17L
I/O
0R
I/O
17R
Data Bus Input/Output (I/O
0
I/O
15
for x16 devices).
LB
L
LB
R
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte (I/O
0
I/O
8
for x18, I/O
0
I/O
7
for x16) of the memory array. For read operations both
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
UB
L
UB
R
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O
8/9L
I/O
15/17L
).
OE
L
OE
R
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/W
L
R/W
R
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPE
L
FT/PIPE
R
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND
Ground Input.
NC
No Connect.
V
CC
Power Input.
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +70
C 5V
10%
Industrial
[5]
40
C to +85
C 5V
10%
CY7C09349A
CY7C09359A
Document #: 38-06048 Rev. **
Page 5 of 17
Note:
6.
CE
L
and CE
R
are internal signals. To select either the left or right port, both CE
0
AND CE
1
must be asserted to their active states (CE
0
V
IL
and CE
1
V
IH
).
Electrical Characteristics
Over the Operating Range
Parameter
Description
CY7C09349A
CY7C09359A
Unit
-6
[1]
-7
-9
-12
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
V
OH
Output HIGH Voltage
(V
CC
= Min., I
OH
= 4.0 mA)
2.4
2.4
2.4
2.4
V
V
OL
Output LOW Voltage
(V
CC
= Min., I
OH
= +4.0 mA)
0.4
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
2.2
2.2
2.2
V
V
IL
Input LOW Voltage
0.8
0.8
0.8
0.8
V
I
OZ
Output Leakage Current
10
10
10
10
10
10
10
10
A
I
CC
Operating Current
(V
CC
= Max,
I
OUT
= 0 mA)
Outputs Disabled
Com'l.
250
450
235
420
215
360
195
300
mA
Ind.
[5]
240
410
mA
I
SB1
Standby Current (Both
Ports TTL Level)
[6]
CE
L
& CE
R
V
IH
, f = f
MAX
Com'l.
45
115
40
105
35
95
30
85
mA
Ind.
[5]
50
110
mA
I
SB2
Standby Current (One
Port TTL Level)
[6]
CE
L
|
CE
R
V
IH
, f = f
MAX
Com'l.
175
235
160
220
145
205
125
190
mA
Ind.
[5]
160
220
mA
I
SB3
Standby Current (Both
Ports CMOS Level)
[6]
CE
L
& CE
R
V
CC
0.2V, f = 0
Com'l.
0.05
0.5
0.05
0.5
0.05
0.5
0.05
0.5
mA
Ind.
[5]
0.05
0.5
mA
I
SB4
Standby Current (One
Port CMOS Level)
[6]
CE
L
| CE
R
V
IH
,
f = f
MAX
Com'l.
160
200
145
185
130
170
110
150
mA
Ind.
[5]
145
185
mA
Capacitance
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
10
pF
C
OUT
Output Capacitance
10
pF
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