3.3V, 125-MHz Multi-Output Zero Delay Buffer

CY29972

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07290 Rev. *A

December 22, 2002

Features

· Output frequency up to 125 MHz
· 12 Clock outputs: frequency configurable
· 350 ps max. output-to-output skew
· Configurable output disable
· Two reference clock inputs for dynamic toggling
· Oscillator or crystal reference input
· Spread-spectrum-compatible
· Glitch-free output clocks transitioning
· 3.3V power supply
· Pin-compatible with MPC972
· Industrial temperature range: 40°C to +85°C
· 52-pin TQFP package

Table 1. Frequency Table

[1]

VC0_SEL

FB_SEL2

FB_SEL1

FB_SEL0

VC0

12x

16x

20x

16x

24x

32x

40x

10x

12x

16x

20x

Note:

x = the reference input frequency, 200 MHz < F

VCO

< 480 MHz.

Block Diagram

Pin Configuration

REF_SEL

0
1

Phase

Detector

VCO

LPF

Sync

Frz

D Q

QA0

Sync

Frz

D Q

Sync

Frz

D Q

Sync

Frz

D Q

Sync

Frz

D Q

Sync

Frz

D Q

0
1

Power-On

Reset

Output Disable

Circuitry

Data Generator

/4, /6, /8, /12

/4, /6, /8, /10

/2, /4, /6, /8

/4, /6, /8, /10

Sync Pulse

XIN

XOUT

TCLK0

TCLK1

TCLK_SEL

FB_IN

FB_SEL2

MR#/OE

SELA(0,1)

SELB(0,1)

SELC(0,1)

FB_SEL(0,1)

SCLK

SDATA

INV_CLK

QA1

QA2

QA3

QB0

QB1

QB2

QB3

QC0

QC1

QC2

QC3

FB_OUT

SYNC

VCO_SEL

PLL_EN

VSS

MR#/OE

SCLK

SDATA

FB_SEL2

PLL_EN

REF_SEL

TCLK_SEL

TCLK0

TCLK1

XIN

XOUT

VDD

SEL

SYNC

VSS

QC0

VDDC

QC1

SEL

QC2

VDDC

QC3

VSS

INV

CLK

SEL

VDDC

VSS

VDDC

VSS

VCO

SEL

VSS

QB0

VDDC

QB1

VSS

QB2

VDDC

QB3

FB_IN

VSS
FB_OUT

VDDC

FB_SEL0

2
3
4
5
6
7
8
9
10
11
12
13

38
37
36
35
34
33
32
31
30
29
28
27

14 15 16 17 18 19 20 21 22 23 24 25 26

52 51 50 49 48 47 46 45 44 43 42 41 40

CY29972

CY29972

Document #: 38-07290 Rev. *A

Page 2 of 8

Pin Description

[2]

Pin

Name

PWR

I/O

Type

Description

Oscillator Input. Connect to a crystal.

OUT

Oscillator Output. Connect to a crystal.

CLK0

External Reference/Test Clock Input.

CLK1

External Reference/Test Clock Input.

44, 46, 48, 50

QA(3:0)

DDC

Clock Outputs. See Table 2 for frequency selections.

32, 34, 36, 38

QB(3:0)

DDC

Clock Outputs. See Table 2 for frequency selections.

16, 18, 21, 23

QC(3:0)

DDC

Clock Outputs. See Table 2 for frequency selections.

FB_OUT

DDC

Feedback Clock Output. Connect to FB_IN for normal operation.
The divider ratio for this output is set by FB_SEL(0:2). See Table 1.
A bypass delay capacitor at this output will control Input Reference/
Output Banks phase relationships.

SYNC

DDC

Synchronous Pulse Output. This output is used for system
synchronization. The rising edge of the output pulse is in sync with
both the rising edges of QA (0:3) and QC(0:3) output clocks
regardless of the divider ratios selected.

42, 43

SELA(1,0)

Frequency Select Inputs. These inputs select the divider ratio at
QA(0:3) outputs. See Table 2.

40, 41

SELB(1,0)

Frequency Select Inputs. These inputs select the divider ratio at
QB(0:3) outputs. See Table 2.

19, 20

SELC(1,0)

Frequency Select Inputs. These inputs select the divider ratio at
QC(0:3) outputs. See Table 2.

5, 26, 27

FB_SEL(2:0)

Feedback Select Inputs. These inputs select the divide ratio at
FB_OUT output. See Table 1.

VCO_SEL

VCO Divider Select Input. When set low, the VCO output is
divided by 2. When set high, the divider is bypassed. See Table 1.

FB_IN

Feedback Clock Input. Connect to FB_OUT for accessing the
PLL.

PLL_EN

PLL Enable Input. When asserted high, PLL is enabled. And when
low, PLL is bypassed.

REF_SEL

Reference Select Input. When high, the crystal oscillator is
selected. And when low, TCLK (0,1) is the reference clock.

TCLK_SEL

TCLK Select Input. When LOW, TCLK0 is selected and when high
TCLK1 is selected.

MR#/OE

Master Reset/Output Enable Input. When asserted low, resets all
of the internal flip-flops and also disables all of the outputs. When
pulled high, releases the internal flip-flops from reset and enables
all of the outputs.

INV_CLK

Inverted Clock Input. When set high, QC(2,3) outputs are
inverted. When set low, the inverter is bypassed.

CLK

Serial Clock Input. Clocks data at SDATA into the internal register.

DATA

Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.

17, 22, 28,

33,37, 45, 49

DDC

3.3V power supply for output clock buffers.

3.3V power supply for PLL.

1, 15, 24, 30,

35, 39, 47, 51

Common ground.

Note:

A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power (< 0.2"). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.

CY29972

Document #: 38-07290 Rev. *A

Page 3 of 8

Description

The CY29972 has an integrated PLL that provides low skew
and low jitter clock outputs for high-performance micropro-
cessors. Three independent banks of four outputs and an
independent PLL feedback output (FB_OUT) provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the V

is configured to

run between 200 MHz and 480 MHz. This allows a wide range
of output frequencies up to125 MHz.

The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input (FB_IN) is connected to the feedback output
(FB_OUT). The internal V

is running at multiples of the input

reference clock set by FB_SEL(0:2) and VCO_SEL select

inputs (refer to Frequency Table). The V

frequency is then

divided to provide the required output frequencies. These
dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select
inputs (see Table 3 below). For situations were the V

needs

to run at relatively low frequencies and hence might not be
stable, assert VCO_SEL low to divide the VCO frequency by
2. This will maintain the desired output relationships but will
provide an enhanced PLL lock range.

The CY29972 is also capable of providing inverted output
clocks. When INV_CLK is asserted HIGH, QC2 and QC3
output clocks are inverted. These clocks could be used as
feedback outputs to the CY29972 or a second PLL device to
generate early or late clocks for a specific design. This
inversion does not affect the output to output skew.

Glitch-Free Output Frequency Transitions

Customarily, when output buffers have their internal counters
changed "on the fly," their output clock periods will:

1. contain short or "runt" clock periods. These are clock cycles

in which the cycle(s) are shorter in period than either the
old or new frequencies to which the cycles are being tran-
sitioned.

2. contain stretched clock periods. These are clock cycles in

which the cycle(s) are longer in period than either the old
or new frequencies to which the cycles are being transi-
tioned.

This device specifically includes logic to guarantee that runt
and stretched clock pulses do not occur if the device logic

levels of any or all of the following pins changed "on the fly"
while it is operating: SELA, SELB, SELC, and VCO_SEL.

SYNC Output

In situations where output frequency relationships are not
integer multiples of each other, the SYNC output provides a
signal for system synchronization. The CY29972 monitors the
relationship between the QA and QC output clocks. It provides
a LOW-going pulse, one period in duration, one period prior to
the coincident rising edges of the QA and QC outputs. The
duration and placement of the pulse depend on the higher of
the QA and QC output frequencies. The following timing
diagram illustrates various waveforms for the SYNC output.
Note that the SYNC output is defined for all possible combina-
tions of QA and QC outputs, even though under some relation-
ships the lower frequency clock could be used as a synchro-

Table 2.

VCO_SEL

SELA1

SELA0

SELB1

SELB0

SELC1

SELC0

VCO/8

VCO/4

VCO/12

VCO/8

VCO/16

VCO/12

VCO/24

VCO/20

VCO/16

VCO/4

VCO/2

VCO/6

VCO/4

VCO/8

VCO/6

VCO/12

VCO/10

VCO/8

CY29972

Document #: 38-07290 Rev. *A

Page 5 of 8

Power Management

The individual output enable/freeze control of the CY29972
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic
`0' state when the freeze control bits are activated. The serial
input register contains one programmable freeze enable bit for
12 of the 14 output clocks. The QC0 and FB_OUT outputs can
not be frozen with the serial port, this avoids any potential lock
up situation should an error occur in the loading of the serial

data. An output is frozen when a logic `0' is programmed and
enabled when a logic `1' is written. The enabling and freezing
of individual outputs is done in such a manner as to eliminate
the possibility of partial "runt" clocks.

The serial input register is programmed through the SDATA
input by writing a logic `0' start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equals the period of
the free running SCLK signal. The SDATA is sampled on the
rising edge of SCLK.

Figure 2.

Notes:

For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meet or exceed these specifi-
cations.

Larger values may cause this device to exhibit oscillator start-up problems.

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11

D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC

Start

Bit

Table 3. Suggested Oscillator Crystal Parameters

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

Frequency Tolerance

±100

PPM

Note 3

Frequency Temperature
Stability

±100

PPM

10 to +60

[3]

Aging

PPM/Yr

(first 3 years @ 25

[3]

Load Capacitance

The crystal's rated load.

[3]

ESR

Effective Series Resistance
(ESR)

Ohms

Note 44

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