2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
CY29773
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07573 Rev. **
Revised August 27, 2003
Features
Output frequency range: 8.33 MHz to 200 MHz
Input frequency range: 6.25 MHz to 125 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
2% max Output duty cycle variation
12 Clock outputs: drive up to 24 clock lines
One feedback output
Three reference clock inputs: LVPECL or LVCMOS
300-ps max output-output skew
Phase-locked loop (PLL) bypass mode
Spread AwareTM
Output enable/disable
Pin-compatible with MPC9773 and MPC973
Industrial temperature range: 40C to +85C
52-pin 1.0-mm TQFP package
Description
The CY29773 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high speed clock
distribution applications.
The CY29773 features one LVPECL and two LVCMOS
reference clock inputs and provides 12 outputs partitioned in
three banks of four outputs each. Each bank divides the VCO
output per SEL(A:C) settings (see Table 2. Function Table
(Configuration Controls)). These dividers allow output-to-input
ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4,
1:1, and 5:6. Each LVCMOS-compatible output can drive 50
series- or parallel-terminated transmission lines. For
series-terminated transmission lines, each output can drive
one or two traces, giving the device an effective fanout of 1:24.
The PLL is ensured stable, given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies, from 8 MHz to 200 MHz. For normal
operation, the external feedback input FB_IN is connected to
the feedback output FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider (see Table 1. Frequency Table).
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
A V SS
MR#/OE
SCLK
SDA TA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
A V DD
FB
_
S
E
L
1
SY
N
C
VS
S
QC
0
V
DDQ
C
QC
1
SE
L
C
0
SE
L
C
1
QC
2
V
DDQ
C
QC
3
VS
S
INV
_
CLK
SE
L
B
1
SE
L
B
0
SE
L
A
1
SE
L
A
0
QA
3
V
DDQ
A
QA
2
VS
S
QA
1
V
DDQ
A
QA
0
VS
S
VC
O
_
SEL
V SS
QB0
V DDQB
QB1
V SS
QB2
V DDQB
QB3
FB_IN
V SS
FB_OUT
V DD
FB_SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
C Y 29773
REF_SEL
0
1
0
1
Phase
Detector
VCO
LPF
Sync
Frz
D Q
QA0
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
0
1
/2
Power-On
Reset
Output Disable
Circuitry
Data Generator
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
PECL_CLK
PECL_CLK#
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
SCLK
SDATA
INV_CLK
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
12
VCO_SEL
PLL_EN
CY29773
Document #: 38-07573 Rev. **
Page 2 of 12
Pin Description
[1]
Pin
Name
I/O
Type
Description
11
PECL_CLK
I, PU
LVPECL
LVPECL reference clock input.
12
PECL_CLK#
I
LVPECL
LVPECL reference clock input.
9
TCLK0
I, PU
LVCMOS LVCMOS/LVTTL reference clock input.
10
TCLK1
I, PU
LVCMOS LVCMOS/LVTTL reference clock input.
44,46,48,50
QA(3:0)
O
LVCMOS Clock output bank A.
32,34,36,38
QB(3:0)
O
LVCMOS Clock output bank B.
16,18,21,23
QC(3:0)
O
LVCMOS Clock output bank C.
29
FB_OUT
O
LVCMOS Feedback clock output. Connect to FB_IN for normal operation.
31
FB_IN
I, PU
LVCMOS Feedback clock input. Connect to FB_OUT for normal operation. This
input should be at the same voltage rail as input reference clock. See
Table 1. Frequency Table.
25
SYNC
O
LVCMOS Synchronous pulse output. This output is used for system synchro-
nization.
6
PLL_EN
I, PU
LVCMOS PLL enable/bypass input. When Low, PLL is disabled/bypassed and
the input clock connects to the output dividers.
2
MR#/OE
I, PU
LVCMOS Master reset and Output enable/disable input. See Table 2.
Function Table (Configuration Controls).
8
TCLK_SEL
I, PU
LVCMOS LVCMOS Clock reference select input. See Table 2. Function Table
(Configuration Controls).
7
REF_SEL
I, PU
LVCMOS LVCMOS/LVPECL Reference select input. See Table 2. Function
Table (Configuration Controls).
52
VCO_SEL
I, PU
LVCMOS VCO Operating frequency select input. See Table 2. Function Table
(Configuration Controls).
14
INV_CLK
I, PU
LVCMOS QC(2,3) Phase selection input. See Table 2. Function Table (Config-
uration Controls).
5,26,27
FB_SEL(2:0)
I, PU
LVCMOS Feedback divider select input. See Table 6.
42,43
SELA(1,0)
I, PU
LVCMOS Frequency select input, Bank A. See Table 3. Function Table (Bank
A).
40,41
SELB(1,0)
I, PU
LVCMOS Frequency select input, Bank B. See Table 4. Function Table (Bank
B).
19,20
SELC(1,0)
I, PU
LVCMOS Frequency select input, Bank C. See Table 5. Function Table (Bank
C).
3
SCLK
I, PU
LVCMOS Serial clock input.
4
SDATA
I, PU
LVCMOS Serial data input.
45,49
VDDQA
Supply
VDD
2.5V or 3.3V Power supply for bank A output clocks.
[2,3]
33,37
VDDQB
Supply
VDD
2.5V or 3.3V Power supply for bank B output clocks.
[2,3]
22,17
VDDQC
Supply
VDD
2.5V or 3.3V Power supply for bank C output clocks.
[2,3]
13
AVDD
Supply
VDD
2.5V or 3.3V Power supply for PLL.
[2,3]
28
VDD
Supply
VDD
2.5V or 3.3V Power supply for core and inputs.
[2,3]
1
AVSS
Supply
Ground
Analog Ground.
15,24,30,35,39,47,51 VSS
Supply
Ground
Common Ground.
Notes:
1.
PU = Internal pull up, PD = Internal pull down.
2.
A 0.1-
F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.
AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
CY29773
Document #: 38-07573 Rev. **
Page 3 of 12
Table 1. Frequency Table
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
4
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 95 MHz
6
Input Clock * 6
33.3 MHz to 83.3 MHz
33.3 MHz to 63.3 MHz
8.
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 47.5 MHz
10
Input Clock * 10
20 MHz to 50 MHz
20 MHz to 38 MHz
12
Input Clock * 12
16.6 MHz to 41.6 MHz
16.6 MHz to 31.6 MHz
16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 23.75 MHz
20
Input Clock * 20
10 MHz to 25 MHz
10 MHz to19 MHz
24
Input Clock * 24
8.3 MHz to 20.8 MHz
8.3 MHz to 15.8 MHz
32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 11.8 MHz
40
Input Clock * 40
5 MHz to 12.5 MHz
5 MHz to 9.5 MHz
Table 2. Function Table (Configuration Controls)
Control
Default
0
1
REF_SEL
1
TCLK0, TCLK1
PECL_CLK
TCLK_SEL
1
TCLK0
TCLK1
VCO_SEL
1
VCO
2 (low input frequency range)
VCO
1 (high input frequency range)
PLL_EN
1
Bypass mode, PLL disabled. The input clock connects to the
output dividers
PLL enabled. The VCO output
connects to the output dividers
INV_CLK
1
QC2 and QC3 are in phase with QC0 and QC1
QC2 and QC3 are inverted (180 phase
shift) with respect to QC0 and QC1
MR#/OE
1
Outputs disabled (three-state) and reset of the device. During
reset/output disable the PLL feedback loop is open and the VCO
running at its minimum frequency. The device is reset by the
internal power-on reset (POR) circuitry during power-up.
Outputs enabled
Table 3. Function Table (Bank A)
VCO_SEL
SELA1
SELA0
QA(0:3)
0
0
0
8
0
0
1
12
0
1
0
16
0
1
1
24
1
0
0
4
1
0
1
6
1
1
0
8
1
1
1
12
Table 4. Function Table (Bank B)
VCO_SEL
SELB1
SELB0
QB(0:3)
0
0
0
8
0
0
1
12
0
1
0
16
0
1
1
20
1
0
0
4
1
0
1
6
1
1
0
8
1
1
1
10
Table 5. Function Table (Bank C)
VCO_SEL
SELC1
SELC0
QC(0:3)
0
0
0
4
0
0
1
8
0
1
0
12
0
1
1
16
1
0
0
2
1
0
1
4
1
1
0
6
1
1
1
8
Table 6. Function Table (FB_OUT)
VCO_SEL
FB_SEL2
FB_SEL1
FB_SEL0
FB_OUT
0
0
0
0
8
0
0
0
1
12
0
0
1
0
16
0
0
1
1
20
0
1
0
0
16
0
1
0
1
24
0
1
1
0
32
0
1
1
1
40
1
0
0
0
4
CY29773
Document #: 38-07573 Rev. **
Page 4 of 12
1
0
0
1
6
1
0
1
0
8
1
0
1
1
10
1
1
0
0
8
1
1
0
1
12
1
1
1
0
16
1
1
1
1
20
Table 6. Function Table (FB_OUT) (continued)
CY29773
Document #: 38-07573 Rev. **
Page 5 of 12
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
V
DD
DC Supply Voltage
0.3
5.5
V
V
DD
DC Operating Voltage
Functional
2.375
3.465
V
V
IN
DC Input Voltage
Relative to V
SS
0.3
V
DD
+ 0.3
V
V
OUT
DC Output Voltage
Relative to V
SS
0.3
V
DD
+ 0.3
V
V
TT
Output termination Voltage
V
DD
2
V
LU
Latch-up Immunity
Functional
200
mA
R
PS
Power Supply Ripple
Ripple Frequency < 100 kHz
150
mVp-p
T
S
Temperature, Storage
Non-functional
65
+150
C
T
A
Temperature, Operating Ambient
Functional
40
+85
C
T
J
Temperature, Junction
Functional
+150
C
JC
Dissipation, Junction to Case
Functional
23
C/W
JA
Dissipation, Junction to Ambient
Functional
55
C/W
ESD
H
ESD Protection (Human Body Model)
2000
V
FIT
Failure in Time
Manufacturing test
10
ppm
DC Electrical Specifications
(V
DD
= 2.5V 5%, T
A
= 40C to +85C)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
V
IL
Input Voltage, Low
LVCMOS
0.7
V
V
IH
Input Voltage, High
LVCMOS
1.7
V
DD
+0.3
V
V
PP
Peak-Peak Input Voltage
LVPECL
250
1000
mV
V
CMR
Common Mode Range
[4]
LVPECL
1.0
V
DD
0.6
V
V
OL
Output Voltage, Low
[5]
I
OL
= 15 mA
0.6
V
V
OH
Output Voltage, High
[5]
I
OH
= 15 mA
1.8
V
I
IL
Input Current, Low
[5]
V
IL
= V
SS
100
A
I
IH
Input Current, High
[6]
V
IL
= V
DD
100
A
I
DDA
PLL Supply Current
AVDD only
5
10
mA
I
DDQ
Quiescent Supply Current
All VDD pins except AVDD
8
mA
I
DD
Dynamic Supply Current
Outputs loaded @ 100 MHz
135
mA
C
IN
Input Pin Capacitance
4
pF
Z
OUT
Output Impedance
14
18
22
DC Electrical Specifications
(V
DD
= 3.3V 5%, T
A
= 40C to +85C)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
V
IL
Input Voltage, Low
LVCMOS
0.8
V
V
IH
Input Voltage, High
LVCMOS
2.0
V
DD
+0.3
V
V
PP
Peak-Peak Input Voltage
LVPECL
250
1000
mV
V
CMR
Common Mode Range
[4]
LVPECL
1.0
V
DD
0.6
V
V
OL
Output Voltage, Low
[5]
I
OL
= 24 mA
0.55
V
I
OL
= 12 mA
0.30
V
OH
Output Voltage, High
[5]
I
OH
= 24 mA
2.4
V
I
IL
Input Current, Low
[6
V
IL
= V
SS
100
A
Notes:
4.
V
CMR
(DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the V
CMR
range and the input
swing is within the V
PP
(DC) specification.
5.
Driving one 50
parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50
series terminated
transmission lines.
6.
Inputs have pull-up or pull-down resistors that affect the input current.
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