High-Performance SiS645DX/648DX/650/651

Intel Pentium

4 Clock Synthesizer

CY28381

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07546 Rev. **

Revised May 20, 2003

Features

· Supports Pentium

4-type CPUs

· 3.3V power supply
· Eight copies of PCI clocks
· One 48-MHz USB clock
· Two copies of ZCLK cocks
· One 48-MHz/24-MHz Programmable SIO clock
· Two differential CPU clock pairs

· SMBus support with readback capabilities
· Spread Spectrum electromagnetic interference (EMI)

reduction

· Dial-A-Frequency

features

· Dial-A-RatioTM features
· Dial-A-dBTM features
· 48-pin SSOP Package
· Watchdog function

Note:

Pins marked with [*] have internal 150K pull-up resistors. Pins marked with [**] have internal 150K pull-down resistors.

Block Diagram

Pin Configuration

[1]

PLL1

PLL2

Logic

XIN

XOUT

CPU_STP#

IREF

FS[0:4]

MULT0

VTT_PWRGD

PCI_STP#

PD#

SDATA

SCLK

48M_24M#

48M

PCIF[0:1]

PCI[0:5]

ZCLK[0:1]

AGP[0:1]

CPUC[0:1]

CPUT[0:1]

REF(0:2)

I2C

Logic

SRESET#

Power

Latch

SDCLK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

VDDSD
SDCLK
VSSSD
CPU_STP#*

CPUT1
CPUC1
VDDC

VSSC

CPUT0
CPUC0
IREF
VSSA
VDDA
SCLK
SDATA
PD#/VTT_PWRGD*
VSSAGP
AGP0
AGP1
VDDAGP
VDD48M

48M
24_48M/MULT0*
VSS48M

VDDR

**FS0/REF0
**FS1/REF1
**FS2/REF2

VSSR

XIN

XOUT

VSSZ

ZCLK0
ZCLK1

VDDZ

*SRESET#/PCI_STP#

VDDP

**FS3/PCIF0

PCI0

**FS4/PCIF1

PCI1

VSSP

VDDP

PCI2
PCI3

PCI4
PCI5

VSSP

28381

48 pin SSOP

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Document #: 38-07546 Rev. **

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Pin Description

[2]

Pin

Name

PWR

I/O

Description

XIN

Oscillator Buffer Input. Connect to a crystal or to an external clock.

XOUT

VDDR

Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.

40,44

CPU[0:1]

VDDC

"True" Host Output Clocks. See Table 1 for frequencies and functionality.

39,43

CPUC[0:1]

VDDC

"Complementary" Host Output Clocks. See Table 1 for frequencies and
functionality.

16,17,20,23 PCI [0:5]

VDDP

PCI Clock Outputs. See Table 1.

FS3/PCIF0

VDDP

I/O
PD

Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When
VTT_PWRGD transitions to a logic high, FS3 state is latched and this pin
becomes PCIF0 Clock Output. See Table 1.

FS4/PCIF1

VDDP

I/O
PD

Power-on Bidirectional Input/Output. At power-up, FS4 is the input. When
VTT_PWRGD transitions to a logic high, FS4 state is latched and this pin
becomes PCIF1 Clock Output. See Table 1.

FS0/REF0

VDDR

I/O
PD

Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When
VTT_PWRGD transitions to a logic high, FS0 state is latched and this pin
becomes REF0, buffered Output copy of the device's XIN clock.

FS1/REF1

VDDR

I/O
PD

Power-on Bidirectional Input/Output. At power-up, FS1 is the input. When
VTT_PWRGD is transited to logic low, FS1 state is latched and this pin
becomes REF1, buffered Output copy of the device's XIN clock.

FS2/REF2

VDDR

I/O
PD

Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When
VTT_PWRGD is transited to logic low, FS2 state is latched and this pin
becomes REF2, buffered Output copy of the device's XIN clock.

IREF

Current Reference Programming Input for CPU Buffers. A resistor is
connected between this pin and VSS. See Figure 9.

PD#/
VTT_PRGD

VDDAGP

Power-down Input/VTT Power Good Input. At power-up, VTT_PWRGD is
the input. When this input is transitions initially from low to high, the FS (0:4)
and MULT0 are latched. After the first low to high transition, this pin become
a PD# input with an internal pull-up. When PD# is asserted low, the device
enters power down mode. See power management function.

48M

VDD48M

Fixed 48MHz USB Clock Output.

24_48M/
MULT0

VDD48M

I/O

Power-on Bidirectional Input/Output. At power-up, MULT0 is the input.
When VTT_PWRGD is transited to logic low, MULT0 state is latched and this
pin becomes 24_48M, SIO programmable clock output.

9,10

ZCLK (0:1)

VDDZ

HyperZip Clock Outputs. See Table 1.

SDATA

VDDAGP

I/O

Serial Data Input. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.

SCLK

VDDAGP

Serial Clock Input. Conforms to the SMBus specification.

SRESET#

VDDZ

PCI Clock Disable Input. If Byte12 Bit7 = 0, this pin becomes an SRESET#
open drain output, and the internal pulled up is not active. See system reset
description.

PCI_STP#

VDDZ

System Reset Control Output. If Byte12 Bit7 = 1 (Default), this pin becomes
PCI Clock Disable Input. When PCI_STP# is asserted low, PCI (0:5) clocks
are synchronously disabled in a low state. This pin does not affect PCIF (0:1)
if they are programmed to be free-running clocks via the device's SMBus
interface.

CPU_STP#

VDDSD

CPU Clock Disable Input. When asserted low, CPU (0:1)T clocks are
synchronously disabled in a high state and CPU (0:1)C clocks are synchro-
nously disabled in a low state.

SDCLK

VDDSD

SDRAM Clock Output.

30,31

AGP (0:1)

VDDAGP

AGP Clock Outputs. See Table 1 for frequencies and functionality.

Note:

PU = internal pull-up. PD = internal pull-down. T = Tri-level logic input with valid logic voltages of LOW =<0.8V, T =1.0 -1.8V and HIGH => 2.0V.

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VDDSD

PWR 3.3V Power Supply for SDRAM Clock Output.

VDDAGP

PWR 3.3V Power Supply for AGP Clock Outputs.

VDDZ

PWR 3.3V Power Supply for HyperZip Clock Outputs.

VDDR

PWR 3.3V Power Supply for REF Clock Outputs.

13,19

VDDP

PWR 3.3V Power Supply for PCI Clock Outputs.

VDDC

PWR 3.3V Power Supply for CPU Clock Outputs.

VDD48M

PWR 3.3V Power Supply for 48-MHz/24-MHz Clock Outputs.

VDDA

PWR 3.3V Analog Power Supply.

18,24

VSSP

PWR GND for PCI Clocks Outputs.

VSSC

PWR GND for CPU Clocks Outputs.

VSSZ

PWR GND for HyperZip Clock Outputs.

VSS48M

PWR GND for 48-MHz/24-MHz Clock Outputs.

VSSR

PWR GND for REF Clock Outputs.

VSSSD

PWR GND for SDRAM Clock Output.

VSSAGP

PWR GND for AGP Clock Outputs.

VSSA

PWR GND for Analog.

Table 1. Frequency Table

FS(4:0)

CPU(MHz)

SDRAM(MHz)

ZCLK(MHz)

AGP(MHz

PCI(MHz)

VCO(MHz)

00000

100.2

80.2

66.8

33.4

400.8

00001

100.2

133.6

80.2

66.8

33.4

400.8

00010

100.2

200.4

80.2

66.8

33.4

400.8

00011

100.2

167.0

83.5

62.6

31.3

501.0

00100

133.6

100.2

80.2

66.8

33.4

400.8

00101

133.6

80.2

66.8

33.4

400.8

00110

133.6

200.4

80.2

66.8

33.4

400.8

00111

133.6

167.0

83.5

66.8

33.4

668.0

01000

166.7

100.0

83.4

62.5

31.3

500.1

01001

166.7

133.4

83.4

66.7

33.3

666.8

01010

166.7

222.3

83.4

66.7

33.3

666.8

01011

166.7

83.4

66.7

33.3

666.8

01100

200.1

100.0

80.0

66.7

33.3

400.1

01101

200.1

133.4

80.0

66.7

33.3

400.1

01110

200.1

80.0

66.7

33.3

400.1

01111

200.1

150.0

75.0

66.7

33.3

600.2

10000

100.2

133.6

66.8

33.4

400.8

10001

100.2

133.6

66.8

33.4

400.8

10010

100.2

200.4

133.6

66.8

33.4

400.8

10011

100.2

167.0

125.3

62.6

31.3

501.0

10100

133.6

100.2

133.6

66.8

33.4

400.8

10101

133.6

66.8

33.4

400.8

10110

133.6

200.4

133.6

66.8

33.4

400.8

10111

133.6

167.0

133.6

66.8

33.4

668.0

11000

166.7

100.0

125.0

62.5

31.3

500.1

Pin Description

[2]

(continued)

Pin

Name

PWR

I/O

Description

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Document #: 38-07546 Rev. **

Page 4 of 19

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.

The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).

11001

166.7

133.4

66.7

33.3

666.8

11010

166.7

222.3

133.4

66.7

33.3

666.8

11011

166.7

133.4

66.7

33.3

666.8

11100

200.1

100.0

133.4

66.7

33.3

400.1

11101

200.1

133.4

66.7

33.3

400.1

11110

200.1

133.4

66.7

33.3

400.1

11111

200.1

150.0

120.0

66.7

33.3

600.2

Table 1. Frequency Table (continued)

FS(4:0)

CPU(MHz)

SDRAM(MHz)

ZCLK(MHz)

AGP(MHz

PCI(MHz)

VCO(MHz)

Table 2. Command Code Definition

Bit

Description

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

Table 3. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write = 0

Acknowledge from slave

11:18

Command Code 8 bits
`00000000' stands for block operation

11:18

Command Code 8 bits
`00000000' stands for block operation

Acknowledge from slave

20:27

Byte Count 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

29:36

Data byte 1 8 bits

Read = 1

Acknowledge from slave

38:45

Data byte 2 8 bits

30:37

Byte count from slave 8 bits

Acknowledge from slave

Acknowledge

....

......................

39:46

Data byte from slave 8 bits

....

Data Byte (N1) 8 bits

Acknowledge

....

Acknowledge from slave

48:55

Data byte from slave 8 bits

....

Data Byte N 8 bits

Acknowledge

....

Acknowledge from slave

....

Data bytes from slave/Acknowledge

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Since SDR and DDR Zero Delay Buffers, will share this same
address, this device starts from Byte 4.

....

Stop

....

Data byte N from slave 8 bits

....

Not Acknowledged

....

Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write = 0

Acknowledge from slave

11:18

Command Code 8 bits
`1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed

11:18

Command Code 8 bits
`1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed

Acknowledge from slave

20:27

Data byte from master 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

Stop

Read = 1

Acknowledge from slave

30:37

Data byte from slave 8 bits

Not Acknowledge

Stop

Table 3. Block Read and Block Write Protocol (continued)

Byte 4: CPU Clock Register

Bit

@Pup

Name

Description

H/W Setting

FS3

For selecting frequencies in Table 1

H/W Setting

FS2

For selecting frequencies in Table 1

H/W Setting

FS1

For selecting frequencies in Table 1

H/W Setting

FS0

For selecting frequencies inTable 1

SW/HW

Frequency Setting

Selection

If this bit is programmed to a "1", it enables writes to bits (7:4, 2) for
selecting the frequency via software (SMBus) If this bit is programmed to
a "0" it enables only reads of bits (7:4, 2), which reflect the hardware
setting of FS(0:4).

H/W Setting

FS4

For selecting frequencies in Table 1

SSCG

Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On. This is a Read
and Write control bit.

Master Output Control. 0 = running, 1 = three-state all outputs

Byte 5: CPU Clock Register

Bit

@Pup

Name

Description

Reserved

MULT0

MULT0 (pin 26) Value. This bit is Read-Only

FS4

FS4 read back. This bit is Read-Only

FS3

FS3 read back. This bit is Read-Only.

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FS2

FS2 read back. This bit is Read-Only.

FS1

FS1 read back. This bit is Read-Only.

FS0

FS0 read back. This bit is Read-Only.

Byte 6: CPU Clock Register

Bit

@Pup

Name

Description

Function Test Bit, always program to 0.

Reserved

PCIF0

PCI_STP# control of PCIF0. 0 = Free-Running, 1 = Stopped when
PCI_STP# is LOW.

PCIF1

PCI_STP# control of PCIF1. 0 = Free-Running, 1 = Stopped when
PCI_STP# is LOW.

CPU[T/C]0

Controls CPUT0 and CPUC0 functionality when CPU_STP# is asserted
LOW
0 = Free-Running, 1 + Stopped with CPU_STP# asserted LOW
This is a Read and Write Control bit.

CPU[T/C]1

Controls CPUT1 and CPUC1 functionality when CPU_STP# is asserted
LOW
0 = Free-Running, 1 Stopped with CPU_STP# asserted to LOW
This and Read and Write Control Bit.

CPU0T/C

CPUT0, CPUC0 Output Control, 1 = enabled, 0 = disabled.
This is a Read and Write Control bit.

CPU1T/C

CPUT1, CPUC1 Output Control, 1 = enabled, 0 = disabled.
This is a Read and Write Control bit.

Byte 7: PCI Clock Register

Bit

@Pup

Name

Description

PCIF0

PCIF0 Output Control 1 = enabled, 0 = forced LOW

PCIF1

PCIF1 Output Control 1 = enabled, 0 = forced LOW

PCI5

PCI5 Output Control 1 = enabled, 0 = forced LOW

PCI4

PCI4 Output Control 1 = enabled, 0 = forced LOW

PCI3

PCI3 Output Control 1 = enabled, 0 = forced LOW

PCI2

PCI2 Output Control 1 = enabled, 0 = forced LOW

PCI1

PCI1 Output Control 1 = enabled, 0 = forced LOW

PCI0

PCI0 Output Control 1 = enabled, 0 = forced LOW

Byte 8: Silicon Signature Register

Bit

@Pup

Description

Vendor ID
1000 = Cypress

Revision ID

Byte 5: CPU Clock Register (continued)

Bit

@Pup

Name

Description

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Page 7 of 19

Byte 9: Peripheral Control Register

Bit

@Pup

Name

Description

PD#

PD# Enable. 0 = enable, 1 = disable

PD# output control

0 = when PD# is asserted LOW, CPU(0:1)T stop in a high state,
CPUC[0:1] stop in a low state. 1 = when PD# is asserted LOW, CPUT[0:1]
and CPUC[0:1] stop in H-Z.

48M

48M Output Control 1 = enabled, 0 = forced LOW

48M_24M

48M_24M Output Control 1 = enabled, 0 = forced LOW

48M_24M

48M_24M, 0 = pin28 output is 24 MHz, 1 = pin26 output is 48 MHz.

SS2

SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread)

SS1

SS1 Spread Spectrum control bit. See Table 5.

SS0

SS0 Spread Spectrum control bit. See Table 5.

Table 5. Spread Spectrum

SS2

SS1

SS0

Spread Mode

Spread%

Down

0.50

Down

0.75

Down

1.00

Down

1.50

Center

+0.25, 0.25

Center

+0.37, 0.37

Center

+0.50, 0.50

Center

+0.75, 0.75

Byte 10: Peripheral Control Register

Bit

@Pup

Name

Description

SDCLK

SDCLK Output Enable 1 = enabled, 0 = disabled

REF2

REF2 Output Control 1 = enabled, 0 = forced LOW

REF1

REF1 Output Control 1 = enabled, 0 = forced LOW

REF0

REF0 Output Control 1 = enabled, 0 = forced LOW

ZCLK1

ZCLK1 Output Enable 1 = enabled, 0 = disabled

ZCLK0

ZCLK0 Output Enabled 1 = enabled, 0 = disabled

AGP1

AGP1 Output Enabled 1 = enabled, 0 = disabled

AGP0

AGP0 Output Enabled 1 = enabled, 0 = disabled

Byte 11: Dial-a-SkewTM and Dial-a-Ratio Control Register

Bit

@Pup

Name

Description

DARZCK2

Programming these bits allow modifying the frequency ratio of the ZCLK
clock relative to the VCO. See Table 6.

DARZCK1

DARZCK0

DARAG2

Programming these bits allow modifying the frequency ratio of the
AGP(1:0), PCI(5:0) and PCIF(0:1) clocks relative to the VCO. See Table 7

DARAG1

DARAG0

DASSD1

Programming these bits allow shifting skew between CPU and SDCLK
signals. See Table 8.

DASSD0

Table 6. Dial-a-Ratio for ZCLK

DARZCK(2:0)

VC0/ZCLK Ratio

000

Frequency Selection Default

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001

010

011

100

101

110

111

Table 7. Dial-a-Ratio for AGP(0:1)

[3]

DARAG(2:0)

VC0/AGP Ratio

000

Frequency Selection Default

001

010

011

100

101

110

111

Table 8. Dial-a-Skew SDCLK CPU

DASSD(1:0)

SDCLK-CPU Skew

0ps (Default)

[4]

+150ps (CPU lag)*

+300ps (CPU lag)*

+450ps (CPU lag)*

Byte 12: Watchdog Time Stamp Register

Bit

@Pup

Name

Description

SRESET#/

PCI_STP# Selection

SRESET#/PCI_STP#. 1 = Pin 12 is the input pin as PCI_STP# signal.
0 = Pin 12 is the output pin as SRESET# signal.

Frequency Revert. This bit allows setting the Revert Frequency once the
system is rebooted due to Watchdog time out only. 0 = selects frequency
of existing H/W setting1 = selects frequency of the second to last S/W
setting. (the software setting prior to the one that caused a system reboot).

WDTEST. For WD-Test, ALWAYS program to `0'

WD Alarm. This bit is set to "1" when the Watchdog times out. It is reset
to "0" when the system clears the WD time stamps (WD3:0).

WD3

This bits selects the Watchdog Time Stamp Value. See Table 9

WD2

WD1

WD0

Notes:

The ratio of AGP to PCI is retained at 2:1.

See Figure 9 for CPU test measurement point. See

Figure 10 for SDCLK test measurement point.

Table 6. Dial-a-Ratio for ZCLK (continued)

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Table 9. Watchdog Time Stamp Table

WD(3:0)

FUNCTION

0000

Off

0001

1 second

0010

2 seconds

0011

3 seconds

0100

4 seconds

0101

5 seconds

0110

6 seconds

0111

7 seconds

1000

8 seconds

1001

9 seconds

1010

10 seconds

1011

11 seconds

1100

12 seconds

1101

13 seconds

1110

14 seconds

1111

15 seconds

Byte 13: Dial-a-Frequency Control Register N (all bits are read- and write-functional)

[5]

Bit

@Pup

Description

Reserved

N6, MSB

N0, LSB

Byte 14: Dial-a-Frequency Control Register R (all bits are read- and write-functional)

[5, 6]

Bit

@Pup

Description

Reserved

R5 MSB

R0, LSB

R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded
from the Dial-a-Frequency registers into R and N.

Notes:

Byte 13 and Byte 14 should be written together in every case.

The range of R = (20...60), The range of N = (21...125) and N > R > N/2.

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Dial-A-Frequency Feature

SMBus Dial-A-frequency feature is available in this device via
Byte13 and Byte14. P is a large value PLL constant that
depends on the frequency selection achieved through the
hardware selectors (FS4, FS0). P value may be determined
from the following table.

Dial-A-Frequency Formula

Fcpu = (P*N)/R and Range of R = (20..60), Range of N =
(21..125) where N > R > N/2.

For a more detail programming guide, please refer to Cypress
"genapp.pfd" file AN-0025.

Spread Spectrum Clock Generation (SSCG)

Spread Spectrum is a modulation technique used to
minimizing EMI radiation generated by repetitive digital
signals. A clock presents the greatest EMI energy at the center
frequency it is generating. Spread Spectrum distributes this
energy over a specific and controlled frequency bandwidth
therefore causing the average energy at any one point in this
band to decrease in value. This technique is achieved by
modulating the clock away from its resting frequency by a
certain percentage (which also determines the amount of EMI
reduction). In this device, Spread Spectrum is enabled by
setting specific register bits in the SMBus control Bytes. See
the SMBus register section of this data sheet for the exact bit
and byte functionally. The following table is a listing of the
modes and percentages of Spread Spectrum modulation that
this device incorporates.

PD# (Power-down) Clarification

The PD# (Power-down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the low `stopped' state.

PD# Assertion

When PD# is sampled low by two consecutive rising edges of
CPUC clock then all clock outputs (except CPUT) clocks must
be held low on their next high to low transition. CPUT clocks
must be hold with CPUT clock pin driven high with a value of
2x Iref and CPUC undriven.

Due to the state of internal logic, stopping and holding the REF
clock outputs in the LOW state may require more than one
clock cycle to complete

PD# Deassertion

The power-up latency between PD# rising to a valid logic `1'
level and the starting of all clocks is less than 3.0 ms.

CPU_STP# Clarification

The CPU_STP# signal is an active low input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.

CPU_STP# Assertion

When CPU_STP# pin is asserted, all CPU outputs that are set
with the SMBus configuration to be stoppable via assertion of
CPU_STP# will be stopped after being sampled by two falling
CPU clock edges. The final state of the stopped CPU signals
is CPU = HIGH and CPUC0 = LOW. There is no change to the
output drive current values during the stopped state. The CPU
is driven HIGH with a current value equal to (Mult 0 `select') x
(Iref), and the CPUC signal will not be driven. Due to external
pull-down circuitry CPUC will be LOW during this stopped
state.

Table 10.

FS(4:0)

00100, 00101, 00110, 01000,
01111,10100,10101,10110,11000,11111

127994666.7

00000, 00001, 00010, 01001, 01010, 01011,
10000, 10001,10010,11001,11010,11011

95996000

00011, 00111,10011,10111

76796800

01100, 01101, 01110,11100,11101,11110

191992000

CPU_STP#

CPUT

CPUC

CPU Internal

CPU# Internal

Figure 1. Power-down Assertion/Deassertion Timing Waveforms Nonbuffered Mode

CY28381

Document #: 38-07546 Rev. **

Page 11 of 19

CPU_STP# Deassertion

The de-assertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the Deassertion to
active outputs is no more than two CPU clock cycles.

PCI_STP# Assertion

The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (t

setup

). (See

Figure 4.) The PCIF (clocks will not be affected by this pin if
their control bits in the SMBus register are set to allow them to
be free running.

CPU_STP#

CPUT

CPUC

Figure 2. Assertion CPU_STP# Waveforms

CPU_STP#

CPUT

CPUC

CPUT

CPUC

Figure 3. Deassertion CPU_STP# Waveforms

PC I_STP #

PC I_F 33M

PC I 33M

setup

Figure 4. Assertion PCI_STP# Waveforms

CY28381

Document #: 38-07546 Rev. **

Page 12 of 19

PCI_STP# Deassertion

The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.

Note:

The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically
ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus
Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device's stoppable PCI clocks are not running.

P C I_S T P #

P C I_F

P C I

setup

Figure 5. Deassertion PCI_STP# Waveforms

[7]

VTT_PWRGD

PWRGD_VRM

VDD Clock Gen

Clock State

Clock Outputs

Clock VCO

0.2-0.3mS

Delay

State 0

State 2

State 3

Wait for

VTT_PWRGD

Sample FS

Off

State 1

Device is not affected,

VTT_PWRGD is ignored

Figure 6. VTT_PWRGD Timing Diagram

VTT_PWRGD = Low

Delay

>0.25mS

Power Off

VDD_A = 2.0V

Sample

Inputs straps

Normal

Operation

Wait for <1.8ms

Enable Outputs

VTT_PWRGD = toggle

VDD_A = off

Figure 7. Clock Generator Power-up/Run State Diagram

CY28381

Document #: 38-07546 Rev. **

Page 13 of 19

Watchdog Self-Recovery Sequence

This feature is designed to allow the system designer to
change frequency while the system is running and reboot the
operation of the system in case of a hang up due to the
frequency change.

When the system sends an SMBus command requesting a
frequency change through the Dial-a-Frequency Control
Registers, it must have previously sent a command to the
Watchdog Timer to select which time out stamp the Watchdog
must perform, otherwise the System Self-recovery feature will
not be applicable. Consequently, this device will change
frequency and then the Watchdog timer starts timing.

Meanwhile, the system BIOS is running its operation with the
new frequency. If this device receives a new SMBus command
to clear the bits originally programmed in the Watchdog Timer
bits (reprogram to 0000) before the Watchdog times out, then
this device will keep operating in its normal condition with the
new selected frequency.

The Watchdog timer will also be triggered if you program the
software frequency select bits (FSEL) to a new frequency
selection. If the Watchdog times out before the new SMBus
reprograms the Watchdog Timer bits to (0000), then this
device will send a low system reset pulse, on SRESET# and
changes WD Time-out bit to "1."

RESET W ATCHDOG TIMER

Set WD(0:3) Bits = 0

INITIALIZE W ATCHDOG TIMER

Set Frequency Revert Bit

Set WD(0:3) = (# of Sec ) x 2

SET SOFTW ARE FSEL

Set SW Freq_Sel = 1

Set FS(0:4)

Wait for 6msec For

Clock Output to Ramp to

Target Frequency

Hang?

W ATCHDOG TIMEOUT

CLEAR W D

Set WD(0:3) Bits = 0

Exit

Reset

Frequency Revert Bit =

Set Frequency to

FS_HW_Latched

Frequency Revert Bit =

Set Frequency to FS_SW

Set SRESET# = 0 for 6 msec

SET DIAL-A-FREQUENCY

Load M and N Registers

Set Pro_Freq_EN = 1

Figure 8. Watchdog Self-recovery Sequence Flowchart

CY28381

Document #: 38-07546 Rev. **

Page 14 of 19

Absolute Maximum Conditions

Parameter

Description

Condition

Min.

Max.

Unit

Core Supply Voltage

0.5

4.6

DDA

Analog Supply Voltage

0.5

4.6

Input Voltage

Relative to V

0.5

+ 0.5

VDC

Temperature, Storage

Non Functional

+150

°C

Temperature, Operating Ambient

Functional

°C

Temperature, Junction

Functional

150

°C

ESD

HBM

ESD Protection (Human Body Model)

MIL-STD-883, Method 3015

2000

Dissipation, Junction to Case

Mil-Spec 883E Method 1012.1

°C/W

Dissipation, Junction to Ambient

JEDEC (JESD 51)

°C/W

UL94

Flammability Rating

At 1/8 in.

MSL

Moisture Sensitivity Level

Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing
is NOT required.

DC Electrical Specifications

Parameter

Description

Condition

Min.

Max.

Unit

DDSD

DDAGP,

DDZ,

DDR,

DDP,

DDC,

DD48M,

DDA

3.3V Operating Voltage

3.3V ± 5%

3.135

3.465

ILI2C

Input Low Voltage

SDATA, SCLK

1.0

IHI2C

Input High Voltage

SDATA, SCLK

2.2

Input Low Voltage

0.5

0.8

Input High Voltage

2.0

+ 0. 5

Input Leakage Current

except Pull-ups or Pull downs
0 < V

< V

µA

Output Low Voltage

= 1 mA

0.4

Output High Voltage

= 1 mA

2.4

High-Impedance Output Current

µA

Input Pin Capacitance

OUT

Output Pin Capacitance

Pin Inductance

XIH

Xin High Voltage

0.7V

XIL

Xin Low Voltage

0.3V

Dynamic Supply Current

At 200 MHz and all outputs
loaded per Table 11 and Figure 7

300

Power-down Supply Current

PD# Asserted

XTAL

Crystal Pin Capacitance

Nominal = 36 pF

CY28381

Document #: 38-07546 Rev. **

Page 15 of 19

AC Electrical Specifications

Parameter

Description

Condition

Min.

Max.

Unit

Crystal
T

XIN Duty Cycle

The device will operate reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification

47.5

52.5

PERIOD

XIN period

When Xin is driven from an external clock
source

69.841

71.000

XIH

Xin High Voltage

0.7V

XIL

Xin Low Voltage

0.3V

/ T

XIN Rise and Fall Times

Measured between 0.3V

and 0.7V

10.0

CCJ

XIN Cycle to Cycle Jitter

As an average over 1

s duration

500

CPU at 0.7V
T

CPUT and CPUC Duty Cycle

Measured at crossing point V

PERIOD100

100-MHz CPUT and CPUC Period

Measured at crossing point V

9.8

10.2

PERIOD133

133-MHz CPUT and CPUC Period

Measured at crossing point V

7.35

7.65

SKEW

Any CPUT/C to CPUT/C Clock Skew

Measured at crossing point V

150

CCJ

CPUT/C Cycle to Cycle Jitter

Measured at crossing point V

200

/ T

CPUT and CPUC Rise and Fall Times

Measured from Vol = 0.175 to Voh = 0.525V

175

900

RFM

Rise/Fall Matching

Determined as a fraction of
2*(T

-T

)/(T

)

Rise Time Variation

125

Fall Time Variation

125

Crossing Point Voltage at 0.7V Swing

280

430

AGP
T

AGP Duty Cycle

Measured at crossing point V

PERIOD

AGP Period

Measured at crossing point V

15.0

15.3

SKEWUN-

BUFFERED

Any AGP to Any AGP Clock Skew

Measurement at 1.5V

175

/ T

AGP Rise and Fall Times

Measured from Vol= 0.175 to Voh = 0.525V

0.5

1.6

HIGH

AGP High Time

5.25

LOW

AGP Low Time

5.05

CCJ

AGP Cycle to Cycle Jitter

Measured at crossing point V

500

ZCLK
T

ZCLK Duty Cycle

Measurement at 1.5V

/ T

ZCLK Rise and Fall Times

Measured between 0.4V and 2.4V

0.5

1.6

SKEW

Any ZCLK to Any ZCLK Clock Skew

Measurement at 1.5V

175

CCJ

ZCLK Cycle to Cycle Jitter

Measurement at 1.5V

500

PCI/PCIF
T

PCI/PCIF Duty Cycle

Measurement at 1.5V

PERIOD

PCIF/PCI Period

Measurement at 1.5V

30.0

HIGH

PCIF and PCI High Time

Measurement at 2.4V

12.0

LOW

PCIF and PCI Low Time

Measurement at 0.4V

12.0

/ T

PCIF and PCI Rise and Fall Times

Measured between 0.4V and 2.4V

0.5

2.0

SKEW

Any PCI clock to Any PCI Clock Skew

Measurement at 1.5V

500

CCJ

PCIF and PCI Cycle to Cycle Jitter

Measurement at 1.5V

500

SDCLK
T

SDCLK Duty Cycle

Measurement at 1.5V

CY28381

Document #: 38-07546 Rev. **

Page 16 of 19

PERIOD

SDCLK Period

Measurement at 1.5V

7.4

15.0

HIGH100

SDCLK High Time

Measurement at 2.4V

3.0

HIGH133

SDCLK High Time

Measurement at 2.4V

1.87

LOW100

SDCLK Low Time

Measurement at 0.4V

2.8

LOW133

SDCLK Low Time

Measurement at 0.4V

1.67

/ T

SDCLK Rise and Fall Times

Measured between 0.4V and 2.4V

0.4

1.6

CCJ

SDCLK Cycle to Cycle Jitter

Measurement at 1.5V

800

48M
T

48M Duty Cycle

Measurement at 1.5V

PERIOD

48M Period

Measurement at 1.5V

20.829

20.834

/ T

48M Rise and Fall Times

Measured between 0.4V and 2.4V

1.0

2.0

CCJ

48M Cycle to Cycle Jitter

Measurement at 1.5V

500

24M
T

24M Duty Cycle

Measurement at 1.5V

PERIOD

24M Period

Measurement at 1.5V

41.66

41.67

/ T

24M Rise and Fall Times

Measured between 0.4V and 2.4V

1.0

4.0

CCJ

24M Cycle to Cycle Jitter

Measurement at 1.5V

800

REF
T

REF Duty Cycle

Measurement at 1.5V

PERIOD

REF Period

Measurement at 1.5V

69.841

71.00

/ T

REF Rise and Fall Times

Measured between 0.4V and 2.4V

1.0

4.0

V/ns

CCJ

REF Cycle to Cycle Jitter

Measurement at 1.5V

1000

ENABLE/DISABLE and SET-UP
tpZL,tpZH

Output Enable Delay(all outputs)

1.0

10.0

tpLZ,tpZH

Output Disable Delay (all outputs)

1.0

10.0

STABLE

Clock Stabilization from Power-up

1.5

Stopclock Set-up Time

10.0

Stopclock Hold Time

AC Electrical Specifications

(continued)

Parameter

Description

Condition

Min.

Max.

Unit

Table 11. Maximum Lumped Capacitive Output Loads

Clock

Max Load

Units

PCI, PCIF

AGP, SDCLK

ZCLK

48M_24, 48M Clock

REF

CPUT,CPUC

CY28381

Document #: 38-07546 Rev. **

Page 17 of 19

Test and Measurement Set-up

For Differential CPU Output Signals

The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.

Note:

See Figure 9 for CPU clocks measurement point. SeeFigure 10 for SDCLK, AGP, ZCLK and PCI Outputs measurement point.

Table 12. CPU Clock Current Select Function

Mult0

Board Target Trace/Term Z

Reference R, Iref Vdd (3*Rr)

Output Current

Voh @ Z

50 Ohms (not used)

Rr = 221 1%, Iref = 5.00mA

Ioh = 4*Iref

1.0V @ 50

50 Ohms

Rr = 475 1%, Iref = 2.32mA

Ioh = 6*Iref

0.7V @ 50

Table 13. Group Timing Relationship and Tolerances

Offset

Tolerance

(or Range)

Conditions

Notes

CPU to SDCLK

TypicaL 0 ns

±2 ns

CPU leads

See Note 8

CPU to AGP

TypicaL 2 ns

14 ns

CPU leads

See Note 8

CPU to ZCLK

TypicaL 2 ns

14 ns

CPU leads

See Note 8

CPU to PCI

Typical 2 ns

14 ns

CPU leads

See Note 8

CPUT

M ULTSEL

PCB

CPUC

49.9

M easurem ent Point

2pF

475

IREF

M easurem ent Point

2pF

Figure 9. 0.7V Configuration

2 .4 V

0 .4 V

3 .3 V

0 V

T r

T f

1 .5 V

3 .3 V s ig n a l s

tD C

P r o b e

O u tp u t u n d e r T e s t

L o a d C a p

Figure 10. Lumped Load for Single-Ended Output Signals (for AC Parameters Measurement)

CY28381

Document #: 38-07546 Rev. **

Page 18 of 19

© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Drawing and Dimensions

Pentium is a registered trademark of Intel Corporation. Dial-a-Frequency is a registered trademark, and Dial-a-dB, Dial-a-Skew,
and Dial-a-Ratio are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are
trademarks of their respective owners.

Ordering Information

Part Number

Package Type

Product Flow

CY28381OC

48-pin Shrunk Small Outline package (SSOP)

Commercial, 0

to 70

CY28381OCT

48-pin Shrunk Small Outline package (SSOP) Tape and Reel

Commercial, 0

to 70

48-lead Shrunk Small Outline Package O48

51-85061-*C

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