FTG for Pentium 4
and Intel
845 Series Chipset
CY28378
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07519 Rev. **
Revised February 28,2003
Features
C
ompatible with Intel
CK-Titan and CK-408 Clock
Synthesizer/Driver specifications
System frequency synthesizer for Intel Brookdale 845
and Brookdale G Pentium 4
chipsets
Programmable clock output frequency with less than
1-MHz increment
Integrated fail-safe Watchdog timer for system
recovery
Automatically switch to HW selected or SW
programmed clock frequency when Watchdog timer
time-out
Programmable 3V66 and PCI output frequency mode
Capable of generating system RESET after a Watchdog
timer time-out or a change in output frequency via
SMBus interface occurs
Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
Vendor ID and Revision ID support
Programmable drive strength support
Programmable output skew support
Power management control inputs
Available in 48-pin SSOP
Table 1. Frequency Table
CPU
3V66
PCI
REF
48M
24_48M
x 3
x 4
x 10
x 2
x 1
x 1
Note:
1.
Signals marked with `*' and `**' have internal pull-up and pull-down resistors, respectively.
~
Block Diagram
VDD_REF
CPUT[0:1], CPUC[0:1],
XTAL
PLL Ref Freq
X2
X1
VDD_PCI
OSC
SCLK
PLL 1
SMBus
Logic
VDD_48MHz
SDATA
VDD_3V66
Divider
Network
VDD_CPU
*FS0:4
2
PWRDWN#
SSOP-48
REF0:1
VTT_PWRGD#
*MULTSEL1/REF1
VDD_REF
X1
X2
GND_PCI
*FS2/PCI_F0
*FS3/PCI_F1
PCI_F2
VDD_PCI
*FS4/PCI0
PCI1
PCI2
GND_PCI
PCI3
PCI4
PCI5
PCI6
VDD_PCI
VTT_PWRGD#
RESET#
GND_48MHz
*FS0/48MHz_0
*FS1/24_48MHz
VDD_48MHz
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
32
31
30
29
REF0/MULTSEL0**
GND_REF
VDD_CPU
CPU_ITP
CPU_ITP#
GND_CPU
PWRDWN#*
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
GNDC_CPU
IREF
VDD_CORE
GND_CORE
VDD_3V66
3V66_0
3V66_1
GND_3V66
3V66_2
3V66_3/48MHz_1
SCLK
SDATA
C
Y
2
837
8
*MULTSEL0:1
3V66_0:2
PCI_F0:2
PCI0:6
48MHz_0
24_48MHz
RESET#
CPU_ITP, CPU_ITP#
VDD_48MHz
3V66_3/48MHz_1
2
Fract.
Aligner
PLL2
Pin Configuration
[1]
CY28378
Document #: 38-07519 Rev. **
Page 2 of 22
Pin Description
Pin #
Name
Type
Description
3
X1
I
Crystal Connection or External Reference Frequency Input: This
pin has dual functions. It can be used as an external 14.318-MHz
crystal connection or as an external reference frequency input.
4
X2
O
Crystal Connection: Connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
48 REF0/MULTSEL0
I/O
Reference Clock 0/Current Multiplier Selection 0: 3.3V 14.318-MHz
clock output. This pin also serves as a power-on strap option to
determine the current multiplier for the CPU clock outputs. The
MULTSEL1:0 definitions are as follows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
150k internal pull down.
1
REF1/MULTSEL1
I/O
Reference Clock 1/Current Multiplier Selection 1: 3.3V 14.318-MHz
clock output. This pin also serves as a power-on strap option to
determine the current multiplier for the CPU clock outputs. The
MULTSEL1:0 definitions are as follows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
150k internal pull up.
41, 38, 40, 37
CPUT(0:1),
CPUC(0:1)
O
CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through
serial input interface.
44, 45
CPU_ITP,
CPU_ITP#
O
CPU Clock Output for ITP: Frequency is set by the FS0:4 inputs or
through serial input interface.
31, 30, 28
3V66_0:2
O
66MHz Clock Outputs: 3.3V fixed 66-MHz clock.
6 PCI_F0/FS2
I/O
Free-running PCI Output 0/Frequency Select 2: 3.3V free-running
PCI output. This pin also serves as a power-on strap option to
determine device operating frequency as described in the Frequency
Selection Table. 150k internal pull up.
7 PCI_F1/FS3
I/O
Free-running PCI Output 1/Frequency Select 3: 3.3V free-running
PCI output. This pin also serves as a power-on strap option to
determine device operating frequency as described in the Table 2.
150k internal pull up.
8
PCI_F2
O
Free-running PCI Output 2: 3.3V free-running PCI output.
10
PCI0/FS4
I/O
PCI Output 0/Frequency Select 4: 3.3V PCI output. This pin also
serves as a power-on strap option to determine device operating
frequency as described in Table 2. 150k internal pull up.
11, 12, 14, 15, 16,
17
PCI(1:6)
O
PCI Clock Output 1 to 6: 3.3V PCI clock outputs.
22
48MHz_0/FS0
I/O
48MHz Output/Frequency Select 0: 3.3V fixed 48-MHz, non-spread
spectrum output. This pin also serves as a power-on strap option to
determine device operating frequency as described in Table 2.
This output will be used as the reference clock for USB host controller
in Intel 845 (Brookdale) platforms. For Intel Brookdale G platforms,
this output will be used as the VCH reference clock. 150k internal pull
up.
CY28378
Document #: 38-07519 Rev. **
Page 3 of 22
23
24_48MHz/FS1
I/O
24 or 48MHz Output/Frequency Select 1: 3.3V fixed 24-MHz or
48-MHz non-spread spectrum output. This pin also serves as a
power-on strap option to determine device operating frequency as
described in Table 2. This output will be used as the reference clock
for SIO devices in Intel 845 (Brookdale) platforms. For Intel Brookdale
G platforms, this output will be used as the reference clock for both
USB host controller and SIO devices. We recommend system designer
to configure this output as 48 MHz and "HIGH Drive" by setting Byte
[5], Bit [0] and Byte [9], Bit [7], respectively.150k internal pull up.
27
3V66_3/48MHz_1
O
48MHz or 66MHz Output: 3.3V output.
42 PWRDWN#
I
Power Down Control: 3.3V LVTTL compatible input that places the
device in power down mode when held low. 150k internal pull up.
26
SCLK
I
SMBus Clock Input: Clock pin for serial interface.
25
SDATA
I/O
SMBus Data Input: Data pin for serial interface.
20
RESET#
O (open-drain) System Reset Output: Open-drain system reset output.
35
IREF
I
Current Reference for CPU Output: A precision resistor is attached
to this pin which is connected to the internal current reference.
19
VTT_PWRGD#
I
Powergood from Voltage Regulator Module (VRM): 3.3V LVTTL
input. VTT_PWRGD# is a level sensitive strobe used to determine
when FS0:4 and MULTSEL0:1 inputs are valid and OK to be sampled
(Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this
input will be ignored.
2, 9, 18, 24, 32, 39,
46
VDD_REF,
VDD _PCI,
VDD_48MHz,
VDD_3V66,
VDD_CPU
P
3.3V Power Connection: Power supply for CPU outputs buffers, 3V66
output buffers, PCI output buffers, reference output buffers and
48-MHz output buffers. Connect to 3.3V.
5, 13, 21, 29, 36,
43, 47
GND_PCI,
GND_48MHz,
GND_3V66,
GND_CPU,
GND_REF,
G
Ground Connection: Connect all ground pins to the common system
ground plane.
34
VDD_CORE
P
3.3V Analog Power Connection: Power supply for core logic, PLL
circuitry. Connect to 3.3V.
33
GND_CORE
G
Analog Ground Connection: Ground for core logic, PLL circuitry.
Pin Description
Pin #
Name
Type
Description
CY28378
Document #: 38-07519 Rev. **
Page 4 of 22
Table 2. Frequency Selection Table
Input Conditions
Output Frequency
VCO
Freq.
PLL Gear
Constants
(G)
FS4
FS3
FS2
FS1
FS0
CPU
3V66
PCI
SEL4
SEL3
SEL2
SEL1
SEL0
0
0
0
0
0
100.7
67.1
33.6
402.80
47.99750
0
0
0
0
1
100.9
67.3
33.6
403.60
47.99750
0
0
0
1
0
108.0
72.0
36.0
432.00
47.99750
0
0
0
1
1
101.2
67.5
33.7
404.80
47.99750
0
0
1
0
0
114.0
76.0
38.0
456.00
47.99750
0
0
1
0
1
117.0
78.0
39.0
468.00
47.99750
0
0
1
1
0
120.0
80.0
40.0
480.00
47.99750
0
0
1
1
1
123.0
82.0
41.0
492.00
47.99750
0
1
0
0
0
125.7
62.9
31.4
377.12
63.99667
0
1
0
0
1
130.3
65.1
32.6
390.80
63.99667
0
1
0
1
0
133.9
67.0
33.5
401.70
63.99667
0
1
0
1
1
134.2
67.1
33.6
402.60
63.99667
0
1
1
0
0
134.5
67.3
33.6
403.50
63.99667
0
1
1
0
1
148.0
74.0
37.0
444.00
63.99667
0
1
1
1
0
152.0
76.0
38.0
456.00
63.99667
0
1
1
1
1
156.0
78.0
39.0
468.00
63.99667
1
0
0
0
0
160.0
80.0
40.0
480.00
63.99667
1
0
0
0
1
164.0
82.0
41.0
492.00
63.99667
1
0
0
1
0
167.4
66.9
33.5
334.80
95.99500
1
0
0
1
1
170.0
68.0
34.0
340.00
95.99500
1
0
1
0
0
175.0
70.0
35.0
350.00
95.99500
1
0
1
0
1
180.0
72.0
36.0
360.00
95.99500
1
0
1
1
0
185.0
74.0
37.0
370.00
95.99500
1
0
1
1
1
190.0
76.0
38.0
380.00
95.99500
1
1
0
0
0
166.8
66.7
33.4
333.60
95.99500
1
1
0
0
1
100.2
66.8
33.4
400.80
47.99750
1
1
0
1
0
133.6
66.8
33.4
400.80
63.99667
1
1
0
1
1
200.4
66.8
33.4
400.80
95.99500
1
1
1
0
0
166.6
66.6
33.3
333.33
95.99500
1
1
1
0
1
100.0
66.6
33.3
400.00
47.99750
1
1
1
1
0
200.0
66.6
33.3
400.00
95.99500
1
1
1
1
1
133.3
66.6
33.3
400.00
63.99667
Swing Select Functions
MULTSEL1
MULTSEL0
Board Target
Trace/Term Z
Reference R, IREF
=
VDD/(3*Rr)
Output
Current
V
OH
@ Z
0
0
50
Rr = 221 1%,
IREF = 5.00 mA
I
OH
= 4*Iref
1.0V @ 50
1
0
50
Rr = 475 1%,
IREF = 2.32 mA
I
OH
= 6*Iref
0.7V @ 50
CY28378
Document #: 38-07519 Rev. **
Page 5 of 22
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface (SDI), various device functions such as
individual clock output buffers, etc. can be individually enabled
or disabled.
The register associated with the SDI initializes to it's default
setting upon power-up, and therefore use of this interface is
optional. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power
management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write and block read operation from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol.
The slave receiver address is 11010010 (D2h).
Table 3. Command Code Definition
Bit
Descriptions
7
0 = Block read or block write operation
1 = Byte read or byte write operation
6:0
Byte offset for byte read or byte write operation. For block read or block write operations, these
bits should be `0000000'.
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address 7 bits
2:8
Slave address 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code 8 Bit
'00000000' stands for block operation
11:18
Command Code 8 Bit
'00000000' stands for block operation
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte Count 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address 7 bits
29:36
Data byte 1 8 bits
28
Read = 1
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 2 8 bits
30:37
Byte count from slave 8 bits
46
Acknowledge from slave
38
Acknowledge
....
......................
39:46
Data byte from slave 8 bits
....
Data Byte (N1) 8 bits
47
Acknowledge
....
Acknowledge from slave
48:55
Data byte from slave 8 bits
....
Data Byte N 8 bits
56
Acknowledge
....
Acknowledge from slave
....
Data bytes from slave/Acknowledge
....
Stop
....
Data byte N from slave 8 bits
....
Not Acknowledge
....
Stop
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