Advance Information
Dual Output 125-MHz
Clock Generator
CY26126
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07351 Rev. *A
Revised December 14, 2002
5
Features
Benefits
Integrated phase-locked loop
Highest-performance PLL tailored for multimedia applications
Low skew, low jitter, high accuracy outputs
Meets critical timing requirements in complex system designs
3.3V Operation
Part Number
Outputs
Input Frequency Range
Output Frequencies
CY26126
2
25 MHz
2 copies of 125 MHz (3.3V)
Logic Block Diagram
25 XIN
XOUT
OUTPUT
MULTIPLEXER
AND
DIVIDERS
PLL
OSC.
Q
P
VCO
VDD
VSS
P Comp
125 MHz
OE
125 MHz
8-pin SOIC
CY26126
Pin Configurations
1
2
3
4
XOUT
XIN
CLKA
VSS
CLKB
VSS
5
6
7
8
VDD
OE
CY26126
Advance Information
Document #: 38-07351 Rev. *A
Page 2 of 5
Notes:
1.
Float XOUT pin if XIN is driven by reference clock (as opposed to crystal).
2.
Rated for 10 years.
Pin Summary
Name
Pin Number
Description
XIN
1
Reference Input
VDD
2
3.3V Voltage Supply
OE
3
Output Enable
VSS
4
Ground
VSS
5
Ground
CLKA
6
125-MHz Clock Output A
CLKB
7
125-MHz Clock Output B
XOUT
[1]
8
Reference Output
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit.
V
DD
Supply Voltage
0.5
7.0
V
T
S
Storage Temperature
[2]
65
125
C
T
J
Junction Temperature
125
C
Digital Inputs
V
SS
0.3
V
DD
+ 0.3
V
Digital Outputs referred to V
DD
V
SS
0.3
V
DD
+ 0.3
V
Electro-Static Discharge
2
kV
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
Operating Voltage
3.14
3.3
3.47
V
T
A
Ambient Temperature
0
70
C
C
LOAD
Max. Load Capacitance
15
pF
P
max
Max. Output Power Dissipation
150
mW
f
REF
Reference Frequency
25
MHz
t
PU
Power-up time for all VDD's to
reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
ms
DC Electrical Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
I
OH
Output High Current
V
OH
= V
DD
0.5, V
DD
= 3.3V
12
24
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DD
= 3.3V
12
24
mA
V
IH
Input High Voltage
CMOS Levels 70% of V
DD
0.7
V
DD
V
IL
Input Low Voltage
CMOS Levels 30% of V
DD
0.3
V
DD
C
IN
Input Capacitance
7
pF
I
IZ
Input Leakage Current
5
A
I
DD
Supply Current
Sum of Core and Output Current
35
mA
CY26126
Advance Information
Document #: 38-07351 Rev. *A
Page 3 of 5
Note:
3.
Not 100% tested.
AC Electrical
Characteristics
(V
DD
= 3.3V)
[3]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of V
DD
45
50
55
%
t3
Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of V
DD
0.8
1.4
V/ns
t4
Falling Edge Slew
Rate
Output Clock Fall Time, 80% - 20% of V
DD
0.8
1.4
V/ns
t9
Clock Jitter
Peak to Peak period jitter
200
ps
t10
PLL Lock Time
3
ms
Test Circuit
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY26126SC
S8
8-Pin SOIC
Commercial
3.3V
0.1
F
V
DD
0.1
F
V
DD
CLK out
C
LOAD
GND
OUTPUTS
t1
t2
CLK
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
CLK
80%
20%
t4
Figure 2. Rise and Fall Time Definitions
CY26126
Advance Information
Document #: 38-07351 Rev. *A
Page 4 of 5
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
8-Lead (150-Mil) SOIC S8
51-85066-A
CY26126
Advance Information
Document #: 38-07351 Rev. *A
Page 5 of 5
Document Title: CY26126 Dual Output 125-MHz Clock Generator
Document Number: 38-07351
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
112233
03/01/02
CKN
New data sheet
*A
121891
12/14/02
RBI
Power up requirements added to Operating Conditions Information
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