CY24133
PRELIMINARY
MediaClockTM
Digital TV Clock Generator with VCXO
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07497 Rev. **
Revised February 3, 2003
Features
Benefits
Low jitter, high-accuracy outputs
Meets critical timing requirements in complex system designs
VCXO with analog adjust
Large 150-ppm range, better linearity
3.3V operation
Enables application compatibility
Frequency Table
Part Number
Outputs
Input Frequency Range
Output Frequency Range
CY24133-1
2
27-MHz pullable Crystal per
Cypress Specification
3.072-, 4.096-, 6.144-, 11.2896-, 12.288-MHz-selectable output
frequencies and 27-MHz reference output
Logic Block Diagram
XIN
XOUT
CLKOUT
PLL
ROM
OSC
REFCLK
Q
P
VCO
AVDD
VSS
VCXO
VDDL VSSL
VDD AVSS
FS0
FS1
16-pin TSSOP
CY24133-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDDL
VSSL
VCXO
REFCLK
NC
CLKOUT
FS0
XOUT
NC
XIN
VDD
FS1
FS2
VSS
AVDD
AVSS
Pin Configuration
FS2
Output
and Dividers
Multiplexer
PRELIMINARY
CY24133
Document #: 38-07497 Rev. **
Page 2 of 5
Pin Description
Name
Pin Number
Description
XIN
1
Reference Crystal Input
V
DD
2
Voltage Supply
A
VDD
3
Analog Voltage Supply
VCXO
4
Input Analog Control Voltage for VCXO
AV
SS
5
Analog Ground
V
SSL
6
Output Clock Ground
FS2
7
Frequency Select 2
FS1
8
Frequency Select 1
CLKOUT
9
Configurable Clock Output 1 at VDDL level
FS0
10
Frequency Select 0
VDDL
11
Clock Output Voltage Supply
REFCLK
12
Reference Clock Output at VDDL level
VSS
13
Ground
NC
14
No Connect
NC
15
No Connect
XOUT
[1]
16
Reference Crystal Output
Frequency Select Table--CY24133-1
FS2
FS1
FSO
CLKOUT
REFCLK
0
0
0
3.072
27
0
0
1
4.096
27
0
1
0
6.144
27
0
1
1
11.2896
27
1
0
0
12.288
27
1
0
1
off
off
1
1
0
off
off
1
1
1
off
off
Pullable Crystal Specifications
Parameter
Name
Min.
Typ.
Max.
Unit
CR
load
Crystal Load Capacitance
14
pF
C0/C1
250
ESR
Equivalent Series Resistance
35
50
T
o
Operating Temperature
0
70
C
Crystal Accuracy
Crystal Accuracy
+20
ppm
TT
s
Stability over temperature and aging
+50
ppm
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
0.5
7.0
V
V
DDL
I/O Supply Voltage
0.5
7.0
V
T
S
Storage Temperature
[2]
65
125
C
T
J
Junction Temperature
125
C
Notes:
1.
Float X
OUT
if X
IN
is externally driven.
2.
Rated for 10 years.
PRELIMINARY
CY24133
Document #: 38-07497 Rev. **
Page 3 of 5
Digital Inputs
AV
SS
0.3
AV
DD
+ 0.3
V
Analog Input referred to AV
DD
AV
SS
0.3
AV
DD
+ 0.3
V
Electrostatic Discharge
2
kV
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
AV
DD
/V
DD
/V
DDL
Operating Voltage
3.135
3.3
3.456
V
T
A
Ambient Temperature
0
70
C
C
LOAD
Max. Load Capacitance
V
DD
/V
DDL
=3.3V
15
pF
f
REF
Reference Frequency
27
MHz
DC Electrical Specifications
Parameter
[3]
Name
Description
Min.
Typ.
Max.
Unit
I
OH
Output High Current
V
OH
= V
DD
0.5, V
DD
/V
DDL
= 3.3V
12
24
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DD
/V
DDL
= 3.3V
12
24
mA
V
IH
Input High Voltage
CMOS levels
0.7
VDD
V
IL
Input Low Voltage
CMOS levels
0.3
VDD
C
IN
Input Capacitance
Frequency Select Pins
7
pF
f
XO
VCXO pullability range
+150
ppm
V
VCXO
VCXO input range
0
AV
DD
V
I
DD
Supply Current
AV
DD
/V
DD
/V
DDL
Current
18
25
mA
AC Electrical Specifications
Parameter
[3]
Name
Description
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of V
DD
45
50
55
%
ER
Rising Edge Rate
Output Clock Edge Rate, Measured from 20% to
80% of V
DD
, C
LOAD
= 15 pF See Figure 2.
0.8
1.4
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 80% to
20% of V
DD
, C
LOAD
= 15 pF See Figure 2.
0.8
1.4
V/ns
t
9
Clock Jitter
Peak-to-Peak period jitter on CLKOUT
350
ps
t
10
PLL Lock Time
Measured from V
DD
= 3.0V
3
ms
Test and Measurement Set-up
Note:
3.
Guaranteed by design, not 100% tested.
Absolute Maximum Conditions
(continued)
Parameter
Description
Min.
Max.
Unit
0.1
F
V
DDs
Outputs
C
LOAD
GND
DUT
CY24133
PRELIMINARY
Document #: 38-07497 Rev. **
Page 4 of 5
Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Drawing and Dimensions
MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
may be the trademarks of their respective holders.
Voltage and Timing Definitions
Figure 1. Duty Cycle Definition
Figure 2. ER = (0.6 x V
DD
) /t3, EF = (0.6 x V
DD
) /t4
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY24133ZC-1
Z16
16-pin TSSOP
Commercial
3.3V
CY24133ZC-1T
Z16
16-pin TSSOP Tape and Reel
Commercial
3.3V
Clock
Output
V
DD
50% of V
DD
0V
t
1
t
2
Clock
Output
t
3
t
4
V
DD
80% of V
DD
20% of V
DD
0V
16-
l
ead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
51-85091-**
PRELIMINARY
CY24133
Document #: 38-07497 Rev. **
Page 5 of 5
Document History Page
Document Title: CY24133 MediaClockTM Digital TV Clock Generator with VCXO
Document Number: 38-07497
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
121554
02/17/03
CKN
New Data Sheet
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ZIP