MediaClockTM
MPEG Clock Generator with VCXO
CY2411
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07193 Rev. *B
Revised December 14, 2002
Note:
1.
Float X
OUT
if X
IN
is externally driven.
Features
Benefits
Integrated phase-locked loop (PLL)
Highest-performance PLL tailored for multimedia applications
Low-jitter, high-accuracy outputs
Meets critical timing requirements in complex system designs
VCXO with analog adjust
Large 150 ppm range, better linearity
3.3V operation
Part Number
Outputs
Input Frequency Range
Output Frequencies
CY2411-1
1
13.5-MHz Pullable Crystal per
Cypress Specification
1 copy of 54 MHz (3.3V)
Pin Summary
Pin Name
Pin Number
Pin Description
A
VDD
2
Analog Voltage Supply
V
DD
5
Output Voltage Supply
AV
SS
4
Analog Ground
V
SS
7
Output Ground
X
IN
1
Reference Crystal Input
V
CXO
3
Analog Control for V
CXO
X
OUT
[1]
8
Reference Crystal Output
54 MHz
6
54-MHz clock output
Logic Block Diagram
Pin Configuration
13.5 XIN
XOUT
54 MHz
OUTPUT
DIVIDER
PLL
OSC
VCXO
Q
P
VCO
VDD
AVSS
AVDD
VSS
8-pin SOIC
CY2411
1
2
3
4
XOUT
XIN
VCXO
54 MHz
AVSS
VSS
VDD
5
6
7
8
AVDD
CY2411
Document #: 38-07193 Rev. *B
Page 2 of 5
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
0.5
7.0
V
T
S
Storage Temperature
[2]
65
125
C
T
J
Junction Temperature
125
C
Digital Inputs
V
SS
0.3
V
DD
+ 0.3
V
Digital Outputs Referred to V
DD
V
SS
0.3
V
DD
+ 0.3
V
Electro-Static Discharge
2000
V
Recommended
Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
Operating Voltage
3.15
3.3
3.45
V
T
A
Ambient Temperature
0
70
C
C
LOAD
Max Load Capacitance
15
pF
f
REF
Reference Frequency
13.5
13.5
13.5
MHz
t
PU
Power-up time for all VDD's to
reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
ms
Pullable Crystal Specifications
Parameter
Description
Min.
Typ.
Max.
Unit
CR
load
Crystal Load Capacitance
12.4
pF
C0/C1
240
ESR
Equivalent Series Resistance
35
50
T
o
Operating Temperature
0
70
C
Crystal Accuracy
Crystal Accuracy
+ 20
ppm
TT
s
Stability over Temperature and
Aging
+ 20
+ 50
ppm
DC
Electrical Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
I
OH
Output High Current
V
OH
= V
DD
0.5, V
DD
= 3.3 V (source)
12
24
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DD
= 3.3 V (sink)
12
24
mA
C
IN
Input Capacitance
7
pF
I
IZ
Input Leakage Current
5
A
f
xo
V
CXO
Pullability Range
150
+150
ppm
V
VCXO
V
CXO
Input Range
0
AV
DD
V
I
DD
Supply Current
V
DD
= 3.45V, Cload = 15pF
15
20
mA
AC Electrical
Characteristics
(V
DD
= 3.3V)
Parameter
[3]
Description
Conditions
Min.
Typ.
Max.
Unit
DC = t
2
/t
1
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of V
DD
45
50
55
%
ER
0
Rising Edge Rate
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD,
Cload = 15 pF (see Figure 2)
0.8
1.4
V/ns
EF
0
Falling Edge Rate
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD,
Cload = 15 pF (see Figure 2)
0.8
1.4
V/ns
t
9
Clock Jitter
Peak to Peak period jitter
200
ps
CY2411
Document #: 38-07193 Rev. *B
Page 3 of 5
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
t
10
PLL Lock Time
3
ms
Notes:
2.
Rated for 10 years.
3.
Not 100% tested.
AC Electrical
Characteristics
(V
DD
= 3.3V)
Parameter
[3]
Description
Conditions
Min.
Typ.
Max.
Unit
t
1
t
2
54 MHz
50%
Figure 1. Duty Cycle Definition; DC = t
2
/t
1
t3
54 MHz
80%
20%
t
4
Figure 2. Rise and Fall Time Definitions:
ER = 0.6 V
DD
/t3, EF = 0.6 V
DD
/t4
Test Circuit
Ordering Information
Ordering Code
Package
Name
Package Type
Operating Range
Operating Voltage
CY2411SC-1
S8
8-pin SOIC
Commercial
3.3V
CY2411SC-1T
S8
8-pin SOICTape and Reel
Commercial
3.3V
0.1
F
AV
DD
0.1
F
V
DD
CLK out
C
LOAD
GND
OUTPUTS
CY2411
Document #: 38-07193 Rev. *B
Page 4 of 5
MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Pin Diagrams
8-lead (150-mil) SOIC S8
51-85066-A
CY2411
Document #: 38-07193 Rev. *B
Page 5 of 5
Document Title: CY2411 54-MHz MPEG Clock Generator with VCXO
Document Number: 38-07193
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110594
11/07/01
DSG
Change from Spec number: 38-00957 to 38-07193
*A
111572
04/30/02
CKN
Changed title to "MPEG Clock Generator with VCXO"
Added -1 data on pp. 1 and 3
*B
121875
12/14/02
RBI
Power up requirements added to Operating Conditions Information
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