200-MHz Field Programmable Zero Delay Buffer
CY23FP12
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07246 Rev. *C
Revised May 22, 2003
Features
Fully field-programmable:
-- Input and output dividers
-- Inverting/noninverting outputs
-- Phase-locked loop (PLL) or fanout buffer configu-
ration
10-MHz to 200-MHz operating range
Split 2.5V or 3.3V outputs
Total Timing Budget
(TTB)
@ 200 MHz < 650 ps
Two LVCMOS reference inputs
Twelve low-skew outputs
-- Output-output skew < 200 ps
-- Device-device skew < 500 ps
Input-output skew < 250 ps
Cycle-cycle jitter < 100 ps (typical)
Three-stateable outputs
< 50-
A shutdown current
Spread Aware
28-pin SSOP
3.3V operation
Industrial temperature available
Functional Description
The CY23FP12 is a high-performance fully field-program-
mable 200-MHz zero delay buffer designed for high speed
clock distribution. The integrated PLL is designed for low jitter
and optimized for noise rejection. These parameters are
critical for reference clock distribution in systems using high-
performance ASICs and microprocessors.
The CY23FP12 is fully programmable via volume or prototype
programmers enabling the user to define an application-
specific Zero Delay Buffer with customized input and output
dividers, feedback topology (internal/external), output inver-
sions, and output drive strengths. For additional flexibility, the
user can mix and match multiple functions, listed in Table 2,
and assign a particular function set to any one of the four
possible S1-S2 control bit combinations. This feature allows
for the implementation of four distinct personalities, selectable
with S1-S2 bits, on a single programmed silicon. The
CY23FP12 also features a proprietory auto-power-down
circuit that shuts down the device in case of a REF failure,
resulting in less than 50-
A of current draw.
The CY23FP12 provides twelve outputs grouped in two banks
with separate power supply pins which can be connected
independently to either a 2.5V or a 3.3V rail.
21
28
REFSEL
FBK
CLKA0
CLKA1
V
SSA
CLKA2
CLKA3
V
DDA
1
2
3
4
5
6
7
8
22
23
24
25
26
27
REF2
REF1
CLKB0
CLKB1
V
SSB
CLKB2
CLKB3
V
DDB
SSOP
Top View
Pin Configuration
17
V
DDA
20
V
SSA
19
CLKA4
18
CLKA5
16
V
SSC
15
S1
9
V
SSB
12
V
DDB
13
V
DDC
10
CLKB4
11
CLKB5
14
S2
FBK
M
N
100 to
400MHz
PLL
CLKA1
CLKA3
CLKA2
REF2
REFSEL
CLKA4
CLKA5
CLKB1
CLKB3
CLKB2
CLKB4
CLKB5
VDDA
VSSA
VDDB
VSSB
2
3
4
X
CLKA0
VDDC
VSSC
1
Lock Detect
Test Logic
REF1
CLKB0
S[2:1]
Function
Selection
Block Diagram
CY23FP12
Document #: 38-07246 Rev. *C
Page 2 of 10
.
Pin Description
Pin
Name
I/O
Type
Description
1
REF2
I
LVTTL/LVCMOS
Input reference frequency, 5V-tolerant input
2
REF1
I
LVTTL/LVCMOS
Input reference frequency, 5V-tolerant input
3
CLKB0
O
LVTTL
Clock output, Bank B
4
CLKB1
O
LVTTL
Clock output, Bank B
5
V
SSB
PWR
POWER
Ground for Bank B
6
CLKB2
O
LVTTL
Clock output, Bank B
7
CLKB3
O
LVTTL
Clock output, Bank B
8
V
DDB
PWR
POWER
2.5V or 3.3V supply, Bank B
9
V
SSB
PWR
POWER
Ground for Bank B
10
CLKB4
O
LVTTL
Clock output, Bank B
11
CLKB5
O
LVTTL
Clock output, Bank B
12
V
DDB
PWR
POWER
2.5V or 3.3V supply, Bank B
13
V
DDC
PWR
POWER
3.3V core supply
14
S2
I
LVTTL
Select input
15
S1
I
LVTTL
Select input
16
V
SSC
PWR
POWER
Ground for Bank B
17
V
DDA
PWR
POWER
2.5V or 3.3V supply, Bank A
18
CLKA5
O
LVTTL
Clock output, Bank A
19
CLKA4
O
LVTTL
Clock output, Bank A
20
V
SSA
PWR
POWER
Ground for Bank A
21
V
DDA
PWR
POWER
2.5V or 3.3V supply Bank A
22
CLKA3
O
LVTTL
Clock output, Bank A
23
CLKA2
O
LVTTL
Clock output, Bank A
24
V
SSA
PWR
POWER
Ground for Bank A
25
CLKA1
O
LVTTL
Clock output, Bank A
26
CLKA0
O
LVTTL
CLock output, Bank A
27
FBK
I
LVTTL
PLL feedback input
28
REFSEL
I
LVTTL
Reference select input. When Low REF1 is selected.
CY23FP12
Document #: 38-07246 Rev. *C
Page 3 of 10
Below is a list of independent functions that can be
programmed with a volume or prototype programmer on the
"default" silicon.
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
PLL
/M
/N
Output
Function
Select
Matrix
REF
FBK
CLKB5
CLKB4
CLKB3
CLKB2
CLKB1
CLKB0
CLKA5
CLKA4
CLKA3
CLKA2
CLKA1
CLKA0
Figure 1. Basic PLL Block Diagram
Table 1.
Configuration
Description
Default
DC Drive Bank A
Programs the drive strength of Bank A outputs. The user can select one out
of four possible drive strength settings that produce output DC currents in the
range of 16 mA to 20 mA.
+16 mA
DC Drive Bank B
Programs the drive strength of Bank B outputs. The user can select one out
of four possible drive strength settings that range from +16 mA to +20 mA in
terms of output DC current.
+16 mA
Output Enable for Bank B clocks
Enables/Disables CLKB[5:0] outputs. Each of the six outputs can be disabled
individually if not used, to minimize electromagnetic interference (EMI) and
switching noise.
Enable
Output Enable for Bank A clocks
Enables/Disables CLKA[5:0] outputs. Each of the six outputs can be disabled
individually if not used, to minimize EMI and switching noise.
Enable
Inv CLKA0
Generates an inverted clock on the CLKA0 output. When this option is
programmed, CLKA0 and CLKA1 will become complimentary pairs.
Non-invert
Inv CLKA2
Generates an inverted clock on the CLKA2 output. When this option is
programmed, CLKA2 and CLKA3 will become complimentary pairs.
Non-invert
Inv CLKA4
Generates an inverted clock on the CLKA4 output. When this option is
programmed, CLKA4 and CLKA5 will become complimentary pairs.
Non-invert
Inv CLKB0
Generates an inverted clock on the CLKB0 output. When this option is
programmed, CLKB0 and CLKB1 will become complimentary pairs.
Non-invert
Inv CLKB2
Generates an inverted clock on the CLKB2 output. When this option is
programmed, CLKB2 and CLKB3 will become complimentary pairs.
Non-invert
CY23FP12
Document #: 38-07246 Rev. *C
Page 4 of 10
Below is a list of independent functions, which can be
assigned to each of the four S1 and S2 combinations. When
a particular S1 and S2 combination is selected, the device will
assume the configuration (which is essentially a set of
functions given in Table 2, below) that has been preassigned
to that particular combination.
Inv CLKB4
Generates an inverted clock on the CLKB4 output. When this option is
programmed, CLKB4 and CLKB5 will become complimentary pairs.
Non-invert
Pull-down Enable
Enables/Disables internal pulldowns on all outputs
Enable
Fbk Pull-down Enable
Enables/Disables internal pulldowns on the feedback path (applicable to both
internal and external feedback topologies)
Enable
Fbk Sel
Selects between the internal and the external feedback topologies
External
Table 1. (continued)
Configuration
Description
Default
Table 2.
Function
Description
Default
Output Enable CLKB[5:4] Enables/Disables CLKB[5:4] output pair
Enable
Output Enable CLKB[3:2] Enables/Disables CLKB[3:2] output pair
Enable
Output Enable CLKB[1:0] Enables/Disables CLKB[1:0] output pair
Enable
Output Enable CLKA[5:4] Enables/Disables CLKA[5:4] output pair
Enable
Output Enable CLKA[3:2] Enables/Disables CLKA[3:2] output pair
Enable
Output Enable CLKA[1:0] Enables/Disables CLKA[1:0] output pair
Enable
Auto Power-down Enable Enables/Disables the auto power down circuit, which monitors the reference clock rising
edges and shuts down the device in case of a reference "failure." This failure is triggered
by a drift in reference frequency below a set limit. This auto power down circuit is
disabled internally when one or more of the outputs are configured to be driven directly
from the reference clock.
Enable
PLL Power-down
Shuts down the PLL when the device is configured as a non-PLL fanout buffer.
PLL Enabled
M[7:0]
Assigns an eight-bit value to reference divider M. The divider can be any integer value
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
2
N[7:0]
Assigns an eight-bit value to feedback divider N. The divider can be any integer value
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
2
X[6:0]
Assigns a seven-bit value to output divider X. The divider can be any integer value
from 5 to 127. Divide by 1,2,3, and 4 are preprogrammed on the device and can be
activated by the appropriate output mux setting.
1
Divider Source
Selects between the PLL output and the reference clock as the source clock for the
output dividers.
PLL
CLKA54 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKA5 and CLKA4 pair. Please refer to Table 3 for a list of divider values.
Divide by 2
CLKA32 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKA3 and CLKA2 pair. Please refer to Table 3 for a list of divider values.
Divide by 2
CLKA10 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKA1 and CLKA0 pair. Please refer to Table 3 for a list of divider values.
Divide by 2
CLKB54 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKB5 and CLKB4 pair. Please refer to Table 3 for a list of divider values.
Divide by 2
CLKB32 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKB3 and CLKB2 pair. Please refer to Table 3 for a list of divider values.
Divide by 2
CLKB10 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKB1 and CLKB0 pair. Please refer to Table 3 for a list of divider values.
Divide by 2
CY23FP12
Document #: 38-07246 Rev. *C
Page 5 of 10
Table 3 is a list of output dividers that are independently
selected to connect to each output pair.
In the default (non-programmable) state of the device, S1 and
S2 pins will function, as indicated in Table 4.
Field Programming the CY23FP12
The CY23FP12 is programmed at the package level, i.e. in a
programmer socket. The CY23FP12 is flash-technology
based, so the parts can be reprogrammed up to 100 times.
This allows for fast and easy design changes and product
updates, and eliminates any issues with old and out-of-date
inventory.
Samples and small prototype quantities can be programmed
on the CY3672 programmer. Cypress's value-added distri-
bution partners and third-party programming systems from BP
Microsystems, HiLo Systems, and others are available for
large production quantities.
CyClocksRT
Software
CyClocksRT is an easy-to-use software application that allows
the user to custom-configure the CY23FP12. Users can
specify the REF, PLL frequency, output frequencies and/or
post-dividers, and different functional options. CyClocksRT
outputs an industry standard JEDEC file used for
programming the CY23FP12.
CyClocksRT can be downloaded free of charge from the
Cypress website at www.cypress.com.
CY3672 FTG Development Kit
The Cypress CY3672 FTG Development Kit comes complete
with everything needed to design with the CY23FP12 and
program samples and small prototype quantities. The kit
comes with the latest version of CyClocksRT and a small
portable programmer that connects to a PC serial port for on-
the-fly programming of custom frequencies.
The JEDEC file output of CyClocksRT can be downloaded to
the portable programmer for small-volume programming, or
for use with a production programming system for larger
volumes.
CY23FP12 Frequency Calculation
The CY23FP12 is an extremely flexible clock buffer with up to
twelve individual outputs, generated from an integrated PLL.
There are four variables used to determine the final output
frequency. These are the input Reference Frequency M, the N
dividers, and the post divider X.
The basic PLL block diagram is shown in Figure 1. Each of the
six clock outputs pair has many output options available to it.
There are six post divider options: /1, /2, /3, /4, /X, and /2X.
The post divider options can be applied to the calculated PLL
frequency or to the REF directly. The feedback either is
connected to CLKA0 internally or connected to any output
externally.
A programmable divider, M, is inserted between the reference
input, REF, and the phase detector. The divider M can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
A programmable divider, N, is inserted between the feedback
input, FBK, and the phase detector. The divider N can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
So the output can be calculated as following:
F
REF
/ M = F
FBK
/ N.
F
PLL
= (F
REF
* N *
post divider)/M.
F
OUT
= F
PLL
/ post divider.
In addition to above divider options, the another option
bypasses the PLL and passes the REF directly to the output.
F
OUT
= F
REF
.
Note:
1.
This device setting will not provide synchronous output.
Table 3.
CLKA/B Source
Output Connects To
0 [000]
REF
1 [001]
Divide by 1
2 [010]
Divide by 2
3 [011]
Divide by 3
4 [100]
Divide by 4
5 [101]
Divide by X
6 [110]
Divide by 2X
[1]
7 [111]
TEST mode [LOCK signal]
Table 4.
S2
S1
CLKA[5:0]
CLKB[5:0]
Output
Source
0
0
Three-state
Three-state
PLL
0
1
Driven
Three-state
PLL
1
0
Driven
Driven
Reference
1
1
Driven
Driven
PLL
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