Phase-Aligned Clock Multiplier
CY2300
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07252 Rev. *B
Revised July 26, 2004
Features
4-multiplier configuration
Single phase-locked loop architecture
Phase Alignment
Low jitter, high accuracy outputs
Output enable pin
3.3V operation
5V Tolerant input
Internal loop filter
8-pin 150-mil SOIC package
Commercial and Industrial Temperature available
Benefits
1/2x, 1x, 1x, 2x Ref
10 MHz to 166.67 MHz operating range (reference input
from 20 MHz to 83.33 MHz)
All outputs will have a consistent phase relationship
with each other and the reference input
Meets critical timing requirements
Enables design flexibility and lower power
consumption
Supports industry standard design platforms
Allows flexibility on Reference input
Alleviates the need for external components
Industry standard packaging saves on board space
Suitable for wide spectrum of applications
Selector Guide
Part Number
Outputs
Input Frequency Range
Output Frequency Range
Specifics
CY2300SC
4
20 MHz83.33 MHz
10 MHz166.67 MHz
Commercial Temperature
CY2300SI
4
20 MHz83.33 MHz
10 MHz166.6 7MHz
Industrial Temperature
PLL
1/2xREF
2xREF
REFIN
1
2
3
4
5
8
7
6
1/2xREF
GND
REFIN
REF
V
DD
OE
REF
Top View
8-pin SOIC
2xREF
REF
Block Diagram
Pin Configuration
Divider
Logic
FBK
/2
OE
REF
CY2300
Document #: 38-07252 Rev. *B
Page 2 of 7
Functional Description
The CY2300 is a 4-output 3.3V phase-aligned system clock
designed to distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance applications.
The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN
output frequencies on respective output pins.
The part has an on-chip PLL which locks to an input clock
presented on the REFIN pin. The input-to-output skew is guar-
anteed to be less than
200 ps, and output-to-output skew is
guaranteed to be less than 200 ps.
Multiple CY2300 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 400 ps.
The CY2300 is available in commercial and industrial temper-
ature ranges.
Maximum Ratings
Supply Voltage to Ground Potential ...............0.5V to +7.0V
DC Input Voltage (Except Ref) .............. 0.5V to V
DD
+ 0.5V
DC Input Voltage REF ........................................... 0.5 to 7V
Storage Temperature ................................. 65C to +150C
Junction Temperature.................................................. 150C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
Pin Definitions
Pin
Signal
[1]
Description
1
1/2xREF
Clock output, 1/2x Reference
2
GND
Ground
3
REFIN
Input Reference frequency, 5V tolerant input
4
REF
Clock output Reference
5
REF
Clock output Reference
6
2xREF
Clock output, 2x Reference
7
VDD
3.3V Supply
8
OE
Output Enable (weak pull-up)
Operating Conditions for CY2300SC Commercial Temperature Devices
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
3.0
3.6
V
T
A
Operating Temperature (Ambient Temperature)
0
70
C
C
L
Load Capacitance, Fout < 133.33 MHz
18
pF
Load Capacitance,133.33 MHz < Fout < 166.67 MHz
12
pF
C
IN
Input Capacitance
7
pF
t
PU
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
0.05
50
ms
Electrical Characteristics for CY2300SC Commercial Temperature Devices
Parameter
Description
Min.
Max.
Unit
V
IL
Input LOW Voltage
0.8
V
V
IH
Input HIGH Voltage
2.0
V
I
IL
Input LOW Current
V
IN
= 0V
100
A
I
IH
Input HIGH Current
V
IN
= V
DD
50
A
V
OL
Output LOW Voltage
[2]
I
OL
= 8 mA
0.4
V
V
OH
Output HIGH Voltage
[2]
I
OH
= 8 mA
2.4
V
I
DD
Supply Current
Unloaded outputs, REFIN = 66 MHz
45
mA
Unloaded outputs, REFIN = 33 MHz
32
mA
Unloaded outputs, REFIN = 20 MHz
18
mA
Notes:
1.
Weak pull-down on all outputs.
2.
Parameter is guaranteed by design and characterization. It is not 100% tested in production.
CY2300
Document #: 38-07252 Rev. *B
Page 3 of 7
Switching Characteristics for CY2300SC Commercial Temperature Devices
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
1/t
1
Output Frequency
18-pF load
10
133.33
MHz
12-pF load
166.67
MHz
Duty Cycle
[3]
= t
2
t
1
Measured at V
DD
/2 40
50
60
%
t
3
Rise Time
[3]
Measured between 0.8V and 2.0V
1.20
ns
t
4
Fall Time
[3]
Measured between 0.8V and 2.0V
1.20
ns
t
5
Output to Output Skew on rising
edges
[3]
All outputs equally loaded
Measured at V
DD
/2
200
ps
t
6
Delay, REFIN Rising Edge to Out-
put Rising Edge
[3]
Measured at V
DD
/2 from REFIN to any
output
200
ps
t
7
Device to Device Skew
[3]
Measured at V
DD
/2 on the 1/2xREF pin of
devices (pin 1)
400
ps
t
J
Period Jitter
[3]
Measured at Fout=133.33 MHz, loaded
outputs, 18-pF load
175
ps
t
LOCK
PLL Lock Time
[3]
Stable power supply, valid clocks pre-
sented on REFIN
1.0
ms
Operating Conditions for CY2300SI Industrial Temperature Devices
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
3.0
3.6
V
T
A
Operating Temperature (Ambient Temperature)
40
85
C
C
L
Load Capacitance, Fout < 133.33 MHz
15
pF
Load Capacitance,133.33 MHz < Fout < 166.67MHz
10
pF
C
IN
Input Capacitance
7
pF
t
PU
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
0.05
50
ms
Electrical Characteristics for CY2300SI Industrial Temperature Devices
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
IL
Input LOW Voltage
0.8
V
V
IH
Input HIGH Voltage
2.0
V
I
IL
Input LOW Current
V
IN
= 0V
100
A
I
IH
Input HIGH Current
V
IN
= V
DD
50
A
V
OL
Output LOW Voltage
[2]
I
OL
= 8 mA
0.4
V
V
OH
Output HIGH Voltage
[2]
I
OH
= 8 mA
2.4
V
I
DD
Supply Current
Unloaded outputs, REFIN = 66 MHz
48
mA
Unloaded outputs, REFIN = 33 MHz
35
mA
Unloaded outputs, REFIN = 20 MHz
20
mA
Note:
3.
All parameters are specified with equally loaded outputs.
CY2300
Document #: 38-07252 Rev. *B
Page 4 of 7
Switching Characteristics for CY2300SI Industrial Temperature Devices
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
1/t
1
Output Frequency
15-pF load
10
133.33
MHz
10-pF load
166.67
MHz
Duty Cycle
[3]
= t
2
t
1
Measured at V
DD
/2
40
50
60
%
t
3
Rise Time
[3]
Measured between 0.8V and 2.0V
1.20
ns
t
4
Fall Time
[3]
Measured between 0.8V and 2.0V
1.20
ns
t
5
Output to Output Skew on ris-
ing edges
[3]
All outputs equally loaded
Measured at V
DD
/2
200
ps
t
6
Delay, REFIN Rising Edge to
Output Rising Edge
[3]
Measured at V
DD
/2 from REFIN to any
output
200
ps
t
7
Device to Device Skew
[3]
Measured at V
DD
/2 on the 1/2xREF pin of
devices (pin 1)
400
ps
t
J
Period Jitter
[3]
Measured at Fout=133.33 MHz, loaded
outputs, 15-pF load
175
ps
t
LOCK
PLL Lock Time
[3]
Stable power supply, valid clocks present-
ed on REFIN
1.0
ms
Switching Waveforms
Duty Cycle Timing
t
1
t
2
V
DD
/2
All Outputs Rise/Fall Time
OUTPUT
t
3
3.3V
0V
0.8V
2.0V
2.0V
0.8V
t
4
Output-Output Skew
V
DD
/2
t
5
OUTPUT
OUTPUT
V
DD
/2
CY2300
Document #: 38-07252 Rev. *B
Page 5 of 7
Switching Waveforms
Input-Output Propagation Delay
V
DD
/2
t
6
REFIN
OUTPUT
V
DD
/2
V
DD
/2
t
7
1/2xREF, Device1
1/2xREF, Device2
Device-Device Skew
V
DD
/2
Test Circuits
0.1
F
V
DD
CLK
OUT
C
LOAD
OUTPUTS
GND
Test Circuit # 1
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