133-MHz Spread Spectrum Clock Generator For Use With
the AMD-K7
Processor and AMD-750 Chipset
CY22K7
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 9, 1999
Features
Benefits
Multiple output clocks running at different frequencies
-- Three open-drain differential CPU outputs running up
to 133 MHz
-- Eight 3.3V synchronous PCI clocks (one free running)
-- Two 3.3V AGP clocks at 2xPCI
-- One dedicated 3.3V USB clock at 48 MHz
-- One 3.3V USB/IO clock at 48 MHz or 24 MHz, selectable
via power-on latch input
-- One 3.3V SDRAM clock output running at the CPU fre-
quency
-- Two 3.3V Reference clocks at 14.318 MHz
Main clock generator for PC motherboard designs using the
AMD-K7 processor and AMD-750 Chipset
-- Supports up to two CPUs and chipset
-- Support for 4 PCI slots and chipset
-- Supports designs using AGP
-- Supports designs using USB
-- Allows for one additional USB output or support for I/O
chip from various vendors
-- Supports SDRAM memory architecture with external
PLL buffer
-- Supports ISA slots and I/O chip
Spread Spectrum clocking
-- 33 kHz modulation frequency
--
-
0.6% downspread margin
EMI reduction
Dedicated inputs for various functions
-- PCI_STOP
-- CPU_STOP
-- PWR_DWN
-- SPREAD
-- TEST
-- USB/IO
-- FS [0:1]
Provides system design flexibility and power management
-- Stops all PCI clocks (except PCICLK_F0) when LOW
-- Stops all CPU clocks when LOW
-- Power is removed from internal logic when LOW
-- Activates Spread Spectrum for lower EMI
-- Used to enter Test Mode
-- Selects USB or SuperIO Clock
-- Power-on latched inputs for frequency select options
I
2
C interface
Dynamic control of output clock signals via SMBus
48-Pin SSOP package
Industry-standard package provides cost and space savings
Logic Block Diagram
14.318 MHz
Xtal
Oscillator
CPU PLL
STOP
LOGIC
STOP
LOGIC
DIVIDER
2X
/2
LATCH
SYSTEM PLL
CONTROL
LOGIC
XTALIN
XTALOUT
CPU_STOP
SPREAD
FSO
FS1
TEST
SCLK
SDATA
PCI_STOP
REF [0:1]
SDRAM_OUT
CPUCLKT [0:2]
CPUCLKC [0:2]
AGPCLK [0:1]
PCICLK [0:6]
PCICLK_F
USB0
USB/IO
PWR_DWN
USB/IO
CY22K7
2
Pin Summary
[1]
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
34
AV
DD
PWR
Isolated power for core
33
AV
SS
PWR
Isolated ground for core
48
V
DDREF
PWR
Power for REF[0:1], XTALIN, XTALOUT
3
V
SSREF
PWR
Ground for REF[0:1] outputs
1, 2
FS[0:1]/REF[0:1]
IN/OUT
Frequency select input at power-on/14.318-MHz output
4
XTALIN
[2]
IN
14.318-MHz reference crystal input
5
XTALOUT
OUT
14.318-MHz reference crystal feedback
9, 15
V
DDPCI
PWR
Power for PCICLK outputs
6, 12
V
SSPCI
PWR
Ground for PCICLK outputs
7
PCICLK_F
OUT
Free running PCI output
8, 10, 11, 13, 14,
16, 17
PCICLK[0:6]
OUT
PCI clock outputs, TTL compatible 3.3V
18
V
DDAGP
PWR
Power for AGP outputs
21
V
SSAGP
PWR
Ground for AGP outputs
19, 20
AGP[0:1]
OUT
AGP clock outputs
22
V
DDUSB
PWR
Power for USB outputs
25
V
SSUSB
PWR
Ground for USB outputs
23
USB0
OUT
USB clock output
24
USB/IO (SELECT)
IN/OUT
USB or Super I/O output selected at power-on by latched input resistor:
LOW = 48 MHz, HIGH = 24 MHz
26
SCLK
IN/OUT
SMBus Clock
27
SDATA
IN/OUT
SMBus Data
28
TEST
IN
Three-state or Test Mode when LOW
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
FS0/REF0
34
Top View
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
C
Y
22K
7
FS1/REF1
V
SSREF
XTALIN
XTALOUT
PCICLK_F
V
SSPCI
PCICLK0
PCICLK1
V
DDPCI
PCICLK2
V
SSPCI
PCICLK3
V
DDPCI
PCICLK4
PCICLK6
V
DDAGP
AGP0
AGP1
V
SSAGP
V
DDUSB
USB0
USB/IO (SELECT)
V
DDREF
V
SSSDRAM
SDRAM_OUT
V
DDSDRAM
RESERVED
CPUCLKC2
CPUCLKT2
V
SSCPU
CPUCLKC1
CPUCLKT1
V
SSCPU
CPUCLKC0
CPUCLKT0
RESERVED
AV
DD
AV
SS
PCI_STOP
PWR_DWN
SPREAD
SDATA
SCLK
V
SSUSB
CPU_STOP
PCICLK5
48-pin SSOP
TEST
Pin Configuration
CY22K7
3
Notes:
1.
All control pins have internal pull-ups of 56K including: USB/IO, TEST, SPREAD, PWR_DWN, CPU_STOP, PCI_STOP.
2.
Part will go into test mode if three rising edges come on PCI_STOP while XTALIN is held low.
3.
Part will consume more shutdown current if external pull-ups are connected on latched input/outputs during power-down.
4.
TCLK/4 if Select = 0; TCLK/8 if Select = 1.
29
SPREAD
IN
Enables spread spectrum when LOW
30
PWR_DWN
[3]
IN
Power-down when LOW, removes power from internal logic
31
CPU_STOP
IN
Stops CPU clocks when LOW
32
PCI_STOP
[2]
IN
Stops PCI clocks when LOW
45
V
DDSDRAM
PWR
Power for SDRAM_OUT
47
V
SSSDRAM
PWR
Ground for SDRAM_OUT
46
SDRAM_OUT
OUT
CPU reference clock for SDRAM zero delay buffer
38, 41
V
SSCPU
PWR
Ground for CPU outputs shorted to SDRAM ground
36, 39, 42
CPUCLKT[0:2]
OUT
"True" clocks of differential pair for CPU and host clock outputs
37, 40, 43
CPUCLKC[0:2]
OUT
"Complementary" clocks of differential pair for CPU and host clock outputs
35, 44
RESERVED
-
Reserved for future CPU power rail
Function Table
TEST
FS1
FS0
CPUCLK
SDRAM_OUT
PCICLK
PCICLK_F
AGP
USB/IO
REF
0
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
1
50
25
50
48/24
14.318
0
1
0
66
33
66
48/24
14.318
0
1
1
TCLK/2
TCLK/6
TCLK/3
TCLK/4
[4]
TCLK
1
0
0
90
30
60
48/24
14.318
1
0
1
133
33.3
66.6
48/24
14.318
1
1
0
120
30
60
48/24
14.318
1
1
1
100
33.3
66.6
48/24
14.318
Pin Summary
[1]
(continued)
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Power Management Modes
PWR_DWN
CPU_STOP
PCI_
STOP
CPU+
CPU-
PCICLK
PCICLK_
F
Other
Clocks
Oscillator
PLLs
0
X
X
Low
High
Low
Low
Low
Off
Off
1
0
0
Low
High
Low
Running
Running
Running
Running
1
0
1
Low
High
Running
Running
Running
Running
Running
1
1
0
Running
Running
Low
Running
Running
Running
Running
1
1
1
Running
Running
Running
Running
Running
Running
Running
CY22K7
4
Frequency (MHz)
Am
p
lit
u
d
e
(
d
B)
Spread Spectrum Enabled
Spread Spectrum Disabled
SPREAD SPECTRUM CLOCKING
Description
Output
Min
Max
Unit
Modulation Frequency
CPUCLK, PCICLK, SDRAM_OUT, AGPCLK
30.0
33.0
kHz
Downspread margin at the fundamental frequency CPUCLK, PCICLK, SDRAM_OUT, AGPCLK
0.0
-
0.6
%
CY22K7
5
Serial Configuration Map
The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
I
2
C Address for the CY22K7 is:
Bytes 0 to 3 will be ignored.
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
-
Byte 4: Clock Control Register (1 = Active, 0 = Inactive)
Bit
Pin #
Default
Description
7
1
Active
REF0
6
24
Active
USB/IO
5
23
Active
USB0
4
20
Active
AGP1
3
19
Active
AGP0
2
42, 43
Active
CPUCLK2 (both of differential pair, "True" and "Complementary")
1
39, 40
Active
CPUCLK1 (both of differential pair, "True" and "Complementary")
0
36, 37
Active
CPUCLK0 (both of differential pair, "True" and "Complementary")
Byte 5: PCI/REF Clock Control Register (1 = Active, 0 = Inactive)
Bit
Pin #
Default
Description
7
2
Active
REF1
6
17
Active
PCICLK6
5
16
Active
PCICLK5
4
14
Active
PCICLK4
3
13
Active
PCICLK3
2
11
Active
PCICLK2
1
10
Active
PCICLK1
0
8
Active
PCICLK0
Byte 6: SDRAM Clock & Generator Mode Control Register (1 = Active, 0 = Inactive)
Bit
Pin #
Default
Description
7
-
Inactive
Spread Spectrum
6
-
Active
Bits[6:4] correspond to the Function Table on page 3
Bit 6 = TEST, Bit 5 = FS1, Bit 4 = FS0
example: Bits[6:4] = `111' -- 100-MHz CPUCLK and SDRAM_OUT clocks
5
-
Active
4
-
Active
3
-
Active
Reserved
2
-
Active
Reserved
1
-
Inactive
I
2
C (directs the generator to utilize either I
2
C feature selection if bit is enabled
or pin-based feature if bit is disabled)
0
46
Active
SDRAM_OUT
CY22K7
6
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ................................................. 0.5 to +4.0V
Input Voltage ............................................. 0.5V to V
DD
+0.5
Storage Temperature (Non-Condensing) .. 65
C to +150
C
Max. Soldering Temperature (10 sec) ...................... +260
C
Junction Temperature ............................................... +150
C
Package Power Dissipation ........................................... 0.7W
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
CY22K7 DC Operating Conditions
Over which the DC Characteristics are Guaranteed
Parameter
Description
Min.
Max.
Unit
V
DD
3.3V Power Supply Voltages
3.135
3.465
V
T
A
Operating Temperature, Ambient
0
70
C
C
L
Maximum Capacitive Load on
SDRAM_OUT
PCICLK
PCICLK_F
AGPCLK
USB, REF
30
30
30
30
20
pF
f
REF
Reference Frequency, Oscillator Nominal Value
14.318
14.318
MHz
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min. Max. Unit
V
IH
High-level Input Voltage
Except Crystal Pads. Threshold voltage for crystal pads = V
DD
/2
2.0
V
V
IL
Low-level Input Voltage
Except Crystal Pads
0.8
V
I
IH
Input High Current
0 < V
IN
< V
DD
10
A
I
IL
Input Low Current
0 < V
IN
< V
DD
50
A
I
OH
High-level Output Current
SDRAM_OUT
V
OUT
= 2.0V
-
19
mA
PCICLK
V
OUT
= 2.0V
-
26
PCICLK_F
V
OUT
= 2.0V
-
19
AGPCLK
V
OUT
= 2.0V
-
26
USB, USB/IO, REF
V
OUT
= 2.0V
-
22
I
OL
Low-level Output Current
CPUCLK
V
OUT
= 0.3V
16
mA
SDRAM_OUT
V
OUT
= 0.8V
12
PCICLK
V
OUT
= 0.8V
19
PCICLK_F
V
OUT
= 0.8V
12
AGPCLK
V
OUT
= 0.8V
19
USB, USB/IO, REF
V
OUT
= 0.8V
16
I
OZ
Output Leakage Current
Three-state
10
A
I
DD
3.3V Power Supply Current V
DD
= 3.465V, F
CPU
= 133 MHz
175
mA
I
DDPD
3.3V Shutdown Current
V
DD
= 3.465V
200
A
VIHS
SMBus Input High Level
0.7
V
VILS
SMBus Input Low Level
0.3
V
CY22K7
7
CY22K7 CPUCLK Driver Characteristics (Open Drain)
[7]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
DIF
Differential Voltage
See Note 5
0.4
V
pullup
(External) +
0.6
V
Vx
Differential Crossover Voltage
V
pullup
is to 1.5V
550
750
950
mV
V
X
Differential Crossover Voltage
V
pullup
(External) = 1.4 to 1.9V
Min = (V
pullup
(External)/2)
150mV
Max = (V
pullup
(External)/2) +
150mV
550
750
1100
mV
CY22K7 Switching Characteristics
[6, 7]
Over the Operating Range @ 100 MHz
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t
1
All
Output Duty Cycle
t
1A
/t
1B
[8]
45
55
%
t
2
CPU
Rising Edge Rate
At Output of CY22K7 CPU
1.0
V/ns
t
2
CPU
Rising Edge Rate
As measured at Observation Point in
Figure 1
0.4
V/ns
t
2
PCI
Rise Time
Between 0.4V and 2.4V
2.0
ns
t
2
SDRAM_OUT
Rise Time
Between 0.4V and 2.4V
2.0
ns
t
2
AGP
Rise Time
Between 0.4V and 2.4V
0.4
2.0
ns
t
2
USB, REF
Rise Time
Between 0.4V and 2.4V
4.0
ns
t
3
CPU
Falling Edge Rate
At Output of CY22K7 CPU
1.0
V/ns
t
3
CPU
Falling Edge Rate
As measured at Observation Point in
Figure 1
0.4
V/ns
t
3
PCI
Fall Time
Between 2.4V and 0.4V
2.0
ns
t
3
SDRAM_OUT
Fall Time
Between 2.4V and 0.4V
2.0
ns
t
3
AGP
Fall Time
Between 2.4V and 0.4V
0.4
2.0
ns
t
3
USB, REF
Fall Time
Between 2.4V and 0.4V
4.0
ns
t
4
CPU, PCI
CPU-PCI Offset
Load shown in Figure 1 & 2
500
700
ps
t
4
CPU, SDRAM
CPU-SDRAM Skew
Load shown in Figure 1 & 2
500
700
ps
t
4
CPU, AGP
CPU-AGP Skew
Load shown in Figure 1 & 2
1000
ps
t
4
CPU, CPU
CPU-CPU Skew
Load shown in Figure 1
250
ps
t
4
PCI, PCI
PCI-PCI Skew
Load shown in Figure 2
500
ps
t
5
CPU
Cycle-Cycle Clock Jitter
Measured at V
X
, t
5A
t
5B
250
ps
Notes:
5.
V
DIF
specifies the minimum input differential voltages (V
TR
V
CP
) required for switching, where V
TR
is the `true' input level and V
CP
is the `complement' input
level.
6.
All parameters specified with loaded outputs.
7.
All parameters for CPU are measured at observation point shown in figure1 on page 10 and parameters for PCI, SDRAM & AGP are measured at observation
point shown in Figure 2 on page 11 unless otherwise mentioned.
8.
For 133-MHz Output Duty Cycle will be guaranteed at 40% Min., 60% Max.
CY22K7
8
Switching Waveforms
Differential Clock Parameters
V
DDCPU
V
TR
V
CP
V
SS
V
X
V
DIF
Duty Cycle Timing
t
1A
t
1B
OUTPUT
All Outputs Rise/Fall Time
OUTPUT
t
2
V
DD
0V
t
3
Output_A-Output_B Clock Skew
t
4
OUTPUT_A
OUTPUT_B
Cycle-Cycle Clock Jitter
CLK
t
5A
t
5B
CLK
CY22K7
9
Notes:
9.
CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.
10. CPU_STOP may be applied asynchronously. It is synchronized internally.
11. USB, USB/IO, REF are not synchronized when entering/leaving power-down.
Switching Waveforms
(continued)
CPU_STOP Timing
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
CPU_STOP
CPU, CPU/2, AGP
(External)
[9,10]
PCI_STOP
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
PCI_STOP
PCICLK
(External)
(Free-Running)
PWR_DOWN
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN
PCICLK
CPUCLK
(External)
(External)
VCO
Crystal
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
[11]
CY22K7
10
Figure 1. AMD CPU Load Circuit
Component Values
Symbol
Value
V1
3.3V
V2
1.5V
R1,3
95
R2
360
R4,5,6,7
500
R8,9
50
R10,11
150
C1,2
680 pF
C3,4
20 pF
T1,4
Z
0
= 50
length = 5"
T2,5
Z
0
= 50
length = 3"
T3,6
Z
0
= 50
length = 1"
V
DD
V
DDCPU
V
DD
V
DD
V
DD
V
DD
V
DDCPU
V
DDCPU
CPUCLK_T
CPUCLK_C
R11
R10
R9
R8
R1
R3
R2
R4
R5
R6
R7
C2
C1
C4
C3
K7 CLOCK INPUT
CY22K7
T1
T2
T3
T6
T5
T4
V1
V2
Observation Point
CY22K7
PRELIMINARY
Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 3800745-B
Ordering Information
Ordering Code
Package
Name
Package Type
Operating
Range
CY22K7PVC1
O48
48-pin SSOP
Commercial
PCI,
SDRAM,
AGP
12 pF
Zo=50
, 5"
33
Observation Point
Figure 2. Test Circuit for PCI/SDRAM/AGP
Package Diagram
AMD-K7 is a registered trademark of Advanced Micro Devices.
48-Lead Shrunk Small Outline Package O48
51-85061-B
PDF 
ZIP