Features

·
·

Provides Analog Transmission Line
Interface for T1 and E1 Applications

·
·

Provides Line Driver, Jitter Attenuator
and Clock Recovery Functions

·
·

Fully Compliant with AT&T 62411
Stratum 4, Type II Jitter Requirements

·
·

Low Power Consumption

·
·

B8ZS/HDB3/AMI Encoder/Decoder

·
·

50 mA Transmitter Short-Circuit
Current Limiting

General Description

The CS61304A combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61304A is a pin-compatible replacement for the
LXT304A.

The receiver uses a digital Delay-Locked-Loop which is
continuously calibrated from a crystal reference to pro-
vide excellent stability and jitter tolerance. The
CS61304A has a receiver jitter attenuator optimized for
T1 CPE applications subject to AT&T 62411 and E1
ISDN PRI applications. The transmitter features inter-
nal pulse shaping and a low impedance output stage
allowing the use of external resistors for transmitter im-
pedance matching.

Applications

Primary Rate ISDN Network/Termination Equipment

Channel Service Units

ORDERING INFORMATION

See

page 31

MAY 96

DS156PP2

Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581

T1/E1 Line Interface

TTIP

TCLK

RRING

RTIP

TRING

TGND

CONTROL

LINE RECEIVER

LINE DRIVER

RCLK

LLOOP

(SCLK)

(INT)

LEN0

(SDI)

LEN1

(SDO)

LEN2

(CLKE)

TAOS

MODE

TPOS

[TDATA]

RPOS

[RDATA]

RNEG

[BPV]

TNEG

[TCODE]

MTIP
[RCODE]

DPM
[AIS]

LOS

RV+

RGND

MRING
[PCS]

XTALIN

XTALOUT

ACLKI

( ) = Pin Function in Host Mode
[ ] = Pin Function in Extended Hardware Mode

RLOOP

(CS)

R
E

M
O

T
E

O
O

P
B
A
C
K

AMI,

B8ZS,

HDB3,

CODER

JITTER

ATTENUATOR

O
C

O
O

P
B
A
C
K

CLOCK &

DATA

RECOVERY

SIGNAL

QUALITY

MONITOR

DRIVER

MONITOR

PULSE

SHAPER

TV+

Crystal Semiconductor Corporation 1996

CS61304A

This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.

Preliminary Product Information

Copyright

Cirrus Logic, Inc. 2005

http://www.cirrus.com

CS61304A

T1/E1 Line Interface

SEP `05

DS156F1

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Min

Max

Units

DC Supply

(referenced to RGND=TGND=0V)

RV+

TV+

-
-

6.0

(RV+) + 0.3

V
V

Input Voltage, Any Pin

(Note 1)

RGND-0.3

(RV+) + 0.3

Input Current, Any Pin

(Note 2)

-10

Ambient Operating Temperature

-40

Storage Temperature

stg

-65

150

WARNING: Operations at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Notes:

1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V.
2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND

can withstand a continuous current of 100 mA.

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

Typ

Max

Units

DC Supply

(Note 3) RV+, TV+

4.75

5.0

5.25

Ambient Operating Temperature

-40

Power Consumption

(Notes 4,5)

350

Notes:

3. TV+ must not exceed RV+ by more than 0.3V.
4. Power consumption while driving line load over operating temperature range. Includes IC and load.

Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF
capacitive load.

5. Assumes 100% ones density, 5.25 V, LEN2/1/0=1/1/1, a 100

load and a 1:1.15 transformer.

DIGITAL CHARACTERISTICS

(TA = -40

C to 85

C; TV+, RV+ = 5.0V

5%; GND = 0V)

Parameter

Symbol

Min

Typ

Max

Units

High-Level Input Voltage

(Notes 6, 7)

PINS 1-4, 17, 18, 23-28

2.0

Low-Level Input Voltage

(Notes 6, 7)

PINS 1-4, 17, 18, 23-28

0.8

High-Level Output Voltage

(Notes 6, 7, 8)

IOUT = -400

PINS 6-8, 11, 12, 25

2.4

Low-Level Output Voltage

(Notes 6, 7, 8)

IOUT = 1.6 mA

PINS 6-8, 11, 12, 23, 25

0.4

Input Leakage Current (Except Pin 5)

Low-Level Input Voltage, PIN 5

0.2

High-Level Input Voltage, PIN 5

(RV+) - 0.2

Mid-Level Input Voltage, PIN 5

(Note 9)

2.3

2.7

Notes:

6. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is

an open drain output and pin 25 is a tristate digital output.

7. This specification guarantees TTL compatibility (V

= 2.4V @ I

OUT

= -40

A).

8. Output drivers will drive CMOS logic levels into a CMOS load.
9. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating.

CS61304A

DS156PP2

CS61304A

DS156F1

ANALOG SPECIFICATIONS

(TA = -40

C to 85

C; TV+, RV+ = 5.0V

5%; GND = 0V)

Parameter

Min

Typ

Max

Units

Transmitter

AMI Output Pulse Amplitudes

(Note 10)

E1, 75

(Note 11)

E1, 120

(Note 12)

T1, FCC Part 68

(Note 13)

T1, DSX-1

(Note 14)

2.14

2.7
2.7
2.4

2.37

3.0
3.0
3.0

2.6
3.3
3.3
3.6

V
V
V
V

E1 Zero (space) level (LEN2/1/0 = 0/0/0)

1:1 transformer and 75

load

1:1.26 transformer and 120

load

-0.237

-0.3

-
-

0.237

0.3

V
V

Load Presented To Transmitter Output

(Note 10)

Jitter Added by the Transmitter

(Note 15)

10Hz - 8kHz
8kHz - 40kHz
10Hz - 40kHz
Broad Band

-
-
-
-

0.01

0.025
0.025

0.05

UI
UI
UI
UI

Power in 2kHz band about 772kHz

(Notes 10, 16)

12.6

17.9

dBm

Power in 2kHz band about 1.544MHz

(Notes 10, 16)

(referenced to power in 2kHz band at 772kHz)

-29

-38

Positive to Negative Pulse Imbalance

(Notes 10, 16)

T1, DSX-1
E1 amplitude at center of pulse
E1 pulse width at 50% of nominal amplitude

-5
-5

0.2

-
-

0.5

5
5

%
%

E1 Transmitter Return Loss

(Notes 10, 16, 17)

51 kHz to 102 kHz
102 kHz to 2.048 MHz
2.048 MHz to 3.072 MHz

20
20
20

28
28
24

-
-
-

dB
dB
dB

E1 Transmitter Short Circuit Current

(Notes 10, 18)

mA RMS

Notes: 10. Using a 0.47

F capacitor in series with the primary of a transformer recommended

in the Applications Section.

11. Pulse amplitude measured at the output of a 1:1 transformer across a 75

load for

line length setting LEN2/1/0 = 0/0/0.

12. Pulse amplitude measured at the output of a 1:1.26 transformer across a 120

load for line length

setting LEN2/1/0 = 0/0/0 or at the output of a 1:1 transformer across a 120

load for LEN2/1/0=0/0/1.

13. Pulse amplitude measured at the output of a 1:1.15 transformer across a 100

load for

line length setting LEN2/1/0 = 0/1/0.

14. Pulse amplitude measured at the DSX-1 Cross-Connect across a 100

load for all line length

settings from LEN2/1/0 = 0/1/1 to LEN2/1/0 = 1/1/1 using a 1:1.5 transformer.

15. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.
16. Not production tested. Parameters guaranteed by design and characterization.
17. Return loss = 20 log

ABS((z

)/(z

-z

)) where z

= impedance of the transmitter, and

= impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0

and a 1:2 transformer with two 9.4

series resistors terminated by a 75

load,

or for LEN2/1/0 = 0/0/1 with a 1:2 transformer and two 15

series resistors terminated by a

120

load.

18. Measured broadband through a 0.5

resistor across the secondary of the transmitter transformer

during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0 or 0/0/1with a 1:2 transformer
and the series resistors specified in Table A1.

CS61304A

DS156PP2

CS61304A

DS156F1

ANALOG SPECIFICATIONS

(TA = -40

C to 85

C; TV+, RV+ = 5.0V

5%; GND = 0V)

Parameter

Min

Typ

Max

Units

Receiver

RTIP/RRING Input Impedance

50k

Sensitivity Below DSX (0dB = 2.4V)

-13.6

500

-
-

Data Decision Threshold

T1, DSX-1

(Note 19)

T1, DSX-1

(Note 20)

T1, FCC Part 68 and E1

(Note 21)

60
53
45

65
65
50

70
77
55

% of peak
% of peak
% of peak

Allowable Consecutive Zeros before LOS

160

175

190

bits

Receiver Input Jitter Tolerance

(Note 22)

10kHz - 100kHz
2kHz
10Hz and below

0.4
6.0

300

-
-
-

UI
UI
UI

Loss of Signal Threshold

(Note 23)

0.25

0.30

0.50

Jitter Attenuator

Jitter Attenuation Curve Corner Frequency

(Notes 16, 24)

Attenuation at 10kHz Jitter Frequency

(Notes 16, 24)

Attenuator Input Jitter Tolerance

(Notes 16, 24)

(Before Onset of FIFO Overflow or Underflow Protection)

138

Notes: 19. For input amplitude of 1.2 V

to 4.14 V

20. For input amplitude of 0.5 V

to 1.2 V

and from 4.14 V

to RV+.

21. For input amplitude of 1.05 V

to 3.3 V

22. Jitter tolerance increases at lower frequencies. See Figure 11.
23. The analog input squelch circuit shall operate when the input signal amplitude above ground on the

RTIP and RRING pins falls within the range of 0.25V to 0.50V. Operation of the squelch results in
the recovery of zeros. During receive LOS, the RPOS, RNEG or RDATA outputs are forced low.

24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates

jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase
significantly when more than 138 UI's are input to the attenuator. See discussion in the text section.

CS61304A

DS156PP2

CS61304A

DS156F1

E1 SWITCHING CHARACTERISTICS

(TA = -40

C to 85

C; TV+, RV+ = 5.0V

5%;

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter

Symbol

Min

Typ

Max

Units

Crystal Frequency

(Note 25)

8.192000

MHz

TCLK Frequency

tclk

2.048

MHz

TCLK Pulse Width

(Note 26)

pwh2

150

340

ACLKI Duty Cycle

pwh3

pw3

ACLKI Frequency

(Note 27)

aclki

2.048

MHz

RCLK Duty Cycle

(Note 28)

pwh1

pw1

Rise Time, All Digital Outputs

(Note 29)

Fall Time, All Digital Outputs

(Note 29)

TPOS/TNEG (TDATA) to TCLK Falling Setup Time

su2

TCLK Falling to TPOS/TNEG (TDATA) Hold Time

RPOS/RNEG Valid Before RCLK Falling

(Note 30)

su1

100

194

RDATA Valid Before RCLK Falling

(Note 31)

su1

100

194

RPOS/RNEG Valid Before RCLK Rising

(Note 32)

su1

100

194

RPOS/RNEG Valid After RCLK Falling

(Note 30)

100

194

RDATA Valid After RCLK Falling

(Note 31)

100

194

RPOS/RNEG Valid After RCLK Rising

(Note 32)

100

194

T1 SWITCHING CHARACTERISTICS

(TA = -40

C to 85

C; TV+, RV+ = 5.0V

5%;

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter

Symbol

Min

Typ

Max

Units

Crystal Frequency

(Note 25)

6.176000

MHz

TCLK Frequency

tclk

1.544

MHz

TCLK Pulse Width

(Note 26)

pwh2

150

500

ACLKI Duty Cycle

pwh3

pw3

ACLKI Frequency

(Note 27)

aclki

1.544

MHz

RCLK Duty Cycle

(Note 28)

pwh1

pw1

Rise Time, All Digital Outputs

(Note 29)

Fall Time, All Digital Outputs

(Note 29)

TPOS/TNEG (TDATA) to TCLK Falling Setup Time

su2

TCLK Falling to TPOS/TNEG (TDATA) Hold Time

RPOS/RNEG Valid Before RCLK Falling

(Note 30)

su1

150

274

RDATA Valid Before RCLK Falling

(Note 31)

su1

150

274

RPOS/RNEG Valid Before RCLK Rising

(Note 32)

su1

150

274

RPOS/RNEG Valid After RCLK Falling

(Note 30)

150

274

RDATA Valid After RCLK Falling

(Note 31)

150

274

RPOS/RNEG Valid After RCLK Rising

(Note 32)

150

274

Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.

26. The transmitted pulse width does not depend on the TCLK duty cycle.
27. ACLKI provided by an external source or TCLK.
28. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached.
29. At max load of 1.6 mA and 50 pF.
30. Host Mode (CLKE = 1).
31. Extended Hardware Mode.
32. Hardware Mode, or Host Mode (CLKE = 0).

CS61304A

DS156PP2

CS61304A

DS156F1

Any Digital Output

t r

t f

10%

90%

Figure 1. Signal Rise and Fall Characteristics

RCLK

tpw1

tpwl1

tpwh1

HOST MODE
(CLKE = 1)

EXTENDED
HARDWARE
MODE OR

HARDWARE

HOST MODE
(CLKE = 0)

MODE OR

RCLK

RPOS
RNEG

su1

RDATA
BPV

Figure 2. Recovered Clock and Data Switching Characteristics

SWITCHING CHARACTERISTICS

(TA = -40

to 85

C; TV+, RV+ =

5%;

Inputs: Logic 0 = 0V, Logic 1 = RV+)

Parameter

Symbol

Min

Typ

Max

Units

SDI to SCLK Setup Time

SCLK to SDI Hold Time

cdh

SCLK Low Time

240

SCLK High Time

240

SCLK Rise and Fall Time

, t

CS to SCLK Setup Time

SCLK to CS Hold Time

cch

CS Inactive Time

cwh

250

SCLK to SDO Valid

(Note 33)

cdv

200

CS to SDO High Z

cdz

100

Input Valid To PCS Falling Setup Time

su4

PCS Rising to Input Invalid Hold Time

PCS Active Low Time

pcsl

250

Notes: 33. Output load capacitance = 50pF.

CS61304A

DS156PP2

CS61304A

DS156F1

THEORY OF OPERATION

Key Enhancements of the CS61304A Relative
to the LXT304A

12.5% Lower Power Consumption,

50 mA

RMS

transmitter short-circuit current

limiting for E1 (per OFTEL OTR-001),

Optional AMI, B8ZS, HDB3 encoder/de-
coder or external line coding support,

Receiver AIS (unframed all ones) detection,

Improved receiver Loss of Signal handling
(LOS set at power-up, reset upon receipt of
3 ones in 32 bit periods with no more than
15 consecutive zeros),

Transmitter TTIP and TRING outputs are
forced low when TCLK is static,

Introduction to Operating Modes

The CS61304A supports three operating modes
which are selected by the level of the MODE pin
as shown in Tables 1 and 2, Figure 7, and Figures
A1-A3 of the Applications section.

The modes are Hardware Mode, Extended Hard-
ware Mode, and Host Mode. In Hardware and
Extended Hardware Modes, discrete pins are used
to configure and monitor the device. The Ex-
tended Hardware Mode provides a parallel chip
select input which latches the control inputs al-
lowing individual ICs to be configured using a
common set of control lines. In the Host Mode,
an external processor monitors and configures the
device through a serial interface. There are thir-
teen multi-function pins whose functionality is
determined by the operating mode. (see Table 2).

Hardware

Mode

Extended

Hardware

Mode

Host

Mode

Control

Method

Control

Pins

Control Pins

with Parallel

Chip Select

Serial

Interface

MODE

Pin

Level

<0.2 V

Floating or

2.5 V

>(RV+)-0.2

Line

Coding

External

Internal-

AMI, B8ZS,

or HDB3

External

AIS

Detection

Yes

Driver

Performance

Monitor

Yes

Table 1. Differences Between Operating Modes

MODE

FUNCTION

PIN HARDWARE

EXTENDED

HARDWARE

HOST

TRANSMITTER

TPOS

TDATA

TPOS

TNEG

TCODE

TNEG

RECEIVER/DPM

RNEG

BPV

RNEG

RPOS

RDATA

RPOS

DPM

AIS

DPM

MTIP

RCODE

MTIP

MRING

CONTROL

PCS

LEN0

INT

LEN1

SDI

LEN2

SDO

RLOOP

LLOOP

SCLK

TAOS

CLKE

Table 2. Pin Definitions

CS61304A

DS156PP2

CS61304A

DS156F1

TPOS

TNEG

RNEG

RPOS

TRANSMIT

TRANSFORMER

RRING

RECEIVE

TRANSFORMER

CONTROL

CS62180B

FRAMER

CIRCUIT

TTIP

TDATA

RDATA

TRING

LINE DRIVER

AMI

B8ZS,

HDB3,

CODER

TRANSMIT

TRANSFORMER

RLOOP

PCS

LEN0/1/2

LLOOP

TAOS

CONTROL

HARDWARE MODE

EXTENDED HARDWARE MODE

HOST MODE

CONTROL

P SERIAL PORT

RCODE

TCODE

CLKE

BPV

AIS

JITTER

ATTENUATOR

DRIVER MONITOR

LINE DRIVER

LINE RECEIVER

MTIP

MRING

DPM
RTIP

TTIP

TRING

T1 or E1

REPEATER

MUX

CS61304A

TTIP

TPOS

TNEG

RNEG

TRING

RPOS

RRING

RTIP

RLOOP

LEN0/1/2

LLOOP

TAOS

CONTROL

DPM

DRIVER MONITOR

LINE DRIVER

LINE RECEIVER

MTIP

MRING

CS61304A

CS62180B
FRAMER
CIRCUIT

JITTER

ATTENUATOR

TRANSMIT

TRANSFORMER

RECEIVE

TRANSFORMER

RECEIVE

TRANSFORMER

RRING

RTIP

AIS

DETECT

JITTER

ATTENUATOR

LINE

RECEIVER

Figure 7. Overview of Operating Modes

CS61304A

DS156PP2

CS61304A

DS156F1

Transmitter

The transmitter takes digital T1 or E1 input data
and drives appropriately shaped bipolar pulses
onto a transmission line. The transmit data (TPOS
& TNEG or TDATA) is supplied synchronously
and sampled on the falling edge of the input
clock, TCLK.

Either T1 (DSX-1 or Network Interface) or E1
CCITT G.703 pulse shapes may be selected.
Pulse shaping and signal level are controlled by
"line length select" inputs as shown in Table 3.
The output options in Table 3 are specified with a
1:1.15 transmitter transformer turns ratio for T1
and a 1:1 turns ratio for E1 without external series
resistors. Other turns ratios may be used if ap-
proriate resistors are placed in series with the
TTIP and TRING pins. Table A1 in the applica-
tions section lists other combinations which can
be used to provide transmitter impedance match-
ing.

For T1 DSX-1 applications, line lengths from 0 to
655 feet (as measured from the transmitter to the
DSX-1 cross connect) may be selected. The five
partition arrangement in Table 3 meets ANSI
T1.102 and AT&T CB-119 requirements when
using #22 ABAM cable. A typical output pulse is
shown in Figure 8. These pulse settings can also
be used to meet CCITT pulse shape requirements
for 1.544 MHz operation.

For T1 Network Interface applications, two addi-
tional options are provided. Note that the optimal
pulse width for Part 68 (324 ns) is narrower than
the optimal pulse width for DSX-1 (350 ns). The
CS61304A automatically adjusts the pulse width
based upon the "line length" selection made.

The E1 G.703 pulse shape is supported with line
length selections LEN2/1/0 = 0/0/0 and 0/0/1.
The pulse width will meet the G.703 pulse shape
template shown in Figure 9, and specified in Ta-
ble 4.

The CS61304A transmitter provides short-circuit
current limiting protection and meets OFTEL
OTR-001 short-circuit current limiting require-
ments for E1 applications.

The CS61304A will detect a static TCLK, and
will force TTIP and TRING low to prevent trans-
mission when data is not present. When any
transmit control pin (TAOS, LEN0-2 or LLOOP)
is toggled, the transmitter outputs will require ap-
proximately 22 bit periods to stabilize. The
transmitter will take longer to stabilize when
RLOOP is selected because the timing circuitry
must adjust to the new frequency.

500

1.0

0.5

-0.5

250

750

1000

NORMALIZED
AMPLITUDE

AT&T CB 119
SPECIFICATIONS

PULSE SHAPE

OUTPUT

TIME (nanoseconds)

ANSI T1.102,

Figure 8. Typical Pulse Shape at DSX-1 Cross Connect

LEN2 LEN1 LEN0

Option Selected

Application

0-133 ft

DSX-1

ABAM

(AT&T 600B

or 600C)

133-266 ft

266-399 ft

399-533 ft

533-655 ft

coax

CCITT G.703

120

twisted-pair

FCC PART 68, OPT. A

Network

Interface

ANSI T1.403

Table 3. Line Length Selection

CS61304A

DS156PP2

CS61304A

DS156F1

Transmit All Ones Select

The transmitter provides for all ones insertion at
the frequency of TCLK. Transmit all ones is se-
lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. If Remote
Loopback is in effect, any TAOS request will be
ignored.

Receiver

The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and out-
puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of
ABAM cable lengths and requires no equalization
or ALBO (Automatic Line Build Out) circuits.
The signal is received on both ends of a center-
tapped, center-grounded transformer. The
transformer is center tapped on the IC side. The
clock and data recovery circuit exceeds the jitter
tolerance specifications of Publications 43802,
43801, AT&T 62411, TR-TSY-000170, and
CCITT REC. G.823.

A block diagram of the receiver is shown in Fig-
ure 10. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar sig-
nals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0 in-
puts).

The leading edge of an incoming data pulse trig-
gers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-

269 ns

244 ns

194 ns

219 ns

488 ns

Nominal Pulse

100

110

120

-10

-20

Percent of
nominal
peak
voltage

Figure 9. Mask of the Pulse at the 2048 kbps Interface

Fo r c o a x i a l c a bl e,
75

l o a d a n d

transformer specified
in Application Section.

For shielded twisted
pair, 120

load and

transformer specified
in Application Section.

Nominal peak voltage of a mark (pulse)

2.37 V

3 V

Peak voltage of a space (no pulse)

0.237 V

0.30 V

Nominal pulse width

244 ns

Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval

0.95 to 1.05*

Ratio of the widths of positive and negative
pulses at the nominal half amplitude

0.95 to 1.05*

* When configured with a 0.47

F nonpolarized capacitor in series with the TX transformer

primary as shown in Figures A1, A2 and A3.

Table 4. CCITT G.703 Specifications

CS61304A

DS156PP2

CS61304A

DS156F1

put from the phase selector feeds the clock and
data recovery circuits which generate the recov-
ered clock and sample the incoming signal at
appropriate intervals to recover the data.

Data sampling will continue at the periods se-
lected by the phase selector until an incoming
pulse deviates enough to cause a new phase to be
selected for data sampling. The phases of the de-
lay line are selected and updated to allow as much
as 0.4 UI of jitter from 10 kHz to 100 kHz, with-
out error. The jitter tolerance of the receiver
exceeds that shown in Figure 11. Additionally,
this method of clock and data recovery is tolerant
of long strings of consecutive zeros. The data
sampler will continuously sample data based on
its last input until a new pulse arrives to update
the clock phase selector.

The delay line is continuously calibrated using
the crystal oscillator reference clock. The delay
line produces 13 phases for each cycle of the ref-
erence clock. In effect, the 13 phases are
analogous to a 20 MHz clock when the reference
clock is 1.544 MHz. This implementation utilizes
the benefits of a 20 MHz clock for clock recovery
without actually having the clock present to im-
pede analog circuit performance.

In the Hardware Mode, data at RPOS and RNEG
should be sampled on the rising edge of RCLK,
the recovered clock. In the Extended Hardware
Mode, data at RDATA should be sampled on the
falling edge of RCLK. In the Host Mode, CLKE
determines the clock polarity for which output
data should be sampled as shown in Table 5.

10k

100

100k

700

100

300

PEAK-TO-PEAK

JITTER

(unit intervals)

JITTER FREQUENCY (Hz)

AT&T 62411

138

Minimum
Performance

Figure 11. Minimum Input Jitter Tolerance of Receiver

(Clock Recovery Circuit and Jitter Attenuator)

1 : 2

RTIP

RRING

Data

Level

Slicer

Edge

Detector

Clock

Phase

Selector

Continuously

Calibrated

Delay Line

Jitter

Attenuator

RPOS

RNEG

RCLK

Data

Clock

Sampling

Extraction

Figure 10. Receiver Block Diagram

CS61304A

DS156PP2

CS61304A

DS156F1

Loss of Signal

The receiver will indicate loss of signal after
power-up, reset or upon receiving 175 consecu-
tive zeros. A digital counter counts received
zeros, based on RCLK cycles. A zero is received
when the RTIP and RRING inputs are below the
input comparator slicing threshold level estab-
lished by the peak detector. After the signal is
removed for a period of time the data slicing
th r e s h o l d level d e c a y s t o ap p ro x imate ly
300 mV

peak

The receiver reports loss of signal by setting the
Loss of Signal pin, LOS, high. If the serial inter-
face is used, the LOS bit will be set and an
interrupt will be issued on INT (unless disabled).
LOS will return low (asserting the INT pin again
in Host Mode) upon receipt of 3 ones in 32 bit
periods with no more than 15 consecutive zeros.
Note that in the Host Mode, LOS is simultane-
ously available from both the register and pin 12.
RPOS/RNEG or RDATA are forced low during
LOS unless the jitter attenuator is disabled. (See
"Jitter Attenuator")

If ACLKI is present during the LOS state, ACLKI
is switched into the input of the jitter attenuator,
resulting in RCLK matching the frequency of
ACLKI. The jitter attenuator buffers any instanta-
neous changes in phase between the last

recovered clock and the ACLKI reference clock.
This means that RCLK will smoothly transition
to the new frequency. If ACLKI is not present,
then the crystal oscillator of the jitter attenuator is
forced to its center frequency. Table 6 shows the
status of RCLK upon LOS.

Jitter Attenuator

The jitter attenuator reduces wander and jitter in
the recovered clock signal. It consists of a FIFO,
a crystal oscillator, a set of load capacitors for the
crystal, and control logic. The jitter attenuator ex-
ceeds the jitter attenuation requirements of
Publications 43802 and REC. G.742. A typical
jitter attenuation curve is shown in Figure 12. The
CS61304A fully meets AT&T 62411 jitter attenu-
ation requirements.

Crystal

present?

ACLKI

present?

Source of RCLK

Yes

ACLKI

Yes

Centered Crystal

Yes

ACLKI via the Jitter Attenuator

Table 6. RCLK Status at LOS

MODE

(pin 5)

CLKE

(pin 28)

DATA

CLOCK

Clock Edge

for Valid Data

LOW

(<0.2V)

RPOS
RNEG

RCLK
RCLK

Rising
Rising

HIGH

(>(V+) - 0.2V)

LOW

RPOS
RNEG

SDO

RCLK
RCLK
SCLK

Rising
Rising

Falling

HIGH

(>(V+) - 0.2V)

HIGH

RPOS
RNEG

SDO

RCLK
RCLK
SCLK

Falling
Falling

Rising

MIDDLE

(2.5V)

RDATA

RCLK

Falling

X = Don't care

Table 5. Data Output/Clock Relationship

t
t
e

ati

n i

Frequency in Hz

100

1 k

10 k

b) Maximum
Attunuation
Limit

62411 Requirements

a) Minimum Attenuation Limit

Measured Performance

Figure 12. Typical Jitter Transfer Function

CS61304A

DS156PP2

CS61304A

DS156F1

The jitter attenuator works in the following man-
ner. The recovered clock and data are input to the
FIFO with the recovered clock controlling the
FIFO's write pointer. The crystal oscillator con-
trols the FIFO's read pointer which reads data out
of the FIFO and presents it at RPOS and RNEG
(or RDATA). The update rate of the read pointer
is analogous to RCLK. By changing the load ca-
pacitance that the IC presents to the crystal, the
oscillation frequency is adjusted to the average
frequency of the recovered signal. Logic deter-
mines the phase relationship between the read and
write pointers and decides how to adjust the load
capacitance of the crystal. Jitter is absorbed in the
FIFO.

The FIFO in the jitter attenuator is designed to
prevent overflow and underflow. If the jitter am-
plitude becomes very large, the read and write
pointers may get very close together. Should they
attempt to cross, the oscillator's divide by four
circuit adjusts by performing a divide by 3 1/2 or
divide by 4 1/2 to prevent data loss from overflow
or underflow.

The jitter attenuator may be bypassed by pulling
XTALIN to RV+ through a 1 k

resistor and pro-

viding a 1.544 MHz (or 2.048 MHz) clock on
ACLKI. RCLK may exhibit quantization jitter of
approximately 1/13 UIpp and a duty cycle of ap-
proximately 30% (70%) when the attenuator is
disabled.

Local Loopback

Local loopback is selected by taking LLOOP, pin
27, high or by setting the LLOOP register bit via
the serial interface.

The local loopback mode takes clock and data
presented on TCLK, TPOS, and TNEG (or
TDATA), sends it through the jitter attenuator and
outputs it at RCLK, RPOS and RNEG (or
RDATA). If the jitter attenuator is disabled, it is
bypassed. Inputs to the transmitter are still trans-

mitted on TTIP and TRING, unless TAOS has
been selected in which case, AMI-coded continu-
ous ones are transmitted at the TCLK frequency.
The receiver RTIP and RRING inputs are ignored
when local loopback is in effect.

Remote Loopback

Remote loopback is selected by taking RLOOP,
pin 26, high or by setting the RLOOP register bit
via the serial interface.

In remote loopback, the recovered clock and data
input on RTIP and RRING are sent through the
jitter attenuator and back out on the line via TTIP
and TRING. Selecting remote loopback overrides
any TAOS request (see Table 7). The recovered
incoming signals are also sent to RCLK, RPOS
and RNEG (or RDATA). A remote loopback oc-
c u r s in response to RLOOP going high.
Simultaneous selection of local and remote loop-
back modes is not valid (see Reset).

In the Extended Hardware Mode the transmitted
data is looped before the AMI/B8ZS/HDB3 en-
coder/decoder during remote loopback so that the
transmitted signal matches the received signal,
even in the presence of received bipolar viola-
tions. Data output on RDATA is decoded,
however, if RCODE is low.

RLOOP

Input

Signal

TAOS

Input

Signal

Source of

Data for

TTIP & TRING

Source of

Clock for

TTIP & TRING

TDATA

TCLK

all 1s

TCLK

RTIP & RRING

RTIP & RRING (RCLK)

Notes: 1. X = Don't Care. The identified All Ones Select

input is ignored when the indicated loopback is
in effect.

2. Logic 1 indicates that Loopback or All Ones

option is selected.

Table 7. Interaction of RLOOP with TAOS

CS61304A

DS156PP2

CS61304A

DS156F1

Driver Performance Monitor

To aid in early detection and easy isolation of
non-functioning links, the IC is able to monitor
transmit drive performance and report when the
driver is no longer operational. This feature can
be used to monitor either the device's perform-
ance or the performance of a neighboring driver.
The driver performance monitor indicator is nor-
mally low, and goes high upon detecting a driver
failure.

The driver performance monitor consists of an ac-
tivity detector that monitors the transmitted signal
when MTIP is connected to TTIP and MRING is
connected to TRING. DPM will go high if the
absolute difference between MTIP and MRING
does not transition above or below a threshold
level within a time-out period. In the Host Mode,
DPM is available from both the register and pin
11.

Whenever more than one line interface IC resides
on the same circuit board, the effectiveness of the
driver performance monitor can be maximized by
having each IC monitor performance of a neigh-
boring IC, rather than having it monitor its own
performance.

Alarm Indication Signal

In the Extended Hardware Mode, the receiver sets
the output pin AIS high when less than 3 zeros
are detected out of 2048 bit periods. AIS returns
low when 4 or more zeros, out of 2048 bits, are
detected.

Line Code Encoder/Decoder

In the Extended Hardware Mode, three line codes
are available: AMI, B8ZS and HDB3. The input
to the encoder is TDATA. The outputs from the
decoder are RDATA and BPV (Bipolar Violation
Strobe). The encoder and decoder are selected
using the LEN2, LEN1, LEN0, TCODE and
RCODE pins as shown in Table 8.

Parallel Chip Select

In the Extended Hardware Mode, PCS can be
used to gate the digital control inputs: TCODE,
RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP
and TAOS. Inputs are accepted on these pins only
when PCS is low and will immediately change
the operating state of the device. Therefore, when
cycling PCS to update the operating state, the
digital control inputs should be stable for the en-
tire PCS low period. The digital control inputs are
ignored when PCS is high.

Power On Reset / Reset

Upon power-up, the IC is held in a static state
until the supply crosses a threshold of approxi-
mately 3 Volts. When this threshold is crossed,
the device will delay for about 10 ms to allow the
power supply to reach operating voltage. After
this delay, calibration of the delay lines used in
the transmit and receive sections commences. The
delay lines can be calibrated only if a reference
clock is present. The reference clock for the re-
ceiver is provided by the crystal oscillator, or
ACLKI if the oscillator is disabled. The reference
clock for the transmitter is provided by TCLK.
The initial calibration should take less than
20 ms.

LEN 2/1/0

000

010-111

TCODE

(Transmit

Encoder

Selection)

LOW

HDB3

Encoder

B8ZS

Encoder

HIGH

AMI Encoder

RCODE

(Receiver

Decoder

Selection)

LOW

HDB3

Decoder

B8ZS

Decoder

HIGH

AMI Decoder

Table 8. Encoder/Decoder Selection

CS61304A

DS156PP2

CS61304A

DS156F1

In operation, the delay lines are continuously cali-
brated, making the performance of the device
independent of power supply or temperature vari-
ations. The continuous calibration function
forgoes any requirement to reset the line interface
when in operation. However, a reset function is
available which will clear all registers.

In the Hardware and Extended Hardware Modes,
a reset request is made by simultaneously setting
both the RLOOP and LLOOP pins high for at
least 200 ns. Reset will initiate on the falling edge
of the reset request (falling edge of RLOOP and
LLOOP). In the Host Mode, a reset is initiated by
simultaneously writing RLOOP and LLOOP to
the register. In either mode, a reset will set all reg-
isters to 0 and force the oscillator to its center
frequency before initiating calibration. A reset
will also set LOS high.

Serial Interface

In the Host Mode, pins 23 through 28 serve as a
microprocessor/microcontroller interface. One
on-board register can be written to via the SDI
pin or read from via the SDO pin at the clock rate
determined by SCLK. Through this register, a
host controller can be used to control operational
characteristics and monitor device status. The se-
rial port read/write timing is independent of the
system transmit and receive timing.

Data transfers are initiated by taking the chip se-
lect input, CS, low (CS must initially be high).
Address and input data bits are clocked in on the
rising edge of SCLK. The clock edge on which

output data is stable and valid is determined by
CLKE as shown in Table 5. Data transfers are ter-
minated by setting CS high. CS may go high no
sooner than 50 ns after the rising edge of the
SCLK cycle corresponding to the last write bit.
For a serial data read, CS may go high any time
to terminate the output.

Figure 13 shows the timing relationships for data
transfers when CLKE = 1. When CLKE = 1, data
bit D7 is held until the falling edge of the 16th
clock cycle. When CLKE = 0, data bit D7 is held
until the rising edge of the 17th clock cycle. SDO
goes High-Z after CS goes high or at the end of
the hold period of data bit D7.

An address/command byte, shown in Table 9, pre-
cedes a data register. The first bit of the
address/command byte determines whether a read
or a write is requested. The next six bits contain
the address. The line interface responds to address
16 (0010000). The last bit is ignored.

SCLK

SDO

SDI

Address/Command Byte

Data Input/Output

R/W

Figure 13. Input/Output Timing

LSB, first bit

R/W

Read/Write Select; 0 = write, 1 = read

ADD0

LSB of address, Must be 0

ADD1

Must be 0

ADD2

Must be 0

ADD3

Must be 0

ADD4

Must be 1

Reserved - Must be 0

MSB, last bit

Don't Care

Table 9. Address/Command Byte

CS61304A

DS156PP2

CS61304A

DS156F1

The data register, shown in Table 10, can be writ-
ten to the serial port. Data is input on the eight
clock cycles immediately following the ad-
dress/command byte. Bits 0 and 1 are used to
clear an interrupt issued from the INT pin, which
occurs in response to a loss of signal or a problem
with the output driver.

Writing a "1" to either "Clear LOS" or "Clear
DPM" over the serial interface has three effects:

1) The current interrupt on the serial interface

will be cleared. (Note that simply reading
the register bits will not clear the inter-
rupt).

2) Output data bits 5, 6 and 7 will be reset as

appropriate.

3) Future interrupts for the corresponding LOS

or DPM will be prevented from occurring.

Writing a "0" to either "Clear LOS" or "Clear
DPM" enables the corresponding interrupt for
LOS or DPM.

Output data from the serial interface is presented
as shown in Tables 11 and 12. Bits 2, 3 and 4 can
be read to verify line length selection. Bits 5, 6
and 7 must be decoded. Codes 101, 110 and 111
(Bits 5, 6 and 7) indicate intermittent loss of sig-
nal and/or driver problems.

SDO goes to a high impedance state when not in
use. SDO and SDI may be tied together in appli-
c ations where th e host processo r has a
bi-directional I/O port.

LSB: first bit in

clr LOS Clear Loss of Signal

1 clr DPM Clear Driver Performance Monitor

LEN0

Bit 0 - Line Length Select

LEN1

Bit 1 - Line Length Select

LEN2

Bit 2 - Line Lenght Select

5 RLOOP Remote Loopback

LLOOP Local Loopback

MSB: last bit in 7

TAOS

Transmit All Ones Select

Table 10. Input Data Register

LSB: first bit in

LOS

Loss of Signal

DPM

Driver Performance Monitor

LEN0

Bit 0 - Line Length Select

LEN1

Bit 1 - Line Length Select

LEN2

Bit 2 - Line Lenght Select

Table 11. Output Data Bits 0 - 4

Bits

Status

5 6 7
0 0 0 Reset has occurred or no program input.
0 0 1 TAOS in effect.
0 1 0 LLOOP in effect.
0 1 1 TAOS/LLOOP in effect.
1 0 0 RLOOP in effect
1 0 1 DPM changed state since last "clear DPM"

occured.

1 1 0 LOS changed state since last "clear LOS"

occured.

1 1 1 LOS and DPM have changed state since

last "clear LOS" and "clear DPM".

Table 12. Coding for Serial Output bits 5,6,7

CS61304A

DS156PP2

CS61304A

DS156F1

Power Supply

The device operates from a single +5 Volt supply.
Separate pins for transmit and receive supplies
provide internal isolation. These pins should be
connected externally near the device and decou-
pled to their respective grounds. TV+ must not
exceed RV+ by more than 0.3V.

Decoupling and filtering of the power supplies is
crucial for the proper operation of the analog cir-
cuits in both the transmit and receive paths. A 1.0

F capacitor should be connected between TV+

and TGND, and a 0.1

F capacitor should be con-

nected between RV+ and RGND. Use mylar or
ceramic capacitors and place them as closely as
possible to their respective power supply pins. A
68

F tantalum capacitor should be added close

to the RV+/RGND supply. Wire-wrap bread-
boarding of the line interface is not recommended
because lead resistance and inductance serve to
defeat the function of the decoupling capacitors.

Schematic & Layout Review Service

Confirm Optimum

Schematic & Layout

Before Building Your Board.

For Our Free Review Service

Call Applications Engineering.

C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2

CS61304A

DS156PP2

CS61304A

DS156F1

PIN DESCRIPTIONS

Hardware Mode

top

view

ACLKI

TCLK

TAOS

TPOS

LLOOP

TNEG

RLOOP

MODE

LEN2

RNEG

LEN1

RPOS

LEN0

RCLK

RGND

XTALIN

RV+

XTALOUT

RRING

DPM

RTIP

LOS

MRING

TTIP

MTIP

TGND

TRING

TV+

ACLKI

TAOS

TCLK

LLOOP

TPOS

RLOOP

TNEG

LEN2

MODE

LEN1

RNEG

LEN0

RPOS

RGND

RCLK

RV+

XTALIN

RRING

XTALOUT

RTIP

DPM

MRING

LOS

MTIP

TTIP

TRING

TGND

TV+

CS61304A

DS156PP2

CS61304A

DS156F1

Extended Hardware Mode

ACLKI

TAOS

TCLK

LLOOP

TDATA

RLOOP

TCODE

LEN2

MODE

LEN1

BPV

LEN0

RDATA

RGND

RCLK

RV+

XTALIN

RRING

XTALOUT

RTIP

AIS

PCS

LOS

RCODE

TTIP

TRING

TGND

TV+

top

view

ACLKI

TCLK

TAOS

TDATA

LLOOP

TCODE

RLOOP

MODE

LEN2

BPV

LEN1

RDATA

LEN0

RCLK

RGND

XTALIN

RV+

XTALOUT

RRING

AIS

RTIP

LOS

PCS

TTIP

RCODE

TGND

TRING

TV+

CS61304A

DS156PP2

CS61304A

DS156F1

Host Mode

ACLKI

CLKE

TCLK

SCLK

TPOS

TNEG

SDO

MODE

SDI

RNEG

INT

RPOS

RGND

RCLK

RV+

XTALIN

RRING

XTALOUT

RTIP

DPM

MRING

LOS

MTIP

TTIP

TRING

TGND

TV+

top

view

ACLKI

TCLK

CLKE

TPOS

SCLK

TNEG

MODE

SDO

RNEG

SDI

RPOS

INT

RCLK

RGND

XTALIN

RV+

XTALOUT

RRING

DPM

RTIP

LOS

MRING

TTIP

MTIP

TGND

TRING

TV+

CS61304A

DS156PP2

CS61304A

DS156F1

Power Supplies

RGND - Ground, Pin 22.

Power supply ground for all subcircuits except the transmit driver; typically 0 Volts.

RV+ - Power Supply, Pin 21.

Power supply for all subcircuits except the transmit driver; typically +5 Volts.

TGND - Ground, Transmit Driver, Pin 14.

Power supply ground for the transmit driver; typically 0 Volts.

TV+ - Power Supply, Transmit Driver, Pin 15.

Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than
0.3 V.

Oscillator

XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.

A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or
2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying
XTALIN, Pin 9 to RV+ through a 1 k

resistor, and floating XTALOUT, Pin 10.

Overdriving the oscillator with an external clock is not supported.

Control

ACLKI - Alternate External Clock Input, Pin 1.

A 1.544 MHz (or 2.048 MHz) clock may be input to ACLKI, or this pin must be tied to ground.
During LOS, the ACLKI input signal, if present, is output on RCLK through the jitter attenuator.

CLKE - Clock Edge, Pin 28. (Host Mode)

Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and
SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS
and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of
SCLK.

CS - Chip Select, Pin 26. (Host Mode)

This pin must transition from high to low to read or write the serial port.

INT - Receive Alarm Interrupt, Pin 23. (Host Mode)

Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing
"clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the
power supply through a resistor.

CS61304A

DS156PP2

CS61304A

DS156F1

LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended
Hardware Modes)

Determines the shape and amplitude of the transmitted pulse to accommodate several cable types
and lengths. See Table 3 for information on line length selection. Also controls the receiver
slicing level and the line code in Extended Hardware Mode.

LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes)

Setting LLOOP to a logic 1 routes the transmit clock and data through the jitter attenuator to the
receive clock and data pins. TCLK and TPOS/TNEG (or TDATA) are still transmitted unless
overridden by a TAOS request. Inputs on RTIP and RRING are ignored.

MODE - Mode Select, Pin 5.

Driving the MODE pin high puts the line interface in the Host Mode. In the host mode, a serial
control port is used to control the line interface and determine its status. Grounding the MODE
pin puts the line interface in the Hardware Mode, where configuration and status are controlled
by discrete pins. Floating the MODE pin or driving it to +2.5 V selects the Extended Hardware
Mode, where configuration and status are controlled by discrete pins. When floating MODE,
there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2).

PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode)

Setting PCS high causes the line interface to ignore the TCODE, RCODE, LEN0, LEN1, LEN2,
RLOOP, LLOOP and TAOS inputs.

RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode)

Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting
RCODE high enables the AMI receiver decoder (see Table 8).

RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes)

Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter
attenuator (if active) and through the driver back to the line. The recovered signal is also sent to
RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored.

Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset.

SCLK - Serial Clock, Pin 27. (Host Mode)

Clock used to read or write the serial port registers. SCLK can be either high or low when the line
interface is selected using the CS pin.

SDI - Serial Data Input, Pin 24. (Host Mode)

Data for the on-chip register. Sampled on the rising edge of SCLK.

SDO - Serial Data Output, Pin 25. (Host Mode)

Status and control information from the on-chip register. If CLKE is high SDO is valid on the
rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to
a high-impedance state when the serial port is being written to or after bit D7 is output.

CS61304A

DS156PP2

CS61304A

DS156F1

TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes)

Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined
by TCLK.

TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode)

Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting
TCODE high enables the AMI transmitter encoder .

Data

RCLK - Recovered Clock, Pin 8.

The receiver recovered clock generated by the jitter attenuator is output on this pin.When in the
loss of signal state ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is
not present during LOS, RCLK is forced to the center frequency of the crystal oscillator.

RDATA - Receive Data - Pin 7. (Extended Hardware Mode)

Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the
line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK.

RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host
Modes)

The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS
and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines
the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse
(with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive
pulse received on the RRING pin generates a logic 1 on RNEG.

RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20.

The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up
transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data
and clock are recovered and output on RCLK and RPOS/RNEG or RDATA.

TCLK - Transmit Clock, Pin 2.

The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are
sampled on the falling edge of TCLK.

TDATA - Transmit Data, Pin 3. (Extended Hardware Mode)

Transmitter NRZ input data which passes through the line code encoder, and is then driven on to
the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK.

TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and
Host Modes)

Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and
TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a
positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted.

CS61304A

DS156PP2

CS61304A

DS156F1

TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16.

The AMI signal is driven to the line through these pins. The transmitter output is designed to
drive a 75

load between TTIP and TRING. A transformer is required as shown in Table A1.

Status

AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode)

AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection
criteria of less than three zeros out of 2048 bit periods.

BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode)

BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3)
zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been
enabled.

DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes)

DPM goes high if no activity is detected on MTIP and MRING.

LOS - Loss of Signal, Pin 12.

LOS goes high when 175 consecutive zeros have been received. LOS returns low when 3 ones
are received within 32 bit periods with no more than 15 consecutive zeros. When in the loss of
signal state RPOS/RNEG or RDATA are forced low, and ACLKI (if present) is output on RCLK
via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center
frequency of the crystal oscillator.

MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes)

These pins are normally connected to TTIP and TRING and monitor the output of a line interface
IC. If the INT pin in the Host mode is used, and the monitor is not used, writing a 1 to the "clear
DPM" bit will prevent an interrupt from the driver performance monitor.

CS61304A

DS156PP2

CS61304A

DS156F1

28 pin
Plastic DIP

MILLIMETERS

INCHES

DIM

MIN

MAX

MIN

MAX

13.72

14.22

0.540

0.560

36.45

1.02

0.36

0.51

3.94

3.18

0.20

0°

15.24

37.21

1.65

0.56

1.02

5.08

3.81

0.38

15°

1.435

0.040

0.014

0.020

0.155

0.125

0.600

0.008

0°

1.465

0.065

0.022

0.040

0.200

0.150

0.015

15°

15.87

0.625

2.41

2.67

0.095

0.105

SEATING
PLANE

NOTES:

1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.

NOM

13.97

36.83

1.27

0.46

0.76

4.32

0.25

2.54

NOM

0.550

1.450

0.050

0.018

0.030

0.170

0.010

0.100

E1
e1
eA

D2/E2

28-pin PLCC

D2/E2

MAX

MIN

MAX

MIN

MILLIMETERS

INCHES

DIM

4.57

4.20

0.180

0.165

D/E

12.32

12.57

0.485

0.495

0.53

0.33

0.021

0.013

2.29

0.090

11.43

11.58

0.450

0.456

9.91

10.92

0.390

0.430

1.19

1.35

0.047

0.053

NOM

4.45

12.45

0.41

2.79

11.51

10.41

1.27

NOM

0.175

0.490

0.016

0.110

0.453

0.410

0.050

3.04

0.120

D1/E1

CS61304A

DS156PP2

CS61304A

DS156F1

APPLICATIONS

Line Interface

Figures A1-A3 show typical T1 and E1 line inter-
face application circuits. Table A1 shows the
external components which are specific to each
application. Figure A1 illustrates a T1 interface in

the Host Mode. Figure A2 illustrates a 120

interface in the Hardware Mode. Figure A3 illus-
trates a 75

E1 interface in the Extended

Hardware Mode.

Control

Monitor

Frame

Format

Encoder/

Decoder

CS61304A

HOST

MODE

Serial

Port

RECEIVE
LINE

TRANSMIT
LINE

XTL

RV+

RGND

0.1

+5V

1.0

TGND

RV+

TV+

CLKE

ACLKI

LOS

DPM

MODE

RPOS

RNEG

RCLK

TPOS

TNEG

TCLK

XTALIN

XTALOUT

RGND

TGND

SCLK

INT

SDI

SDO

RTIP

RRING

MTIP

MRING

TRING

TTIP

0.47

1:1.15

PE-65388

2CT:1

PE-65351

+5V

100 k

Figure A1. T1 Host Mode Configuration

Frequency

MHz

Crystal

XTL

Cable

R1 and R2

LEN2/1/0

Transmit

Transformer

R3 and R4

Typical TX

Return Loss dB

1.544 (T1)

CXT6176

100

200

0/1/1 - 1/1/1

1:1.15

1:2

1:2.3

9.4
9.4

0.5

20
28

2.048 (E1)

CXT8192

120

240

0/0/0
0/0/0
0/0/1
0/0/1

1:1.26

1:2
1:1
1:2

8.7

0.5

150

0/0/0
0/0/0
0/0/1
0/0/1

1:1
1:2
1:1
1:2

9.4

14.3

0.5

Table A1. External Component Values

CS61304A

DS156PP2

Control

Monitor

Frame

Format

Encoder/

Decoder

CS61304A

HARDWARE

MODE

Line

Length
Setting

RECEIVE
LINE

TRANSMIT
LINE

XTL

RGND

0.1

+5V

1.0

TGND

RV+

TV+

TAOS

ACLKI

RLOOP

LLOOP

MODE

RPOS

RNEG

RCLK

TPOS

TNEG

TCLK

XTALIN

XTALOUT

RGND

TGND

LEN0

LEN1

LEN2

RTIP

RRING

MTIP

MRING

TRING

TTIP

0.47

1:1.26

PE-65389

2CT:1

PE-65351

LOS

DPM

Figure A2. 120

E1 Hardware Mode Configuration

Control

Monitor

Frame

Format

Encoder/

Decoder

CS61304A

EXTENDED

HARDWARE

MODE

Line

Length
Setting

RECEIVE
LINE

TRANSMIT
LINE

XTL

RGND

0.1

+5V

1.0

TGND

RV+

TV+

RCODE

PCS

BPV

TAOS

MODE

RDATA

RCLK

TDATA

TCLK

XTALIN

XTALOUT

RGND

TGND

LEN0

LEN1

LEN2

RTIP

RRING

TRING

TTIP

0.47

1:1

PE-65389

2CT:1

PE-65351

ACLKI

RLOOP

LLOOP

LOS

AIS

TCODE

Figure A3. 75

E1 Extended Hardware Mode Configuration

CS61304A

DS156PP2

The receiver transformer has a grounded center
tap on the IC side. Resistors between the RTIP
and RRING pins to ground provide the termina-
tion for the receive line.

The transmitter transformer matches the 75

transmitter output impedance to the line imped-
ance. Figures A1-A3 show a 0.47

F capacitor in

series with the transmit transformer primary. This
capacitor is needed to prevent any output stage
imbalance from resulting in a DC current through
the transformer primary. This current might satu-
rate the transformer producing an output offset
level shift.

Transformers

Recommended transmitter and receiver trans-
former specifications are shown in Table A2. The
transformers in Table A3 are recommended for
use with the CS61304A. Refer to the "Telecom
Transformer Selection Guide" for detailed sche-
matics which show how to connect the line
interface IC with a particular transformer.

Selecting an Oscillator Crystal

Specific crystal parameters are required for
proper operation of the jitter attenuator. It is rec-
ommended that the Crystal Semiconductor

CXT6176 crystal be used for T1 applications and
the CXT8192 crystal be used for E1 applications.

Designing for AT&T 62411

For additional information on the requirements of
AT&T 62411 and the design of an appropriate
system synchronizer, please refer to the Crystal
Semiconductor Application Notes: "AT&T 62411
Design Considerations Jitter and Synchroniza-
ti o n " a nd "J i t te r Test in g Pro c e d u r e s f o r
Compliance with AT&T 62411".

Transmit Side Jitter Attenuation

In some applications it is desirable to attenuate
jitter from the signal to be transmitted. A
CS61304A in local loopback mode can be used
as a jitter attenuator. The inputs to the jitter at-
tenuator are TPOS, TNEG, TCLK. The outputs
from the jitter attenuator are RPOS, RNEG and
RCLK.

Line Protection

Secondary protection components can be added
to provide lightning surge and AC power-cross
immunity. Refer to the "Telecom Line Protection
Application Note" for detailed information on the
different electrical safety standards and specific
application circuit recommendations.

Parameter

Receiver

Transmitter

Turns Ratio

1:2 CT

1:1

1.5 % for 75

1:1.15

5 % for 100

1:1.26

1.5 % for 120

Primary Inductance

600

H min. @ 772 kHz

1.5 mH min. @ 772 kHz

Primary Leakage Inductance

1.3

H max. @ 772 kHz

0.3

H max. @ 772 kHz

Secondary Leakage Inductance

0.4

H max. @ 772 kHz

0.4

H max. @ 772 kHz

Interwinding Capacitance

23 pF max.

18 pF max.

ET-constant

16 V-

s min. for T1

12 V-

s min. for E1

16 V-

s min. for T1

12 V-

s min. for E1

Table A2. Transformer Specifications

CS61304A

DS156PP2

Interfacing The CS61304A With the
CS62180B T1 Transceiver

To interface with the CS62180B, connect the de-
vices as shown in Figure A4. In this case, the line
interface and CS62180B are in Host Mode con-
trolled by a microprocessor serial interface. If the
line interface is used in Hardware Mode, then the
line interface RCLK output must be inverted be-
fore being input to the CS62180B. If the
CS61304A is used in Extended Hardware Mode,
the RCLK output does not have to be inverted be-
fore being input to the CS62180B.

Application

Turns

Ratio(s)

Manufacturer

Part Number

Package Type

RX:

T1 & E1

1:2CT

Pulse Engineering

PE-65351

1.5 kV through-hole, single

Schott

67129300

Bel Fuse

0553-0013-HC

TX:

1:1.15

Pulse Engineering

PE-65388

1.5 kV through-hole, single

Schott

67129310

Bel Fuse

0553-0013-RC

TX:

E1 (75 & 120

)

1:1.26

1:1

Pulse Engineering

PE-65389

1.5 kV through-hole, single

Schott

67129320

Bel Fuse

0553-0013-SC

RX &TX:

1:2CT
1:1.15

Pulse Engineering

PE-65565

1.5 kV through-hole, dual

Bel Fuse

0553-0013-7J

RX &TX:

E1 (75 & 120

)

1:2CT
1:1.26

1:1

Pulse Engineering

PE-65566

1.5 kV through-hole, dual

Bel Fuse

0553-0013-8J

RX &TX:

1:2CT
1:1.15

Pulse Engineering

PE-65765

1.5 kVsurface-mount, dual

Bel Fuse

S553-0013-06

RX &TX:

E1 (75 & 120

)

1:2CT
1:1.26

1:1

Pulse Engineering

PE-65766

1.5 kV surface-mount, dual

Bel Fuse

S553-0013-07

RX :

T1 & E1

1:2CT

Pulse Engineering

PE-65835

3 kV through-hole, single

EN60950, EN41003 approved

TX:

E1 (75 & 120

)

1:1.26

1:1

Pulse Engineering

PE-65839

3 kV through-hole, single

EN60950, EN41003 approved

Table A3. Recommended Transformers

ACLK

TCLK

RCLK

RPOS

RNEG

TPOS

TNEG

CS62180B

CLKE

SCLK

INT

SDO

SDI

TCLK

TPOS

TNEG

RNEG

RPOS

RCLK

SCLK

SDO

SDI

TO HOST CONTROLLER

V+

100k

1.544 MHz

CLOCK

SIGNAL

V+

22k

MODE

CS61304A

Figure A4. Interfacing the CS61304A with a

CS62180B (Host Mode)

CS61304A

DS156PP2

· Notes ·

CS61304A

DS156F1

ORDERING INFORMATION

ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

REVISION HISTORY

Model

Package

Temperature

CS61304A-IL

28-pin PLCC

-40 to +85 °C

Model Number

Peak Reflow Temp

MSL Rating*

Max Floor Life

CS61304A-IL

225 °C

365 Days

Revision

Date

Changes

PP2

MAY 1996

Initial Release

SEP 2005

Updated device ordering info. Updated legal notice. Added MSL data..

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to

www.cirrus.com

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