Advance Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 2001
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS4812
Fixed Function Multi-Effects Audio Processor
Features
l
DSP for embedded reverb/effects
applications
24-bit Audio Processing Engine
No External RAM required
Two 24-bit
ADCs with 100 dB Dyn. Range
Two 24-bit
DACs with 100 dB Dyn. Range
l
Mono Guitar or Mixer Effects firmware
included
l
Real time parameter control via messaging
protocol
l
Serial Control Port for microcontroller
interface
l
Single +5V supply operation
l
100-pin Metric Quad Flat Package (MQFP)
ORDERING INFO
CS4812-KM
-10 to +70C 100-pin
MQFP
CDB4812
Electric Guitar Effects w/
Parameter Controls.
Description
The CS4812 is a complete audio effects processing
system on a chip. This device includes a proprietary 24-
bit audio processing engine with considerable on-chip
RAM, two ADCs and two DACs. A full-featured serial
control port allows interfacing to an external host
microcontroller. Other features such as single +5V
operation simplify system design.
The CS4812, combined with Crystal effects firmware, is
the ideal solution for a variety of effects processing
applications where user parameter control is desired.
The Crystal effects firmware provides a messaging
protocol for the serial control port that allows an external
microcontroller to have real-time parameter control over
the audio effects. The complete processor and effects
solution may be evaluated with the CDB4812
demonstration board. The CDB4812 demonstrates a
host of mono electric guitar effects including a digital
spring reverb, delay, chorus, flange and tremolo with
parameter adjustment capability. Please refer to AN195
for more information on application firmware for the
CS4812.
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DS291PP3
CS4812
2
DS291PP3
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 14
3. FUNCTIONAL DESCRIPTION ............................................................................................... 17
3.1 Overview .......................................................................................................................... 17
3.2 Analog Inputs ................................................................................................................... 17
3.2.1 Line Level Inputs ................................................................................................. 17
3.2.2 Digital High Pass Filter ........................................................................................ 18
3.3 Analog Outputs ................................................................................................................ 18
3.3.1 Line Level Outputs .............................................................................................. 18
3.4 Clock Generation ............................................................................................................. 19
3.4.1 Clock Source ....................................................................................................... 19
3.5 Serial Control Port ............................................................................................................ 19
3.5.1 SPI Bus ............................................................................................................... 19
3.5.1.1 SPI Master Mode ................................................................................ 20
3.5.1.2 SPI Slave Mode .................................................................................. 20
3.5.2 I
2
C Bus ................................................................................................................ 23
3.5.2.1 I
2
C Master Mode ................................................................................. 23
3.5.2.2 I
2
C Slave Mode ................................................................................... 24
3.6 Boot Modes ...................................................................................................................... 26
3.6.1 AutoBoot ............................................................................................................. 26
3.6.2 HostBoot ............................................................................................................. 26
3.7 Resets ............................................................................................................................. 27
4. POWER SUPPLY AND GROUNDING ................................................................................... 28
5. PIN DESCRIPTIONS .............................................................................................................. 29
6. PARAMETER DEFINITIONS .................................................................................................. 33
7. PACKAGE DIMENSIONS ...................................................................................................... 34
LIST OF FIGURES
Figure 1. SPI Control Port Slave Mode Timing .......................................................... 8
Figure 2. SPI Control Port Master Mode (AutoBoot) Timing ..................................... 9
Figure 3. I
2
C
Control Port Slave Mode Timing ...................................................... 11
Figure 4. I
2
C
Control Port Master Mode (AutoBoot) Timing .................................. 12
Figure 5. Typical Connection Diagram, Control Port Slave Mode ........................... 14
Figure 6. Typical Connection Diagram, Control Port I
2
C Master Mode ................... 15
Figure 7. Typical Connection Diagram, Control Port SPI Master Mode .................. 15
Figure 8. Typical Connection Diagram, Control Port I
2
C Slave Mode ..................... 16
Figure 9. Typical Connection Diagram, Control Port SPI Slave Mode .................... 16
Figure 10.Recommended Line Input Buffer .............................................................. 17
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any
kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third
parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publi-
cation may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise)
without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the
printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photo-
graphic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or
sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in
this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
CS4812
DS291PP3
3
Figure 11.Single Ended Input ................................................................................... 18
Figure 12.Butterworth Output Filters ........................................................................ 18
Figure 13.Output Mute Circuit .................................................................................. 19
Figure 14.Control Port Timing, SPI Master Mode AutoBoot ..................................... 20
Figure 15.Control Port Timing, SPI Slave Mode Write ............................................. 20
Figure 16.SPI Slave Write Flow Diagram ................................................................. 21
Figure 17.Control Port Timing, SPI Slave Mode Read ............................................. 21
Figure 18.SPI Slave Mode Read Flow Diagram........................................................ 22
Figure 19.SPI Slave Mode Read Flow Diagram with DSP REQ .............................. 22
Figure 20.Control Port Timing, I
2
C Master Mode AutoBoot ..................................... 23
Figure 21.I
2
C Slave Mode Write Flow Diagram ........................................................ 24
Figure 22.Control Port Timing, I
2
C Slave Mode Write .............................................. 24
Figure 23.Control Port Timing, I
2
C Slave Mode Write .............................................. 24
Figure 24.I
2
C Slave Mode Read Flow Diagram ....................................................... 25
Figure 25.I
2
C Slave Mode Read Flow Diagram with DSP REQ ............................... 26
Figure 26.HostBoot Flow Diagram ........................................................................... 27
Figure 27.CS4812 Suggested Layout ...................................................................... 28
Figure 28.Pin Assignments ...................................................................................... 29
CS4812
4
DS291PP3
1. CHARACTERISTICS AND SPECIFICATIONS
ADC CHARACTERISTICS
(T
A
= 25C; VA, VD = + 5V; -1 dB Full Scale Input Sine wave,
997 Hz; Fs = 48 kHz; XTI = 12.288 MHz (PLL disabled). Measurement Bandwidth is 20 Hz to 20 kHz.)
Notes: 1. Referenced to typical full-scale differential input voltage (2 V
rms
).
2. Bench tested only.
3. Filter characteristics scale with output sample rate.
4. Group delay for Fs = 48 kHz, t
gd
= 15/48 kHz = 313 s.
5. Measured using differential analog input circuit, see Figure 10.
6. Filter Response is not tested but guaranteed by design.
Parameters
Symbol Min Typ
Max
Units
Analog Input Characteristics
ADC Conversion
Stereo Audio channels
16
-
24
Bits
Dynamic Range
(A weighted, Note 5)
(unweighted, Note 5)
93
90
100
97
-
-
dB
dB
Total Harmonic Distortion + Noise
(Note 1,5)
(PLL enabled)
(Note 1,2,5)
THD+N
-
-
-92
-92
-87
-
dB
Interchannel Isolation
-
90
-
dB
Interchannel Gain Mismatch
-
0.1
-
dB
Offset Error (with high pass filter enabled)
(Note 6)
-
-
0
LSB
Full Scale Input Voltage (Differential)
1.9
2.0
2.1
V
rms
Gain Drift
(Note 2)
-
100
-
ppm/C
Input Resistance
10
-
-
k
Input Capacitance
-
-
15
pF
CMOUT Output Voltage
-
2.3
-
V
Common Mode Rejection Ratio
(Note 2)
CMRR
60
dB
Group Delay (Fs = Output Sample Rate)
(Note 4)
t
gd
-
15/Fs
-
s
Group Delay Variation vs. Frequency
t
gd
-
-
0
s
High Pass Filter Characteristics
Frequency Response
-3dB (Note 3)
-0.14dB (Note 3)
-
-
3.7
20
-
-
Hz
Hz
Phase Deviation
@ 20 Hz (Note 3)
-
10
-
Degree
Passband Ripple
-
-
0
dB
CS4812
DS291PP3
5
DAC CHARACTERISTICS
(T
A
= 25C; VA, VD = + 5V; -1 dB Full Scale Output Sine wave,
997 Hz; Fs = 48 kHz; XTI = 12.288 MHz (PLL disabled). Measurement Bandwidth is 20 Hz to 20 kHz.)
Notes: 7. Measured with DAC calibration disabled.
8. Measured with XTI clock disabled.
Parameters
Symbol Min Typ
Max
Units
Analog Output Characteristics - Minimum Attenuation, 10 k
, 100 pF load; unless otherwise specified.
DAC Resolution
16
-
24
Bits
Dynamic Range
(DAC not muted, A weighted)
95
100
-
dB
Total Harmonic Distortion + Noise
THD+N
-
-90
-85
dB
Interchannel Isolation
-
90
-
dB
Interchannel Gain Mismatch
-
0.1
-
dB
Offset Voltage (differential)
(Note 7)
-
-20 5
-
mV
Offset Voltage (V+/V- relative to CMOUT)
(Note 7)
-
-45/-25
-
mV
Full Scale Output Voltage
(Differential)
1.9
2.0
2.1
V
rms
Gain Drift
(Note 2)
-
100
-
ppm/C
Out of Band Energy
(Fs/2 to 2Fs, Note 2)
-
-60
-
dBFS
Analog Output Load
Resistance
Capacitance
10
-
-
-
-
100
k
pF
Group Delay (Fs = Input Sample Rate)
t
gd
-
16/Fs
-
s
Analog Loopback Performance
Signal-to-Noise Ratio (CCIR-2K weighted, -20 dB input)
CCIR-2K
-
74
-
dB
Power Supply
Power Supply Current
Operating
Power Down
(Note 8)
-
-
200
1
-
-
mA
mA
Power Supply Rejection
(1 kHz, 10 mV
rms
, Note 2)
-
50
-
dB
CS4812
6
DS291PP3
SWITCHING CHARACTERISTICS
(T
A
= 25 C; VA, VD = +5V, C
L
= 30 pF)
Notes: 9. Guaranteed by characterization but not tested.
10. On power-up, the CS4812 RST pin should be asserted until the power supplies have reached steady
state.
Parameters
Symbol
Min
Typ
Max
Units
Audio ADC's & DAC's Sample Rate
Fs
30
-
50
kHz
XTI Frequency XTI = 128Fs, 256Fs, 512Fs
3.84
-
25.6
MHz
XTI Duty Cycle XTI = 128Fs, 256Fs, 512Fs
(Note 9)
40
-
60
%
XTI Jitter Tolerance
-
500
-
ps
RST Low Time
(Note 10)
500
-
-
ns
CS4812
DS291PP3
7
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI SLAVE
(T
A
= 25 C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 30 pF)
Notes: 11. Data must be held for sufficient time to bridge 100 ns transition time of CCLK.
12. CDOUT should NOT be sampled during this time period.
13. DSPCLK frequency is twice the DSP instruction rate.
14. Timing is guaranteed by characterization. Production test guarantees functionality.
Parameter
Symbol
Min
Max
Unit
SPI Slave Mode (SPI/I2C = 0, SCPM/S = 0, Note 14)
CCLK Clock Frequency
f
sck
-
6
MHz
CCLK Low Time
t
scl
66
-
ns
CCLK High Time
t
sch
66
-
ns
Rise Time of Both CDIN and CCLK Lines
t
r
-
100
ns
Fall Time of Both CDIN and CCLK Lines
t
f
-
100
ns
Setup Time CDIN to CCLK Rising
t
cdisu
40
-
ns
Hold Time CCLK Rising to CDIN
(Note 11)
t
cdih
15
-
ns
Time from CCLK edge to CDOUT Valid
(Note 12)
t
scdov
-
45
ns
Rise Time for CDOUT
t
cdor
-
25
ns
Fall Time for CDOUT
t
cdof
-
25
ns
CS Falling to CCLK Rising
t
css
20
-
ns
Time from CCLK Falling to CS Rising
t
sccsh
0
-
ns
High Time Between Active CS
t
csht
1
-
s
Time from CCLK Rising to REQ Rising
(Note 13)
t
scrh
-
2*DSPCLK+10
ns
Rise Time for REQ
t
rr
-
100
ns
Fall Time for REQ
t
rf
-
100
ns
CS4812
8
DS291PP3
t cs
s
t sc
l
t r
t sch
t cdi
s
u
t sc
d
o
v
t cd
ih
t s
c
dov
t rf
t f
MSB
MSB
A0
A6
A
5
CS
SC
L
/
C
C
L
K
CD
I
N
CD
O
U
T
RE
Q
(i
n
p
ut
)
(inpu
t
)
(outp
u
t)
t sc
cs
h
t rh
t scr
h
t cs
ht
LS
B
LS
B
6
7
5
A6
t cs
cdo
tri
-
stat
e
R/W
*
Figure 1.
S
P
I
Co
n
t
rol Port
Sl
a
v
e M
o
de T
i
min
g
* S
ee s
e
ct
i
o
n
3.
5.
1.
2 f
o
r
a det
ail
e
d
explanat
ion of
R
E
Q
beha
vior
CS4812
DS291PP3
9
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MASTER
(TA = 25C, VA, VD = 5V; Inputs: logic 0 = DGND, logic 1 = VD, C
L
= 30 pF)
Notes: 15. Depending on the input clock configuration, CCLK may be up to 2*Fs temporarily during AutoBoot after
RST is de-asserted and before the control port registers have been initialized.
16. Measured with a 2.2 k
pull-up resistor to VD.
Parameter
Symbol
Min
Typ
Max
Units
SPI Master (AutoBoot) Mode (SPI/I2C = 0, SCPM/S = 1, Note 14)
CCLK Clock Frequency
(Note 15)
f
sck
-
Fs
-
kHz
CCLK Low Time
t
scl
-
1/(2*Fs)
-
ns
CCLK High Time
t
sch
-
1/(2*Fs)
-
ns
CCLK Rise Time
(Note 16)
t
r2
-
12
-
ns
CCLK Fall Time
(Note 16)
t
f2
-
12
-
ns
RST rising to CS falling
t
srs
-
42
-
s
CS High Time Between Transmissions
t
csh
37
-
-
s
CS Falling to CCLK Edge
t
css
5
-
-
s
CS Falling to CDOUT valid
t
dv
-
-
50
ns
CCLK Falling to CDOUT valid
t
pd
-
-
100
ns
CDIN to CCLK Rising Setup Time
t
dsu
80
-
-
ns
CCLK Rising to DATA Hold Time
t
dh
80
-
-
ns
CCLK Falling to CS rising
t
clcs
40
-
-
ns
t r2
t f2
t dsu t dh
t sch
t scl
CS
CCLK
CDIN
t css
t csh
t clcs
t srs
RST
t pd
CDOUT
t dv
Figure 2. SPI Control Port Master Mode (AutoBoot) Timing
CS4812
10
DS291PP3
SWITCHING CHARACTERISTICS - CONTROL PORT - I
2
C
SLAVE
(T
A
= 25 C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 30 pF)
Notes: 17. Use of the I
2
C bus interface requires a license from Philips. I
2
C is a registered trademark of Philips
Semiconductors.
18. Not tested.
19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
20. DSPCLK frequency is twice the DSP instruction rate.
Parameter
Symbol
Min
Max
Units
I
2
C
Slave Mode (SPI/I2C = 1, SCPM/S = 0) (Note 17)
SCL Clock Frequency
f
scl
-
100
kHz
Bus Free Time Between Transmissions
t
buf
4.7
-
s
Start Condition Hold Time (prior to first clock pulse)
t
hdst
4.0
-
s
SCL Low Time
t
low
4.7
-
s
SCL High Time
t
high
4.0
-
s
RST rising to start condition
(Note18)
t
srs
1
-
ms
SDA Hold Time from SCL Falling
(Note 19)
t
hdd
0
-
s
Rise Time of Both SDA and SCL
t
r
-
1
s
Fall Time of Both SDA and SCL
t
f
-
300
ns
SCL Falling to CS4812 ACK
t
sca
-
1.3
s
SCL Falling to SDA Valid During READ
t
scsdv
-
1.5
s
Time from SCL Rising to REQ Rising
(Note 20)
t
scrh
-
2*DSPCLK+10
ns
Rise Time for REQ
t
rr
-
100
ns
Fall Time for REQ
t
rf
-
100
ns
Setup Time for Stop Condition
t
susp
4.7
-
s
Setup Time for Repeated Start
t
sust
4.7
s
CS4812
DS291PP3
11
MS
B
A0
A6
A5
SCL
/
CCLK
SD
A
RE
Q
AC
K
st
o
p
st
a
r
t
01
6
7
80
t rf
(in
p
ut)
t su
s
p
t rr
AC
K
7
8
LS
B
stop
t scr
h
t bu
f
t hd
s
t
t lo
w
t hd
d
t hi
g
h
t sc
a
t r
t f
t sud
R/
W
t scs
d
v
6
*
F
i
g
u
re 3.
I
2
C
Contro
l Port
S
l
a
v
e M
o
de T
i
min
g
*
Se
e
sec
t
ion 3.
5.
2.
2 f
o
r
a det
a
i
led explanat
i
on of
RE
Q
behav
i
o
r
CS4812
12
DS291PP3
SWITCHING CHARACTERISTICS - CONTROL PORT - I
2
C
MASTER
(T
A
= 25C;
VA, VD = 5V; Inputs: logic 0 = DGND, logic 1 = VD, C
L
= 30 pF)
Notes: 21. Use of the I
2
C bus interface requires a license from Philips. I
2
C is a registered trademark of Philips
Semiconductors.
22. Depending on the input clock configuration, CCLK may be up to 2*Fs temporarily during AutoBoot after
RST has been de-asserted and before the control port registers have been initialized.
23. Data must be held for sufficient time to bridge the worst case fall time of 300 ns for CCLK/SCL.
24. For both SDA transmitting and receiving.
Parameter
Symbol
Min
Typ
Max
Units
I
2
C
Master (AutoBoot) Mode (SPI/I2C = 1, SCPM/S = 1) (Note 21)
SCL Clock Frequency
(Note 22)
f
scl
-
Fs
-
kHz
Clock Low Time
t
low
-
1/(2*Fs)
-
s
Clock High Time
t
high
-
1/(2*Fs)
-
s
Bus Free Time Between Transmissions
t
buf
4.7
-
-
s
RST rising to start condition
t
irs
-
22
-
s
Start Condition Hold Time
t
hdst
4.0
-
-
s
Setup Time for Repeated Start Condition
t
sust
13.5
-
-
s
SDA Setup Time to SCL Rising
t
sud
250
-
-
ns
SDA Hold Time from SCL Falling
(Note 23)
t
hdd
0
-
-
s
SCL falling to SDA Output Valid
t
cldv
-
-
1.5
s
SCL and SDA Rise Time
(Note 24)
t
r
-
-
1
s
SCL and SDA Fall Time
(Note 24)
t
f
-
-
300
ns
Setup Time for Stop Condition
t
susp
4.7
-
-
s
t
buf
t
hdst
t
hdst
t
low
t r
t f
t
hdd
t
high
t sud
tsust
t susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
t
irs
RST
t
cldv
(output)
Figure 4. I
2
C
Control Port Master Mode (AutoBoot) Timing
CS4812
DS291PP3
13
ABSOLUTE MAXIMUM RATINGS
(All voltages with respect to AGND = DGND = 0V.)
Notes: 25. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause
SCR latch-up.
26. The maximum over or under voltage is limited by the input current.
Warning:
Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(All voltages with respect to AGND = DGND = 0V.)
DIGITAL CHARACTERISTICS
(T
A
= 25 C; VA, VD = 5V)
SWITCHING CHARACTERISTICS - PROGRAMMABLE I/O
(T
A
= 25 C; VA, VD = 5V 5%; Inputs: logic 0 = DGND, logic 1 = VD, C
L
= 30 pF)
Parameters
Symbol
Min Typ
Max
Units
Power Supplies
Digital
Analog
VD
VA
-0.3
-0.3
-
-
6.0
6.0
V
V
Input Current
(Note 25)
-
-
10.0
mA
Analog Input Voltage
(Note 26)
-0.7
-
(VA)+0.7
V
Digital Input Voltage
(Note 26)
-0.7
-
(VD)+0.7
V
Ambient Temperature
(Power Applied)
-55
-
+125
C
Storage Temperature
-65
-
+150
C
Parameters
Symbol
Min Typ
Max
Units
Power Supplies
Digital
|VA - VD| < 0.4V
Analog
VD
VA
4.75
4.75
5.0
5.0
5.25
5.25
V
V
Operating Ambient Temperature
T
A
-10
25
70
C
Parameters
Symbol
Min Typ
Max
Units
High-level Input Voltage
(except XTI)
V
IH
2.8
-
(VD)+0.3
V
Low-level Input Voltage
(except XTI)
V
IL
-0.3
-
0.8
V
High-level Output Voltage at I
0
= -2.0 mA
(except XTO)
V
OH
(VD)-1.0
-
-
V
Low-level Output Voltage at I
0
= 2.0 mA
(except XTO)
V
OL
-
-
0.4
V
High-level Input Voltage
(XTI)
V
IH
2.8
-
-
V
Low-level Input Voltage
(XTI)
V
IL
-
-
2.3
V
Input Leakage Current
(Digital Inputs)
-
-
10
A
Output Leakage Current
(High-Z Digital Outputs)
-
-
10
A
Parameters
Symbol
Min
Typ
Max
Units
Output Rise Time
t
rpo
-
200
-
ns
Output Fall Time
t
fpo
-
200
-
ns
CS4812
14
DS291PP3
2. TYPICAL CONNECTION DIAGRAMS
Ferrite Bead
+ 1 F
0.1
F
43
VA 1..3
VD 1..2
AGND1..4
DGND1..4
XTO XTI
46
45
Optional External
Clock Input instead
of Crystal
44
7
AOUT1+
9
AOUT2+
37
PIO2
35
PIO3
Control/
Monitor
Circuitry
72
69
SPI/I2C
Mode/Reset
Circuit
All unused inputs
should be tied to ground.
CS4812
40
PIO1
41
ANALOG
FILTER
R
= 33
S
65
66
64
70
SCPM/S
RST
PIO0
88
18
8
AOUT1-
10
AOUT2-
13
89
19
42
11
39 pF
RESET
1 M
39 pF
D
A
D
D
D
D
D
A
A
D
82
83
RES-DGND
RES-DGND
+ 1 F
0.1
F
12
+5 V
32
34
36
57
RES-DGND
58
38
48
59
RES-DGND
RES-DGND
RES-NC
RES-NC
RES-NC
RES-DGND
RES-DGND
14
15
16
17
20
21
22
23
RES-NC
RES-NC
RES-NC
RES-NC
RES-NC
RES-NC
RES-NC
RES-NC
ANALOG
FILTER
ANALOG
FILTER
86
AIN1L+
87
AIN1L-
90
AIN1R+
91
AIN1R-
ANALOG
FILTER
92
1
F
CMOUT
To Optional
Input and
Output Buffers
0.1 F
A
A
OVL
39
93
94
0.1 F
1 F
+
CMFILT+
CMFILT-
A
63
62
68
67
Microcontroller
SCL/CCLK
SDA/CDOUT
AD0/CS
AD1/CDIN
71
REQ
2.2
K
2.2
K
VD VD
Program ROM
or
Serial EEPROM
D
Q
74HC74
47
R
S
CLKOUT
95
97
RES-NC
RES-NC
96
RES-DGND
60
61
RES-NC
RES-NC
73
RES-VD
VD
Figure 5. Typical Connection Diagram, Control Port Slave Mode
CS4812
DS291PP3
15
63
62
68
67
I C
EEPROM
SCL/CCLK
SDA/CDOUT
AD0/CS
AD1/CDIN
72
PLLEN
69
SPI/I2C
Reset
Circuit
71
REQ
70
73
SCPM/S
RST
CS4812
2
2.2 K
2.2 K
VD VD
A0
A1
A2
VD
RESET
D
D
Figure 6. Typical Connection Diagram, Control Port
I
2
C Master Mode
63
62
68
67
SPI
EEPROM
SCL/CCLK
SDA/CDOUT
AD0/CS
AD1/CDIN
72
PLLEN
69
SPI/I2C
Reset
Circuit
71
REQ
70
73
SCPM/S
RST
CS4812
RESET
VD
D
Figure 7. Typical Connection Diagram, Control Port
SPI Master Mode
CS4812
16
DS291PP3
2.2 K
VD
D
SDA
SCL
GPIO
SDA/CDOUT
SCL/CCLK
CLKOUT
AD0/CS
AD1/CDIN
REQ
CS4812
R
S
74HC74
RESET
CIRCUIT
RST
PLLEN
SPI/I2C
SCPM/S
D
VD
MICRO
CONTROLLER
2.2 K
VD
Figure 8. Typical Connection Diagram, Control Port
I
2
C Slave Mode
MISO
D
CCLK
CS
MOSI
GPIO
SDA/CDOUT
SCL/CCLK
CLKOUT
AD0/CS
AD1/CDIN
REQ
CS4812
R
S
74HC74
RESET
CIRCUIT
RST
PLLEN
SPI/I2C
SCPM/S
D
VD
MICRO
CONTROLLER
Figure 9. Typical Connection Diagram, Control Port
SPI Slave Mode
CS4812
DS291PP3
17
3. FUNCTIONAL DESCRIPTION
3.1
Overview
The CS4812 is a complete audio subsystem on a
chip, integrating an DSP with on-chip RAM, two
24-bit ADCs, two 24-bit DACs, and a serial control
port.
The sigma-delta ADCs include linear phase digital
anti-aliasing filters and only require a single-pole
external passive filter.
The sigma-delta DACs include analog switched-
capacitor anti-image filters and require an external
second or third order active filter that can be easily
integrated into an output differential-to-single-end-
ed converter circuit.
The serial control port is designed to accommodate
I
2
C
or SPI interfaces and can operate in master or
slave mode. It allows interfacing to external non-
volatile memory for stand-alone operation or to a
host-controller for real-time control. All communi-
cations between the DSP and an external EEPROM
or host-controller are handled through the serial
control port.
3.2
Analog Inputs
3.2.1
Line Level Inputs
AINR+, AINR-, AINL+, and AINL- are the line
level analog inputs (See Figure 5). These pins are
internally biased to the CMOUT voltage of 2.3 V.
A DC blocking capacitor placed in series with the
input pins allows signals centered around 0 V to be
input to the CS4812. Figure 5 shows operation with
a single-ended input source. This source may be
supplied to either the positive or negative input as
long as the unused input is connected to ground
through capacitors as shown. When operated with
single-ended inputs, distortion will increase at in-
put levels higher than -1 dBFS. If better perfor-
mance is required, a single-ended-to-differential
converter, shown in Figure 10, may be used. It pro-
vides unity gain, DC blocking and anti-alias filter-
ing.
Inputs may be externally AC or DC coupled. This
permits use of the ADCs for input of audio signals
or for measurement of DC control voltages. By de-
fault, an internal high pass filter removes any DC
offsets from both of the ADC inputs. If measure-
ment of DC is required on either of the ADC inputs,
then the on-chip high pass filter must be disabled.
Analog audio input signals that are DC coupled
must be biased at 2.3 V to maintain proper input
+
-
10 k
+
-
4.7 k
AIN -
10
F
+
AIN +
2.2 nf
150
150
10 k
10 k
input signal
+
(2 Vrms max)
+5 V
CMOUT
+
-
0.1
F
10 f
GND
Figure 10. Recommended Line Input Buffer
CS4812
18
DS291PP3
signal swing. DC control input voltages may range
from ground to Vcc.
ADC output data is in twos-complement binary
format. For inputs above full scale, the ADC digital
output saturates. The OVL output pin asserts when
the analog input is out-of-range.
3.2.2
Digital High Pass Filter
In DC coupled systems, a small DC offset may ex-
ist between the input circuitry and the A/D convert-
ers. The CS4812 includes a defeatable high pass
filter after the decimator to remove these DC com-
ponents. The high pass filter response is given in
"High Pass Filter Characteristics" on page 4 and
scales linearly with sample rate. In applications
where DC level measurement is required, as would
occur when one of the ADC inputs is used for mea-
surement of DC control voltages, the high pass fil-
ter may be disabled via a control port register.
Note: The high pass filter defeat operates on both
ADC inputs simultaneously therefore external DC
blocking must be provided in the design of the an-
alog audio input circuit.
3.3
Analog Outputs
3.3.1
Line Level Outputs
The CS4812 contains on-chip differential buffer
amplifiers that produce line level outputs capable
of driving 10 k
loads to full scale. These amplifi-
ers internally biased to the CMOUT voltage of 2.3
V.
The recommended off-chip analog filter is a second
order Butterworth with a 3 dB corner at Fs. A third
order Butterworth filter with a -3 dB corner at 0.75
Fs can be used if greater out of band noise filtering
is desired. These filters can be easily integrated into
a differential-to-single-ended converter circuit as
shown in the 2-pole and 3-pole Butterworth filters
of Figure 12. The hardware mute circuit referenced
in Figure 12 is shown in Figure 13. Hardware mut-
ing is recommended on power-up and power-
down.
CS4812
AIN
AIN
150
22 F
2.2 nF
100 F
0.1 F
+
Figure 11. Single Ended Input
2-Pole Butterworth Filter
BUFFERED
CMOUT
_
+
A
OU
T-
Line
Out
14.0 k
14.0 k
A
OUT+
3.24 k
3.24 k
1000 pF
1000 pF
14.0 k
220 pF
220 pF
14.0 k
GND
+5 V
BUFFERED
CMOUT
_
+
Line
Out
A
OU T+
A
OU T-
220 pF
220 pF
2200 pF
2.8k
2.8k
2.8k
2.8k
11.0k
11.0k
14.0k
14.0k
2200 pF
2200 pF
2200 pF
GND
+5 V
3-Pole Butterworth Filter
Output
Mute Ckt
Output
Mute Ckt
Figure 12. Butterworth Output Filters
CS4812
DS291PP3
19
3.4
Clock Generation
The CS4812 master clock may be generated by us-
ing the on-chip oscillator with an external crystal or
may be derived from an external clock source.
3.4.1
Clock Source
The CS4812 requires a 256 Fs master clock to run
the internal logic. The two possible clock sources
are the on-chip crystal oscillator or an external clock
input to the XTI pin.
When using the on-chip crystal oscillator, external
loading capacitors are required. (see Figure 5) High
frequency crystals (>8 MHz) should be parallel
resonant, fundamental mode and designed for
20 pF loading. (equivalent to 40 pF to ground on
each leg)
3.5
Serial Control Port
The serial control port contains all of the main con-
trol logic for the chip. It controls power-on se-
quencing, hardware configuration and DSP
operation. In AutoBoot mode, the serial control
port manages the entire boot process including ini-
tialization of its own hardware configuration regis-
ters from EEPROM, code download from the
EEPROM to the DSP and initialization of the CO-
DEC. In host-controlled mode, the host-device ini-
tializes the hardware configuration registers and
downloads the application code to the DSP via 2
dedicated control port registers. Application mes-
saging between the host and the DSP is also done
via these control port registers. The operation of the
control port may be completely asynchronous to
the audio sample rate. However, it is recommended
that the control port pins remain static when not in
use.
The required control port register settings are con-
tained in the Crystal effects firmware application
code EEPROM image.
The control port supports the SPI bus and the I
2
C
bus in both master and slave modes. The bus inter-
face is selected via the SPI/I
2
C pin and the mas-
ter/slave mode is selected via the SCPM/S pin.
These pins are sampled during de-assertion of the
RST pin.
Master mode is selected for stand-alone operation
when AutoBooting from an external serial EE-
PROM. Slave mode is selected when the CS4812 is
connected to an external host controller.
3.5.1
SPI Bus
The SPI bus interface consists of 5 digital signals,
CCLK, CDIN, CDOUT, CS and REQ. CCLK, the
control port bit clock, is used to clock individual data
bits. CDIN, the control data input, is the serial data
input line to the CS4812. CDOUT, the control data
output, is the output data line from the CS4812. It is
open-drain and requires a 2.2 k
pull-up resistor.
CS, the chip select signal, is asserted low to enable
the SPI port. REQ, the request pin, is used by the
DSP to request a read by a host controller when op-
erating in control port slave mode. Data is clocked
into the chip on the rising edge of CCLK and out on
the falling edge. When in slave mode, the CLK sig-
nal must be synchronous with the internal DSP
clock. An external D flip flop off of CLKOUT as
shown in Figure 9 can be used to retime the CLK sig-
nal. There is limited drive capability on CLKOUT so
Line Out
VA
From
CS4812
PIO
MMBT3906
MMBT3904
MMBT3906
10 k
10 k
10 k
GND
3.3 k
10
F
1 k
10
F
+
From Op-Amp
Figure 13. Output Mute Circuit
CS4812
20
DS291PP3
a buffer may be required to minimize the capacitive
loading on CLKOUT.
CCLK and CS may be inputs or outputs with respect
to the CS4812. If the serial control port of the
CS4812 is defined as the master, then CCLK and CS
are outputs and CCLK requires a 2.2 k
pull-up re-
sistor. If the CS4812 is defined as the slave, then
CCLK and CS are inputs and no pull-up resistor is re-
quired on CCLK.
3.5.1.1
SPI Master Mode
The SPI master mode is designed for read-only op-
eration during AutoBooting from a serial EE-
PROM. A typical AutoBoot sequence with a Xicor
X25650 serial EEPROM, or equivalent, is shown in
Figure 14. On exit from reset, the CS4812 asserts CS.
The 8-bit read instruction (00000011) is sent to the
EEPROM followed by a pre-defined 16-bit start ad-
dress.The CS4812 then automatically clocks out se-
quential bytes from the EEPROM until the last byte
has been received. After the last byte is received, the
CS4812 deasserts CS and begins program execution.
At this point, the serial control port becomes inactive
until the next reset.
3.5.1.2
SPI Slave Mode
In SPI slave mode, a write sequence from an exter-
nal host controller is shown in Figure 15. The host
controller asserts CS and sends a 16-bit write pre-
amble to the CS4812. This preamble consists of a
7-bit chip address (must be 0010000) followed by
a one-bit R/W (Read/Write) bit (set to 0 for write)
0 1 2
21 22 23 24
CS
CDOUT
READ
COMMAND
16-BIT
ADDRESS = 0X0000
CDIN
DATA
MSB
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0
0 0 0 0 0 0 1 1
CLK
7 8 9 10 11
3 4 5 6
30 31
25 26 27 28 29
DATA + n
7 6 5 4 3 2 1 0
Figure 14. Control Port Timing, SPI Master Mode AutoBoot
CDOUT
CS
CLK
12 13 14 15
CDIN
CHIP ADDRESS (WRITE)
MAP BYTE
0 0 1 0 0 0 0 0
MSB
DATA
DATA +n
R/W
6 5 4 3 2 1 0
8 9 10 11
4 5 6 7
0 1 2 3
16 17 18 19 20 21 22
INCR
23
(input)
(input)
(input)
(output)
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Figure 15. Control Port Timing, SPI Slave Mode Write
CS4812
DS291PP3
21
and a memory address pointer (MAP) byte. The
MAP byte contains the address of the control port
register to be accessed. Following the preamble,
the host controller sends the actual data byte to be
written to the register designated by the MAP. The
host controller then de-asserts CS. Figure 16 shows
the SPI slave mode write flow diagram.
In SPI slave mode, a read sequence from an exter-
nal controller is shown in Figure 17. The host con-
troller executes a partial write-cycle by sending a
16-bit write preamble to the CS4812 with the MAP
byte set to the address of the control port byte reg-
ister to be read. The host controller then de-asserts
CS, re-asserts CS, and sends the 7-bit chip address
followed by the R/W bit set to 1. The host control-
ler then clocks out the control port register desig-
nated by the MAP byte. The host controller then
de-asserts CS. Figure 18 shows the SPI mode slave
read flow diagram initiated by the host microcon-
troller. Figure 19 shows the SPI slave mode read
flow diagram incorporating the DSP REQ signal.
REQ is used to notify the host controller that a data
byte from the DSP is waiting to be read.
The behavior of the REQ signal is dependent on
when data is written to the serial control port output
register in relation to CCLK and bit 2 of the current
byte being transferred. There are three cases of
REQ behavior:
1. The REQ line will be de-asserted immediately
following the rising edge of CCLK on the D2 bit of
the current byte being transferred if there is no data
in the serial control port output register. The REQ
line remains de-asserted and a stop condition
SET CS LOW
WRITE DATA BYTE
MORE DATA?
SET CS HIGH
Y
WRITE MAP BYTE
N
WRITE ADDRESS BYTE
WITH R/W BIT = 0
Figure 16. SPI Slave Write Flow Diagram
CDOUT
CS
CLK
CDIN
10 11 12
CHIP ADDRESS (WRITE)
MAP BYTE
MSB
R/W
CHIP ADDRESS (READ)
R/W
0 0 1 0 0 0 0 0
INCR
6 5 4 3 2 1 0
0 0 1 0 0 0 0 1
REQ
0 1 2 3
4 5 6 7 8 9
13 14 15
DATA
7 6 5 4 3 2 1 0
(input)
(output)
(input)
(input)
(output)
DATA
7 6 5 4 3 2 1 0
Figure 17. Control Port Timing, SPI Slave Mode Read
CS4812
22
DS291PP3
should be issued by the bus master, thus complet-
ing the transfer.
2. If data is written to the serial control port output
register prior to the rising edge of CCLK for the D2
data bit, REQ will remain asserted. The bus master
should continue to shift out this new byte.
3. If data is placed in the SCP output register by the
DSP after the rising edge of CCLK for the D2 bit,
REQ will be immediately re-asserted, thus creating
a pulse on REQ. The byte in the SCP out register
may be read by the bus master as part of the current
transaction or may be read later as part of a new
read transaction.
The CS4812 has a MAP auto increment capability
which allows block reads or writes of successive
control port registers.This feature is enabled by set-
ting the INCR bit in the MAP byte.
During a write sequence, multiple bytes may be
written by continuing to send data bytes to the
CS4812 after the first data byte and before de-as-
serting CS. If auto increment is disabled, the last
data byte sent will appear in the register designated
by the MAP. If auto increment is enabled, data
bytes sent following the first data byte will be writ-
ten to successive registers following that designat-
ed in the MAP.
SET CS LOW
WRITE ADDRESS BYTE
READ DATA BYTE
MORE BYTES
SET CS HIGH
Y
WRITE ADDRESS BYTE
WRITE MAP BYTE
N
TOGGLE CS
WITH R/W BIT = 0
WITH R/W BIT = 1
Figure 18. SPI Slave Mode Read Flow Diagram
TO READ?
Figure 19. SPI Slave Mode Read from DSP Core
Flow Diagram using DSP REQ
SET CS LOW
WRITE ADDRESS BYTE
READ DATA BYTE
REQ STILL LOW?
SET CS HIGH
N
Y
WRITE ADDRESS BYTE
WRITE MAP BYTE FOR
REQ LOW?
Y
N
TOGGLE CS
WITH R/W BIT = 0
WITH R/W BIT = 1
DSP OUTPUT REGISTER
(MAP = 0
X
27)
FROM DSP OUTPUT REGISTER
CS4812
DS291PP3
23
During a read sequence, multiple bytes may be read
by continuing to clock out data bytes to the CS4812
after the first data byte and before de-asserting CS.
If auto increment is disabled, the last data byte read
will be the register designated by the MAP. If auto
increment is enabled, data bytes read following the
first data byte will be read from successive registers
following that designated in the MAP.
3.5.2
I
2
C Bus
The I
2
C bus interface implemented on the CS4812
consists of 3 digital signals, SCL, SDA and REQ.
SCL, or serial clock, is used to clock individual
data bits. SDA, or serial data, is a bidirectional data
line. REQ, the request pin, is used by the DSP to re-
quest a host read when operating in control port
slave mode. Two additional pins, AD1 and AD0,
are inputs which determine the 2 lowest order bits
of the 7-bit I
2
C device address.
SCL may be defined as an input or an output with
respect to the CS4812. If the serial control port of
the CS4812 is defined as the master, then SCL is an
open-drain output and requires a pull-up resistor as
shown in Figure 5. Conversely, if the serial control
port of the CS4812 is defined as the slave, then
SCL is an input.
SDA carries time-multiplexed bidirectional serial
data. It is open-drain and requires a pull-up resistor
as shown in Figure 5.
AD1 and AD0, the inputs which determine the 2
lowest order bits of the 8-bit I
2
C device address, are
meaningful only when the CS4812 is operating as
a slave device and may be tied to ground when the
CS4812 is configured for master mode.
When operating in control port slave mode, the
REQ output pin is used by the CS4812 DSP to re-
quest communication with the master.
3.5.2.1
I
2
C Master Mode
The I
2
C master mode is designed for read-only op-
eration during AutoBooting from a serial EE-
PROM. A typical AutoBoot sequence with a
Microchip X24256 serial EEPROM, or equivalent,
is shown in Figure 20. On exit from reset, the
CS4812 sends an initial write preamble to the EE-
PROM which consists of a I
2
C start condition and
the slave address byte. The slave address consists
of the 4 most significant bits set to 1010, the fol-
lowing 3 bits corresponding to the device select
bits, A2, A1 and A0 set to 000 and the last bit (R/
W
)
set to 0. Following this, a 2-byte EEPROM starting
address of 0x0000 is sent to the EEPROM. The 2-
byte EEPROM starting address uses only the low-
est 13 bits and sets the highest 3 bits to zero. To be-
gin reading from the EEPROM, the CS4812 sends
another start condition followed by a read pream-
ble. The read preamble is identical to the write pre-
amble except for the state of the R/
W
bit. The
CS4812 then automatically clocks out sequential
bytes from the EEPROM until the last byte has
been received. These bytes include initial values
for all control port registers as well as the DSP ap-
plication code. After the last byte, the CS4812 ini-
tiates a stop condition and begins program
execution. At this point, the serial control port be-
comes inactive until the next reset. Actual EE-
0 1 2 3
16 17 18 19
25 26 27 28 29
CHIP ADDRESS (WRITE)
CHIP ADDRESS (READ)
MEMORY ADDRESS
DATA
DATA +n
START
ACK
NO
START
STOP
ACK
ACK
ACK
ACK
1 0 1 0 A
2
A
1
A
0
0
0 0 0
0 0 0
1 0 1 0 A
2
A
1
A
0
1
7 0
7 0
SCL
SDA
34 35 36 37
30 31 32 33
8 9 10
4 5 6 7
Figure 20. Control Port Timing, I
2
C Master Mode AutoBoot
CS4812
24
DS291PP3
PROM memory mapping is handled automatically
by the development tools and is transparent to the
designer.
3.5.2.2
I
2
C Slave Mode
In I
2
C slave mode, a write sequence from an exter-
nal host controller is shown in Figure 22.. The host
controller sends a write preamble consisting of a
start condition followed by the slave address for the
CS4812. The slave address byte consists of a 7-bit
address field (00100|AD1|AD0) followed by a
Read/Write bit (set to 0). AD1 and AD0 correspond
to the logic levels applied to the these pins on the
CS4812. The host controller then sends a MAP
byte which contains the address of the control reg-
ister to be accessed followed by the actual data byte
to be written to the register designated by the MAP.
Upon completion of this, the host controller then
sends a stop condition to complete the transaction.
Figure 21 shows the I
2
C slave mode write flow di-
agram
In I
2
C slave mode, a read sequence by an external
host controller is shown in Figure 23. The host con-
troller sends a write preamble to the CS4812 which
4 5 6 7
24 25
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
0 0 1 0 0 AD1 AD0 0
SDA
INCR
6 5 4 3 2 1 0
7 6 1 0
7 6 1 0
7 6 1 0
0 1 2 3
8 9
12
16 17 18 19
10 11
13 14 15
27 28
26
DATA +n
Figure 22. Control Port Timing, I
2
C Slave Mode Write
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
0 0 1 0 0 AD1 AD0 0
SDA
0 0 1 0 0 AD1 AD0 1
CHIP ADDRESS (READ)
START
INCR
6 5 4 3 2 1 0
7 0
7 0
7 0
NO
16
8 9
12 13 14 15
4 5 6 7
0 1
20 21 22 23 24
26 27 28
2 3
10 11
17 18 19
25
ACK
REQ
DATA + n
Figure 23. Control Port Timing, I
2
C Slave Mode Read
SEND I
2
C START
WRITE ADDRESS BYTE
WITH R/W BIT = 0
GET ACK
SEND DATABYTE
MORE DATA?
N
Y
GET ACK
SEND I
2
C STOP
GET ACK
SEND MAP BYTE
Figure 21. I
2
C Slave Mode Write Flow Diagram
CS4812
DS291PP3
25
consists of a start condition followed by its slave
address byte with the Read/Write bit set to 0. The
host controller then initiates a read preamble. The
read preamble is identical to the write preamble ex-
cept for the state of the Read/Write bit. The host
controller then sends a MAP byte which contains
the address of the control register to be accessed.
After receiving the MAP byte, the CS4812 returns
the contents of this register to the host controller.
The host controller may continue reading registers
by sending additional MAP bytes or complete the
transaction by initiating a stop condition. Figure 24
shows the SPI mode slave read flow diagram initi-
ated by the host microcontroller. Figure 25 shows
the I
2
C slave mode read flow diagram incorporat-
ing the DSP REQ signal. REQ is used to notify the
host controller that a data byte from the DSP is
waiting to be read.
The behavior of the REQ signal is dependent on
when data is written to the SCP output register in
relation to SCL and bit 1 of the current byte being
transferred. There are three cases of REQ behavior:
1. The REQ line will be de-asserted immediately
following the rising edge of SCL on the D1 bit of
the current byte being transferred if there is no data
in the SCP output register. The REQ line remains
de-asserted and a stop condition should be issued
by the bus master, thus completing the transfer.
2. If data is written to the SCP output register prior
to the rising edge of SCL for the D1 bit, REQ will
remain asserted. The bus master should continue to
shift out this new byte.
3. If data is placed in the SCP output register by the
DSP after the rising edge of SCL for the D1 bit,
REQ will be immediately re-asserted, thus creating
a pulse on REQ. The byte in the SCP out register
may be read by the bus master as part of the current
transaction or may be read later as part of a new
read transaction.
The CS4812 has a MAP auto increment capability
which allows block reads or writes of successive
control port registers.This feature is enabled by set-
ting the INCR bit in the MAP byte.
During a write sequence, multiple bytes may be
written by continuing to send data bytes to the
CS4812 after the first data byte and before initiat-
ing a stop condition. If auto increment is disabled,
the last data byte sent will appear in the register
designated by the MAP. If auto increment is en-
SEND I
2
C START
WRITE ADDRESS BYTE
WITH R/W BIT = 0
GET ACK
READ DATABYTE
MORE BYTES
N
Y
SEND ACK
SEND NACK
SEND I
2
C STOP
GET ACK
WRITE ADDRESS BYTE
WITH R/W BIT = 1
GET ACK
SEND I
2
C START
SEND MAP BYTE
Figure 24. I
2
C Slave Mode Read Flow Diagram
TO READ?
CS4812
26
DS291PP3
abled, data bytes sent following the first data byte
will be written to successive registers following
that designated in the MAP.
During a read sequence, multiple bytes may be read
by continuing to clock in data bytes to the CS4812
after the first data byte and before initiating a stop
condition. If auto increment is disabled, the last
data byte read will be the register designated by the
MAP. If auto increment is enabled, data bytes read
following the first data byte will be read from suc-
cessive registers following that designated in the
MAP.
3.6
Boot Modes
There are two different techniques that allow the
system to load the application code into the
CS4812. The first technique is called, "AutoBoot"
and allows the application code to be loaded from
an external serial EEPROM with an I2C or SPI in-
terface. This technique is used in system applica-
tions that due not have a host. The second
technique is called, "Host Boot" and allows the ap-
plication code to be loaded directly from the host
microcontroller via I2C or SPI communication in-
terface. This method may eliminate the need for an
external EEPROM.
3.6.1
AutoBoot
The AutoBoot method simply requires an external
EEPROM with an I
2
C or SPI serial bus interface.
The DSP, automatically loads and runs the applica-
tion code resident in the EEPROM upon deasser-
tion of the RESET line. It should be noted that this
technique is used for systems that do not have a mi-
crocontroller and do not require real-time adjust-
ment of the application code parameters. Please
refer to Table 10 on page 6 for the timing require-
ments of the RESET line.
3.6.2
HostBoot
By using the HostBoot technique, an external mi-
crocontroller is required to download the applica-
Figure 25. I
2
C Slave Mode Read from DSP Core
Flow Diagram with DSP REQ
N
REQ LOW?
Y
SEND I
2
C START
WRITE ADDRESS BYTE
WITH R/W BIT = 0
GET ACK
READ DATABYTE
REQ STILL LOW?
N
Y
SEND ACK
SEND NACK
SEND I
2
C STOP
GET ACK
WRITE ADDRESS BYTE
WITH R/W BIT = 1
GET ACK
SEND I
2
C START
SEND MAP BYTE
CS4812
DS291PP3
27
tion code. This technique allows for real-time
control of all parameters specific to the application
code. Please refer to Figure 26 for the HostBoot
procedure flow chart and to Section 1.2.1 of
AN195 for an example of a host boot sequence.
3.7
Resets
There are several reset mechanisms in the CS4812
which affect different parts of the chip. Full chip re-
set can only be achieved by asserting the external
RST pin. With RST asserted, the chip enters low
power mode during which the control port, CO-
DEC and DSP are reset, all registers are returned to
their default values and the DAC outputs are mut-
ed. The RST pin should be asserted during power-
up until the power supplies have reached steady
state.
If the supply voltage drops below 4 Volts, the CO-
DEC is reset, the DAC outputs are muted and the
DSP automatically executes a soft reset.
Upon exit from a CODEC reset, the DSP restarts
the application code and the CODEC performs the
following procedure:
The CODEC resynchronizes.
The DAC outputs unmute.
Figure 26. HostBoot Flow Diagram
WRITE BYTE 0
X
A4
TO CONTROL PORT
REGISTER 4 (MAP = 4)
WRITE BYTE 0
X
A5
TO CONTROL PORT
REGISTER 4
WRITE BYTE 0
X
A7
TO CONTROL PORT
REGISTER 4
SEND 3 BYTE MESSAGE TO
THE DSP INPUT REGISTER
(MAP = 3) :0
X
000004
WAIT FOR REPLY FROM DSP
(REQ LINE GOES LOW)
READ REPLY BYTE FROM DSP
OUTPUT REGISTER (MAP = 27)
N
Y
REPLY BYTE
= 0
X
01?
WRITE .LDT FILE INTO
DSP INPUT REGISTER (MAP = 16)
(LOAD APPLICATION CODE)
REQ
LOW?
READ REPLY BYTE FROM DSP
OUTPUT REGISTER (MAP = 27)
N
Y
REPLY BYTE
= 0
X
02?
SEND 3 BYTE MESSAGE TO
THE DSP INPUT REGISTER
(MAP = 16):0
X
000005
WRITE BYTE 0
X
A6
TO CONTROL PORT
REGISTER 4
SEND APPLICATION
SPECIFIC CONTROL PORT
CONFIG BYTES
N
Y
CS4812
28
DS291PP3
4. POWER SUPPLY AND GROUNDING
Proper layout and grounding is critical to obtaining
optimal audio performance in your system. The
most important rule to remember is to not allow
currents from digital circuitry to couple into sensi-
tive analog circuitry. This is generally done by us-
ing a separate or filtered power supply for the
analog circuitry, physically separating the analog
and digital components and traces in the pcb layout
and using wide traces or planes for ground and
power. One misplaced component or trace can se-
verely degrade overall system performance.
When using separate supplies, the analog and digi-
tal power should be connected to the CS4812 via a
ferrite bead, positioned closer than 1" to the device
(see Figure 21). The CS4812 VA pin should be de-
rived from the quietest power source available. If
only one supply is available, use the suggested ar-
rangement in Figure 5.
A single solid ground plane is the simplest ground-
ing scheme that works well in many cases. All an-
alog and digital grounds shown in Figure 5 should
be tied to the one plane.
Decoupling capacitors should be placed as close as
possible to the device with the lowest value capac-
itor closest to the chip. Any power and ground con-
nection vias should be placed near their respective
component pins and should be attached directly to
the appropriate plane. If traces are used for the
power supplies to the CS4812, they should be as
wide as possible to maintain low impedance.
It is recommended to solder the CS4812 directly to
the printed circuit board. Soldering improves per-
formance and enhances reliability
Digital
Power
Plane
Note that the CS4812
is oriented with its
digital pins towards the
digital end of the board.
Digital Interface
Analog Signals &
Components
Analog
Power
Plane
1/8"
>
CS4812
Ferrite
Bead
Figure 27. CS4812 Suggested Layout
CS4812
DS291PP3
29
5. PIN DESCRIPTIONS
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DGND
AD1/CDIN
AD0/CS
SPI/I2C
SCPM/S
REQ
RST
RES-VD
NC
NC
NC
NC
NC
NC
NC
NC
RES-DGND
RES-DGND
NC
NC
AINL+
AINL-
VA
AGND
AINR+
AINR-
CMOUT
CMFILT+
CMFILT-
RES-NC
RES-DGND
RES-NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AOUT1+
AOUT1-
AOUT2+
AOUT2-
AGND
VA
AGND
RES-NC
VD
DGND
SCL/CCLK
SDA/CDOUT
RES-NC
RES-NC
RES-NC
RES-NC
RES-NC
NC
NC
NC
NC
NC
NC
NC
NC
RES-DGND
CLKOUT
XTO
XTI
DGND
VD
DGND
PIO0
PIO1
OVL
RES-DGND
PIO2
RES-DGND
PIO3
RES-DGND
NC
RES-DGND
NC
NC
NC
NC
NC
NC
NC
NC
RES-NC
RES-NC
RES-NC
RES-NC
AGND
VA
RES-NC
RES-NC
CS4812
100-PIN MQFP
RES-NC
Figure 28. Pin Assignments
CS4812
30
DS291PP3
Power Supply
VA - Analog Power
Power: analog supply, +5V.
AGND - Analog Ground
Ground: analog ground.
VD - Digital Power
Power: digital supply, +5V.
DGND - Digital Ground
Ground: digital ground.
Analog Inputs
AINL+/-,AINR+/- - Differential Analog Inputs
Inputs: These pins accept differential analog input signals and are internally biased to the reference
voltage of 2.3 V. The + and - input signals should be 180 out of phase. A single-ended signal may also
be directly applied to either the + or - input with the other input AC coupled to ground through a
capacitor. In general, differential input signals provide better performance. For best audio performance,
a passive anti-aliasing filter is required. The typical connection diagram in Figure 5. shows the
recommended single-ended input circuit. Figure 10 shows the recommended differential input circuit.
Inputs may be externally AC or DC coupled. This permits use of the ADCs for input of audio signals or
for measurement of DC control voltages. By default, an internal high pass filter removes any DC offsets
from both of the ADC inputs. If measurement of DC is required on either of the ADC inputs, then the
internal high pass filter must be disabled. Analog audio input signals that are DC coupled must be
biased at 2.3 V to maintain proper input signal swing. DC control input voltages may range from ground
to Vcc and should be applied to only the + or - input with the other input coupled to ground through a
capacitor.
OVL - ADC Overload Indicator
Output: This pin is asserted if either ADC is clipping. The pin does not latch and de-asserts when
clipping stops.
Analog Outputs
AOUT1+/-, AOUT2+/- - Differential Audio Outputs
Outputs: These pins output differential analog signals which are biased to the internal reference voltage
of approximately 2.3V. The + and - output signals are 180 out of phase resulting in a nominal
differential output voltage of twice the output pin voltage. For best performance, an anti-imaging filter is
required. Figure 12 shows the recommended second and third order Butterworth differential-to-single-
ended output buffer circuits.
Voltage Reference
CMOUT - Common Mode Output
Output: This pin provides an internally generated reference of 2.3V to be used for biasing external
analog circuitry. The load on CMOUT must be DC only, with an impedance of not less than 50 k
.
CMFILT+,CMFILT- - Common Mode Filter Connections
Inputs: These pins are connections for external filter components required by the internal common mode
reference circuit. See the typical connection diagram in Figure 5. for details.
CS4812
DS291PP3
31
Serial Control Port
SCPM/S - Serial Control Port Master/Slave Select
Input: This pin configures the serial control port as a master if tied to VD or a slave if tied to DGND.
SPI/I
2
C - Serial Control Port Format Select
Input: This pin configures the control port for I
2
C format if tied to VD or SPI format if tied to DGND.
SCL/CCLK - Serial Control Port Clock
Bidirectional: This pin clocks serial control port data into and out of SDA in I
2
C mode. In SPI mode, it
clocks control port data into CDIN and out of CDOUT. When the serial control port is configured as a
master, SCL/CCLK is an output and is generated internally. When the serial control port is configured as
a slave, SCL/CCLK is an input and may operate asynchronously to the master clock.
AD0/CS - I
2
C Address Bit 0 / SPI Chip Select
Bidirectional: In I
2
C
mode, AD0 is an input and defines bit 0 of the partial chip address. The upper 5
bits of the 7-bit address must be 00100. In SPI mode, CS is the chip select pin. When the serial control
port is defined as a master in SPI mode, CS is an output. When the serial control port is defined as a
slave in SPI mode, CS is an input.
AD1/CDIN - I
2
C Address Bit 1 / SPI Data Input
Input: In I
2
C
mode, AD1 is an input and defines bit 1 of the partial chip address. The upper 5 bits of
the 7-bit address must be 00100. In SPI mode, CDIN is the serial control port data input and is clocked
in on the rising edge of CCLK.
SDA/CDOUT - I
2
C Data / SPI Data Output
Bidirectional: In I
2
C
mode, SDA is the bidirectional data I/O line. In SPI mode, CDOUT is the serial
control port data output and is clocked out on the falling edge of CCLK.
REQ - DSP Output Request
Output: This pin is used when the serial control port is configured for slave mode operation. This pin is
asserted when the DSP has written a byte to a register in the control port. When this register is read by
the master device, REQ is de-asserted.
Clock and Crystal
XTI, XTO - Crystal Oscillator Connections (Master Clock)
Input, Output: These pins provide connections for an external parallel resonant quartz crystal.
Alternately, an external clock source may be applied to XTI. The clock frequency must be 256xFs.
CLKOUT - Clock Output
Output: This pin provides a clock output which can be used to synchronize external components.
Available output frequencies 1xFs, 128xFs and 256xFs are selectable via a control port register. The
default frequency is 256xFs. It is recommended to externally buffer this signal with a CMOS gate as
shown in Figure 5.
Miscellaneous
PIO0:3 - General Purpose Inputs/Outputs
Bidirectional: These pins are general-purpose digital I/O pins. The Default state is input. The
functionality of these pins after boot-up is determined by the application firmware code loaded into the
device during the boot-up process.
RST - Reset
Input: This pin causes the device to enter a low power mode and forces all control port and i/o registers
to be reset to their default values. The control port can not be accessed when reset is low.
CS4812
32
DS291PP3
NC - No Connect
Input: These pins are not internally connected and should be tied to ground for optimal performance.
RES-NC - Reserved, No Connect
These pins are reserved and must be left unconnected for normal operation.
RES-VD - Reserved, Connect to VD
These pins are reserved and must be tied to VD for normal operation.
RES-DGND - Reserved, Connect to DGND
These pins are reserved and must be tied to digital ground for normal operation.
RES-AGND - Reserved, Connect to AGND
These pins are reserved and must be tied to analog ground for normal operation.
CS4812
DS291PP3
33
6. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral components
over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified
bandwidth made with a -60 dbFs signal. 60 dB is then added to the resulting measurement to refer the
measurement to full scale. This technique ensures that the distortion components are below the noise
level and do not effect the measurement. This measurement technique has been accepted by the Audio
Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Total Harmonic Distortion + Noise
The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the
specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels.
ADCs are measured at -1dBFs as suggested in AES 17-1991 Annex A.
Idle Channel Noise / Signal-to-Noise-Ratio
The ratio of the RMS analog output level with 1kHz full scale digital input to the RMS analog output
level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units
in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991,
and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic
Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio.
Total Harmonic Distortion (THD)
THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of the test
signal. Units in decibels.
Interchannel Isolation
A measure of crosstalk between channels. Measured for each channel at the converter's output with no
signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Frequency Response
A measure of the amplitude response variation from 20Hz to 20kHz relative to the amplitude response
at 1kHz. Units in decibels.
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each channel. For
the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in
decibels.
Gain Error
The deviation from the nominal full scale output for a full scale input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
Offset Error
For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For
the DACs, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units
are in volts.
CS4812
34
DS291PP3
7. PACKAGE DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A
---
0.134
---
3.400
A1
0.010
0.014
0.250
0.350
B
0.009
0.015
0.220
0.380
D
0.667
0.687
16.950
17.450
D1
0.547
0.555
13.900
14.100
E
0.904
0.923
22.950
23.450
E1
0.783
0.791
19.900
20.100
e*
0.022
0.030
0.550
0.750
0.000
7.000
0.00
7.00
L
0.018
0.030
0.450
0.750
* Nominal pin pitch is 0.65 mm
Controlling dimension is mm.
JEDEC Designation: MS022
100L MQFP PACKAGE DRAWING
E1
E
D1
D
1
e
L
B
A1
A
Notes
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