Preliminary Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright

Cirrus Logic, Inc. 2002

P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com

CS4383

114 dB, 192 kHz 8-Channel D/A Converter

Features

24-Bit Conversion
Up to 192 kHz Sample Rates
114 dB Dynamic Range
-100 dB THD+N
Supports PCM and DSD Data Formats
Selectable Digital Filters
Volume Control with Soft Ramp

1 dB Step Size
Zero Crossing Click-Free Transitions

Dedicated DSD inputs
Low Clock Jitter Sensitivity

C or Stand-Alone Operation

3 Mute Control pins for Left, Right, and
Surrounds

Description

The CS4383 is a complete 8-channel digital-to-analog
system including digital interpolation, fifth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control and analog filtering. The advantages of
this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.

The CS4383 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, and operates over a
wide power supply range. These features are ideal for
multi-channel audio systems including DVD players,
SACD players, A/V receivers, digital TV's and VCR's,
mixing consoles, effects processors, set-top boxes, and
automotive audio systems.

ORDERING INFORMATION

CS4383-KQ

-10 to 70 °C

48-pin LQFP

CS4383-BQ

-40 to 85 °C

48-pin LQFP

CDB4383

Evaluation Board

E x t e r n a l

M u t e C o n t r o l

R S T

V o l u m e C o n t r o l

I n t e r p o l a t i o n F i l t e r

A n a l o g F i l t e r

D A C

M i x e r

V o l u m e C o n t r o l

D A C

A n a l o g F i l t e r

I n t e r p o l a t i o n F i lt e r

V o l u m e C o n t r o l

I n t e r p o l a t i o n F i l t e r

A n a l o g F i l t e r

D A C

M i x e r

V o l u m e C o n t r o l

D A C

A n a l o g F i l t e r

I n t e r p o l a t i o n F i lt e r

V o l u m e C o n t r o l

I n t e r p o l a t i o n F i l t e r

A n a l o g F i l t e r

D A C

M i x e r

V o l u m e C o n t r o l

D A C

A n a l o g F i l t e r

A O U T B 4 -

I n t e r p o l a t i o n F i lt e r

M C L K

r
i
a

r
t

S C L /C C L K (M 1 )

S D A /C D IN (M 2 )

A D 0 /C S (M 0 ) V L C

V Q

F IL T +

V A

G N D

V D

M U T E C 1

D S D _ S C L K ( M 3 )

G N D

C o n tro l P o r t( S ta n d -A lo n e M o d e S e le c t)

V L S

L R C K

S D I N 1

S D I N 2

S D I N 3

S C L K

D S D x x

A O U T B 4 +

A O U T A 4 -

A O U T A 4 +

A O U T B 2 -

A O U T B 2 +

A O U T A 2 -

A O U T A 2 +

A O U T B 1 -

A O U T B 1 +

A O U T A 1 -

A O U T A 1 +

V o l u m e C o n t r o l

I n t e r p o l a t i o n F i l t e r

A n a l o g F i l t e r

D A C

M i x e r

V o l u m e C o n t r o l

D A C

A n a l o g F i l t e r

I n t e r p o l a t i o n F i lt e r

A O U T B 3 -

A O U T B 3 +

A O U T A 3 -

A O U T A 3 +

S D I N 4

M U T E C 3

M U T E C 2

MAR `02

DS548PP2

CS4383

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ................................................................. 4
2. REGISTER QUICK REFERENCE ................................................................................... 14
3. REGISTER DESCRIPTION ............................................................................................. 15
4. PIN DESCRIPTION .......................................................................................................... 24

5. APPLICATIONS .............................................................................................................. 27

5.1 Grounding and Power Supply Decoupling ........................................................... 27
5.2 Oversampling Modes ........................................................................................... 27
5.3 Recommended Power-up Sequence ................................................................... 27
5.4 Analog Output and Filtering ................................................................................. 27
5.5 Interpolation Filter ................................................................................................ 27
5.6 Using DSD mode ................................................................................................. 28

6. CONTROL PORT INTERFACE ....................................................................................... 28

6.1 Enabling the Control Port ..................................................................................... 28
6.2 Format Selection .................................................................................................. 28
6.3 I

C Format ............................................................................................................ 28

6.3.1 Writing in I

C Format .......................................................................28

6.3.2 Reading in I

C Format ....................................................................29

6.4 SPI Format ........................................................................................................... 29

6.4.1 Writing in SPI ..................................................................................29

6.5 Memory Address Pointer (MAP)

..................................................................... 30

7. PARAMETER DEFINITIONS ........................................................................................... 38
8. REFERENCES ................................................................................................................. 38
9. PACKAGE DIMENSIONS ............................................................................................... 39

LIST OF FIGURES

Figure 1. Serial Mode Input Timing ................................................................................................. 8
Figure 2. Direct Stream Digital - Serial Audio Input Timing ............................................................. 9
Figure 3. Control Port Timing - I

C Format ................................................................................... 10

Figure 4. Control Port Timing - SPI Format ................................................................................... 11
Figure 5. Typical Connection Diagram Control Port...................................................................... 12

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product informa-
tion describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any
kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied
on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining
to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as
the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing
this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property
rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization
with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising
or promotional purposes, or for creating any work for resale.

An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material
and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained
from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law
and is to be exported or taken out of the PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH
APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.

Purchase of I

C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I

C Patent Rights to use

those components in a standard I

C system.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.

CS4383

Figure 6. Typical Connection Diagram Stand-Alone ..................................................................... 13
Figure 7. Control Port Timing, I

C Format .................................................................................... 29

Figure 8. Control Port Timing, SPI Format.................................................................................... 29
Figure 9. Single Speed (fast) Stopband Rejection ........................................................................ 31
Figure 10. Single Speed (fast) Transition Band ............................................................................ 31
Figure 11. Single Speed (fast) Transition Band (detail) ................................................................ 31
Figure 12. Single Speed (fast) Passband Ripple .......................................................................... 31
Figure 13. Single Speed (slow) Stopband Rejection..................................................................... 31
Figure 14. Single Speed (slow) Transition Band........................................................................... 31
Figure 15. Single Speed (slow) Transition Band (detail)............................................................... 32
Figure 16. Single Speed (slow) Passband Ripple......................................................................... 32
Figure 17. Double Speed (fast) Stopband Rejection..................................................................... 32
Figure 18. Double Speed (fast) Transition Band........................................................................... 32
Figure 19. Double Speed (fast) Transition Band (detail)............................................................... 32
Figure 20. Double Speed (fast) Passband Ripple......................................................................... 32
Figure 21. Double Speed (slow) Stopband Rejection ................................................................... 33
Figure 22. Double Speed (slow) Transition Band ......................................................................... 33
Figure 23. Double Speed (slow) Transition Band (detail) ............................................................. 33
Figure 24. Double Speed (slow) Passband Ripple ....................................................................... 33
Figure 25. Quad Speed (fast) Stopband Rejection ....................................................................... 33
Figure 26. Quad Speed (fast) Transition Band ............................................................................. 33
Figure 27. Quad Speed (fast) Transition Band (detail) ................................................................. 34
Figure 28. Quad Speed (fast) Passband Ripple ........................................................................... 34
Figure 29. Quad Speed (slow) Stopband Rejection...................................................................... 34
Figure 30. Quad Speed (slow) Transition Band ............................................................................ 34
Figure 31. Quad Speed (slow) Transition Band (detail) ................................................................ 34
Figure 32. Quad Speed (slow) Passband Ripple .......................................................................... 34
Figure 33. Format 0 - Left Justified up to 24-bit Data.................................................................... 35
Figure 34. Format 1 - I

S up to 24-bit Data................................................................................... 35

Figure 35. Format 2 - Right Justified 16-bit Data .......................................................................... 35
Figure 36. Format 3 - Right Justified 24-bit Data .......................................................................... 35
Figure 37. Format 4 - Right Justified 20-bit Data .......................................................................... 36
Figure 38. Format 5 - Right Justified 18-bit Data .......................................................................... 36
Figure 39. De-Emphasis Curve..................................................................................................... 36
Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, 3, or 4) ................................... 36
Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) .................................................. 37
Figure 42. Recommended Output Filter........................................................................................ 37

LIST OF TABLES

Table 1. Digital Interface Formats - PCM Mode............................................................................ 16
Table 2. Digital Interface Formats - DSD Mode ............................................................................ 16
Table 3. ATAPI Decode ................................................................................................................ 21
Table 4. Example Digital Volume Settings .................................................................................... 22
Table 5. Common Clock Frequencies........................................................................................... 26
Table 6. Digital Interface Format, Stand-Alone Mode Options...................................................... 26
Table 7. Mode Selection, Stand-Alone Mode Options .................................................................. 26
Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................... 26

CS4383

CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS

(Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth

10 Hz to 20 kHz, unless otherwise specified; Test load R

= 3 k

, C

= 100 pF

VA = 5 V, VD = 3.3V (see Figure 5)

For Single speed Mode Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz;
For Double Speed Mode Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz;
For Quad Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz;
For Direct Stream Digital Mode Fs = 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz).

Notes: 1. CS4383-KQ parts are tested at 25 °C.

2. One-half LSB of triangular PDF dither is added to data.

3. Performance limited by 16-bit quantization noise.

4. CS4383-BQ parts are tested at the extremes of the specified temperature range and Min/Max

performance numbers are guaranteed across the specified temperature range, T

. Typical numbers are

taken at 25 °C.

Parameters

Symbol

Min

Typ

Max

Unit

CS4383-KQ Dynamic Performance - All PCM modes and DSD (Note 1)

Specified Temperature Range

-10

°C

Dynamic Range (Note 2)

24-bit

unweighted

A-Weighted

16-bit

unweighted

(Note 3) A-Weighted

105
108

-
-

111
114

94
97

-
-
-
-

dB
dB
dB
dB

Total Harmonic Distortion + Noise

(Note 2)

24-bit

0 dB

-20 dB
-60 dB

16-bit

0 dB

(Note 3)

-20 dB
-60 dB

THD+N

-
-
-
-
-
-

-100

-91
-51
-94
-74
-34

-94

-
-
-
-
-

dB
dB
dB
dB
dB
dB

Idle Channel Noise / Signal-to-noise ratio

114

Interchannel Isolation

(1 kHz)

CS4383-BQ Dynamic Performance - All PCM modes and DSD (Note 4)

Specified Temperature Range

-40

°C

Dynamic Range (Note 2)

24-bit

unweighted

A-Weighted

16-bit

unweighted

(Note 3) A-Weighted

102
105

-
-

111
114

94
97

-
-
-
-

dB
dB
dB
dB

Total Harmonic Distortion + Noise

(Note 2)

24-bit

0 dB

-20 dB
-60 dB

16-bit

0 dB

(Note 3)

-20 dB
-60 dB

THD+N

-
-
-
-
-
-

-100

-91
-51
-94
-74
-34

-91

-
-
-
-
-

dB
dB
dB
dB
dB
dB

Idle Channel Noise / Signal-to-noise ratio

114

Interchannel Isolation

(1 kHz)

CS4383

ANALOG CHARACTERISTICS

(Continued)

POWER AND THERMAL CHARACTERISTICS

Notes: 5. V

is tested under load R

and includes attenuation due to Z

OUT

6. Current consumption increases with increasing FS within a given speed mode and is signal dependant.

Max values are based on highest FS and highest MCLK.

7. I

measured with no external loading on the SDA pin.

8. This specification is violated when the VLC supply is greater than VD and when pin 16 (M1/SDA) is tied

or pulled low. Logic tied to pin 16 needs to be able to sink this current.

9. Power down mode is defined as RST pin = Low with all clock and data lines held static.

10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.

Parameters

Symbol

Min

Typ

Max

Units

Analog Output - All PCM modes and DSD

Full Scale Differential Output Voltage (Note 5)

88% V

92% V

94% V

Vpp

Quiescent Voltage

50% V

VDC

Max Current from V

QMAX

Interchannel Gain Mismatch

0.1

Gain Drift

100

ppm/°C

Output Impedance

(Note 5)

OUT

100

AC-Load Resistance

Load Capacitance

100

Parameters

Symbol

Min

Typ

Max

Units

Power Supplies

Power Supply Current

normal operation, V

= 5V

(Note 6)

= 5V

= 3.3V

Interface current, VLC=5V (Note 7, 8)

VLS=5V

power-down state (all supplies) (Note 9)

-
-
-
-
-
-

60
45
30

200

66
70
46

-
-
-

mA
mA
mA

Power Dissipation

(Note 6)

VA = 5 V, VD = 3.3 V

normal operation

power-down (Note 9)

VA = 5 V, VD = 5 V

normal operation

power-down (Note 9)

-
-
-
-

400

525

485

680

mW
mW
mW
mW

Package Thermal Resistance

-
-

48
15

-
-

°C/Watt
°C/Watt

Power Supply Rejection Ratio (Note 10)

(1 kHz)

(60 Hz)

PSRR

-
-

60
40

-
-

dB
dB

CS4383

ANALOG FILTER RESPONSE

Notes: 11. Slow Roll-Off interpolation filter is only available in control port mode.

12. Filter response is not tested but is guaranteed by design.

13. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 to 32) have

been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

14. Single and Double Speed Mode Measurement Bandwidth is from stopband to 3 Fs.

Quad Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.

15. De-emphasis is available only in Single Speed Mode; Only 44.1kHz De-emphasis is available in Stand-

Alone Mode

Parameter

Fast Roll-Off

Slow Roll-Off (Note 11)

Unit

Min

Typ

Max

Min

Typ

Max

Combined Digital and On-chip Analog Filter Response - Single Speed Mode (Note 12)
Passband (Note 13)

to -0.01 dB corner

to -3 dB corner

0
0

-
-

.454
.499

0
0

-
-

0.417
0.499

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

+0.01

-0.01

+0.01

StopBand

.547

.583

StopBand Attenuation

(Note 14)

Group Delay

12/Fs

6.5/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.41/Fs

±0.14/Fs

De-emphasis Error (Note 15)

Fs = 32 kHz

(Relative to 1kHz)

Fs = 44.1 kHz

Fs = 48 kHz

-
-
-

±0.23
±0.14
±0.09

-
-
-

±0.23
±0.14
±0.09

dB
dB
dB

Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96kHz (Note 12)
Passband (Note 13)

to -0.01 dB corner

to -3 dB corner

0
0

-
-

.430
.499

0
0

-
-

.296
.499

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

0.01

-0.01

0.01

StopBand

.583

.792

StopBand Attenuation

(Note 14)

Group Delay

4.6/Fs

3.9/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.03/Fs

±0.01/Fs

Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192kHz (Note 12)
Passband (Note 13)

to -0.01 dB corner

to -3 dB corner

0
0

-
-

.105
.490

0
0

-
-

.104
.481

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

0.01

-0.01

0.01

StopBand

.635

.868

StopBand Attenuation

(Note 14)

Group Delay

4.7/Fs

4.2/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.01/Fs

Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 12)
Passband (Note 13)

to -0.1 dB corner

to -3 dB corner

-
-

0
0

-
-

120

kHz
kHz

Frequency Response 10 Hz to 20 kHz

-.01

0.1

CS4383

DIGITAL CHARACTERISTICS

(For KQ T

= -10 to +70 °C; For BQ T

= -40 to +85 °C; VLC = VLS =

1.8 V to 5.5 V)

ABSOLUTE MAXIMUM RATINGS

(GND = 0V; all voltages with respect to ground.)

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(GND = 0V; all voltages with respect to ground.)

Parameters

Symbol

Min

Typ

Max

Units

High-Level Input Voltage

Serial Data Port

Control Port

70% VLS
70% VLC

-
-

V
V

Low-Level Input Voltage

Serial Data Port

Control Port

-
-

20% VLS
20% VLC

V
V

Input Leakage Current

(Note 8)

±10

Input Capacitance

Maximum MUTEC Sink Current

MUTEC High-Level Output Voltage

MUTEC Low-Level Output Voltage

Parameters

Symbol

Min

Max

Units

DC Power Supply

Analog power

Digital internal power

Serial data port interface power

Control port interface power

VLS
VLC

-0.3
-0.3
-0.3
-0.3

6.0
6.0
6.0
6.0

V
V
V
V

Input Current, Any Pin Except Supplies

±10

Digital Input Voltage

Serial data port interface

Control port interface

IND-S

IND-C

-0.3
-0.3

VLS+ 0.4

VLC+ 0.4

V
V

Ambient Operating Temperature (power applied)

-55

125

°C

Storage Temperature

stg

-65

150

°C

Parameters

Symbol

Min

Typ

Max

Units

DC Power Supply

Analog power

Digital internal power

Serial data port interface power

Control port interface power

VLS
VLC

4.5
3.0
1.8
1.8

5.0
3.3
5.0
5.0

5.5
5.5
5.5
5.5

V
V
V
V

CS4383

SWITCHING CHARACTERISTICS - CONTROL PORT - I

C FORMAT

(For KQ T

= -10 to +70 °C; For BQ T

= -40 to +85 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC,

= 30 pF)

Notes: 19. Data must be held for sufficient time to bridge the transition time, t

, of SCL.

20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

21.

for Single-Speed Mode,

for Double-Speed Mode,

for Quad-Speed Mode.

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

scl

100

kHz

RST Rising Edge to Start

irs

500

Bus Free Time Between Transmissions

buf

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

hdst

4.0

µs

Clock Low time

low

4.7

µs

Clock High Time

high

4.0

µs

Setup Time for Repeated Start Condition

sust

4.7

µs

SDA Hold Time from SCL Falling

(Note 17)

hdd

µs

SDA Setup time to SCL Rising

sud

250

Rise Time of SCL and SDA

, t

µs

Fall Time SCL and SDA

, t

300

Setup Time for Stop Condition

susp

4.7

µs

Acknowledge Delay from SCL Falling

(Note 18)

ack

(Note 21)

256

---------------------

128

---------------------

------------------

b uf

hd st

l o w

h dd

h igh

s ud

S top

S t a rt

S D A

S C L

irs

R S T

hd st

t sust

t su sp

S t a r t

S to p

R e p e a t e d

a ck

Figure 3. Control Port Timing - I

C Format

CS4383

Figure 5. Typical Connection Diagram Control Port

D ig ita l

A u d io

S o u rc e

V L S

C S 4 3 8 3

M C L K

V D

A O U T A 1 +

1 1

3 2

0 .1 µ F

1 µ F

+ 3 .3 V to + 5 V

S D IN 1

1 µ F

0 .1 µ F

2 0

2 1

F IL T +

V Q

L R C K

S C L K

S D IN 3

S D IN 2

3 9

4 0

0 .1 µ F

4 7 µ F

V A

0 .1 µ F

1 µ F

0 .1 µ F

+ 1 .8 V to + 5 V

+ 5 V

4 3

S D IN 4

1 3

A n a lo g C o n d itio n in g

a n d M u tin g

A O U T A 1 -

A O U T A 2 +

3 5

3 6

A n a lo g C o n d itio n in g

a n d M u tin g

A O U T A 2 -

A O U T B 2 +

3 4

3 3

A n a lo g C o n d itio n in g

a n d M u tin g

A O U T B 2 -

A O U T A 3 +

2 9

3 0

A n a lo g C o n d itio n in g

a n d M u tin g

A O U T A 3 -

A O U T B 3 +

2 8

2 7

A n a lo g C o n d itio n in g

a n d M u tin g

A O U T B 3 -

A O U T A 4 +

2 5

2 6

A n a lo g C o n d itio n in g

a n d M u tin g

A O U T A 4 -

A O U T B 4 +

2 4

2 3

A n a lo g C o n d itio n in g

a n d M u tin g

A O U T B 4 -

M U T E C 1

4 1

1 9

M U T E C 3

1 2

P C M

3 1

G N D

M ic ro -

C o n tro lle r

V L C

0 .1 µ F

+ 1 .8 V to + 5 V

1 7

D S D

A u d io

S o u rc e

4 8

D S D B 2

4 2

D S D _ S C L K

D S D A 1

D S D B 3

D S D A 3

D S D A 4

D S D B 1

D S D A 2

4 6

4 5

4 7

4 4

D S D B 4

1 5

1 4

S C L /C C L K

S D A /C D IN

A D O /C S

R S T

1 8

1 6

N o te : N e c e s s a ry fo r I

c o n tro l p o rt o p e ra tio n

N o te *

A O U T B 1 +

3 7

A n a lo g C o n d itio n in g

a n d M u tin g

A O U T B 1 -

M U T E C 2

2 2

3 8

CS4383

D igital

A u dio

S ource

V LS

C S 4 38 3

M C LK

V D

A O U TA 1+

1 1

0 .1 µ F

1 µ F

+ 3.3 V to +5 V

S D IN 1

1 µ F

0.1 µ F

FILT+

V Q

LR C K

S C LK

S D IN 3

S D IN 2

0 .1 µ F

4 7 µ F

V A

0 .1 µ F

1 µ F

0.1 µ F

+1.8 V to +5 V

+ 5 V

4 3

S D IN 4

A nalog C onditioning

and M utin g

A O U T A 1-

A O U TA 2+

A nalog C onditioning

and M utin g

A O U T A 2-

A O U TB 2+

A nalog C onditioning

and M utin g

A O U T B 2-

A O U TA 3+

A nalog C onditioning

and M utin g

A O U T A 3-

A O U TB 3+

A nalog C onditioning

and M utin g

A O U T B 3-

A O U TA 4+

A nalog C onditioning

and M utin g

A O U T A 4-

A O U TB 4+

A nalog C onditioning

and M utin g

A O U T B 4-

M U T E C 1

M U TE C 3

P C M

G N D

V L C

0.1 µ F

+1 .8 V to +5 V

D S D

A ud io

S o urce

D S D B 2

D S D A 1

D S D B 3

D S D A 3

D S D A 4

D S D B 1

D S D A 2

D S D B 4

M 2

M 1

M 0

M 3 (D S D _S C LK

A O U TB 1+

A na log C ond ition ing

an d M u ting

A O U T B 1 -

M U TE C 2

2 2

R S T

N ote

D S D

N ote

D S D

: F or D S D o peratio n:

1) LR C K m ust be tie d to V LS and

rem ain sta tic hig h.

2) M 3 P C M sta nd-alone con figuration

pin be com es D S D _S C LK

S ta nd-A lone

M o de

C o nfiguratio n

47 K

N ote

V LC

N o te

V LC

: If s eries resisto rs are

used they m ust be <1k O hm . If
possible tie V LC to the V D supply
to redu ce possible excess current
consu m ption fro m V LC .

47 K

V LS

N ote

D S D

Figure 6. Typical Connection Diagram Stand-Alone

CS4383

REGISTER QUICK REFERENCE

Addr

Function

01h

Mode Control 1

CPEN

FREEZE

MCLKDIV

DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS

PDN

default

02h

Mode Control 2

Reserved

DIF2

DIF1

DIF0

Reserved

default

03h

Mode Control 3

SZC1

SZC0

SNGLVOL

RMP_UP

MUTEC+/-

AMUTE

Reserved

default

04h

Filter Control

Reserved

FILT_SEL

Reserved

DEM1

DEM0

RMP_DN

default

05h

Invert Control

INV_B4

INV_A4

INV_B3

INV_A3

INV_B2

INV_A2

INV_B1

INV_A1

default

06h

Mixing Control
Pair 1 (AOUTx1)

P1_A=B

P1ATAPI4

P1ATAPI3

P1ATAPI2

P1ATAPI1

P1ATAPI0

P1FM1

P1FM0

default

07h

Vol. Control A1

A1_MUTE

A1_VOL6

A1_VOL5

A1_VOL4

A1_VOL3

A1_VOL2

A1_VOL1

A1_VOL0

default

08h

Vol. Control B1

B1_MUTE

B1_VOL6

B1_VOL5

B1_VOL4

B1_VOL3

B1_VOL2

B1_VOL1

B1_VOL0

default

09h

Mixing Control
Pair 2 (AOUTx2)

P2_A=B

P2ATAPI4

P2ATAPI3

P2ATAPI2

P2ATAPI1

P2ATAPI0

P2FM1

P2FM0

default

0Ah

Vol. Control A2

A2_MUTE

A2_VOL6

A2_VOL5

A2_VOL4

A2_VOL3

A2_VOL2

A2_VOL1

A2_VOL0

default

0Bh

Vol. Control B2

B2_MUTE

B2_VOL6

B2_VOL5

B2_VOL4

B2_VOL3

B2_VOL2

B2_VOL1

B2_VOL0

default

0Ch

Mixing Control
Pair 3 (AOUTx3)

P3_A=B

P3ATAPI4

P3ATAPI3

P3ATAPI2

P3ATAPI1

P3ATAPI0

P3FM1

P3FM0

default

0Dh

Vol. Control A3

A3_MUTE

A3_VOL6

A3_VOL5

A3_VOL4

A3_VOL3

A3_VOL2

A3_VOL1

A3_VOL0

default

0Eh

Vol. Control B3

B3_MUTE

B3_VOL6

B3_VOL5

B3_VOL4

B3_VOL3

B3_VOL2

B3_VOL1

B3_VOL0

default

0Fh

Mixing Control
Pair 4 (AOUTx4)

P4_A=B

P4ATAPI4

P4ATAPI3

P4ATAPI2

P4ATAPI1

P4ATAPI0

P4FM1

P4FM0

default

10h

Vol. Control A4

A4_MUTE

A4_VOL6

A4_VOL5

A4_VOL4

A4_VOL3

A4_VOL2

A4_VOL1

A4_VOL0

default

11h

Vol. Control B4

B4_MUTE

B4_VOL6

B4_VOL5

B4_VOL4

B4_VOL3

B4_VOL2

B4_VOL1

B4_VOL0

default

12h

Chip Revision

PART3

PART2

PART1

PART0

Reserved

default

CS4383

REGISTER DESCRIPTION

Note:

All registers are read/write in I

C mode and write only in SPI, unless otherwise noted.

3.1

Mode Control 1 (address 01h)

3.1.1

CONTROL PORT ENABLE (CPEN)

Default = 0
0 - Disabled
1 - Enabled

Function

This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode
can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by
the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power-
up, the user should write this bit within 10 ms following the release of Reset.

3.1.2

FREEZE CONTROLS (FREEZE)

Default = 0
0 - Disabled
1 - Enabled

Function:

This function allows modifications to be made to the registers without the changes taking effect until
the FREEZE is disabled. To make multiple changes in the Control port registers take effect simulta-
neously, enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.

3.1.3

MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

Default = 0
0 - Disabled
1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all
other internal circuitry.

3.1.4

DAC PAIR DISABLE (DACX_DIS)

Default = 0
0 - Enabled
1 - Disabled

Function:

When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power down bit is enabled to eliminate the
possibility of audible artifacts.

CPEN

FREEZE

MCLKDIV

DAC4_DIS

DAC3_DIS

DAC2_DIS

DAC1_DIS

PDN

CS4383

3.1.5

POWER DOWN (PDN)

Default = 1
0 - Disabled
1 - Enabled

Function:

The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to `enabled' on power-up and
must be disabled before normal operation in Control Port mode can occur.

3.2

Mode Control 2 (address 02h)

3.2.1

DIGITAL INTERFACE FORMAT (DIF)

Default = 000 - Format 0 (Left Justified, up to 24-bit data)

Function:

These bits select the interface format for the serial audio input. The Functional Mode bits determine
whether PCM or DSD mode is selected.

PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in Figures 33-38.

DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required
Master clock to DSD data rate is defined by the Digital Interface Format pins.

Reserved

DIF2

DIF1

DIF0

Reserved

DIF2

DIF1

DIF0

DESCRIPTION

Format

FIGURE

Left Justified, up to 24-bit data

S, up to 24-bit data

Right Justified, 16-bit data

Right Justified, 24-bit data

Right Justified, 20-bit data

Right Justified, 18-bit data

Reserved

Table 1. Digital Interface Formats - PCM Mode

DIF2

DIF1

DIFO

DESCRIPTION

64x oversampled DSD data with a 4x MCLK to DSD data rate

64x oversampled DSD data with a 6x MCLK to DSD data rate

64x oversampled DSD data with a 8x MCLK to DSD data rate

64x oversampled DSD data with a 12x MCLK to DSD data rate

128x oversampled DSD data with a 2x MCLK to DSD data rate

128x oversampled DSD data with a 3x MCLK to DSD data rate

128x oversampled DSD data with a 4x MCLK to DSD data rate

128x oversampled DSD data with a 6x MCLK to DSD data rate

Table 2. Digital Interface Formats - DSD Mode

CS4383

3.3

Mode Control 3 (address 03h)

3.3.1

SOFT RAMP AND ZERO CROSS CONTROL (SZC)

Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings

Function:

Immediate Change

When Immediate Change is selected all level changes will take effect immediately in one step.

Zero Cross

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel.

Soft Ramp

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods.

Soft Ramp on Zero Crossing

Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.

SZC1

SZC0

SNGLVOL

RMP_UP

MUTEC+/-

AMUTE

Reserved

CS4383

3.3.2

SINGLE VOLUME CONTROL (SNGLVOL)

Default = 0
0 - Disabled
1 - Enabled

Function:

The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel
Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.

3.3.3

SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP)

Default = 0
0 - Disabled
1 - Enabled

Function:

An un-mute will be performed after executing a filter mode change, after a LRCK/MCLK ratio change
or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is ef-
fected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register.
When disabled, an immediate un-mute is performed in these instances.

Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN
bit.

3.3.4

MUTEC POLARITY (MUTEC +/-)

Default = 0
0 - Active Low
1 - Active High

Function:

The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default) the
MUTEC pins are low when active. When set to 1 the MUTEC pin(s) are high when active.

Note: When the on board mute circuitry is designed for active high, the MUTEC outputs will be low
(un-muted) for the period of time during reset and before this bit is enabled to 1.

3.3.5

AUTO-MUTE (AMUTE)

Default = 1
0 - Disabled
1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and
muting is done independently for each channel. The quiescent voltage on the output will be retained
and the Mute Control pin will go active during the mute period. The muting function is affected, similar
to volume control changes, by the Soft and Zero Cross bits in the Mode Control 3 register.

CS4383

3.5

Invert control (address 05h)

3.5.1

INVERT SIGNAL POLARITY (INV_XX)

Default = 0
0 - Disabled
1 - Enabled

Function:

When enabled, these bits will invert the signal polarity of their respective channels.

3.6

Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)
Mixing Control Pair 4 (Channels A4 & B4)(address 0Fh)

3.6.1

CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)

Default = 0
0 - Disabled
1 - Enabled

Function:

The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel
Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are
determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Chan-
nel Bytes are ignored when this function is enabled.

3.6.2

ATAPI CHANNEL MIXING AND MUTING (ATAPI)

Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)

Function:

The CS4383 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI
functions are applied per A-B pair. Refer to Table 3 and Figure 41 for additional information

INV_B4

INV_A4

INV_B3

INV_A3

INV_B2

INV_A2

INV_B1

INV_A1

Px_A=B

PxATAPI4

PxATAPI3

PxATAPI2

PxATAPI1

PxATAPI0

PxFM1

PxFM0

CS4383

3.6.3

FUNCTIONAL MODE (FM)

Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Direct Stream Digital Mode

Function:

Selects the required range of input sample rates or DSD Mode. When DSD mode is selected for any
channel pair then all pairs will switch to DSD mode.

ATAPI4

ATAPI3

ATAPI2

ATAPI1

ATAPI0

AOUTAx

AOUTBx

MUTE

b[(L+R)/2]

MUTE

b[(L+R)/2]

MUTE

b[(L+R)/2]

a[(L+R)/2]

MUTE

a[(L+R)/2]

b[(L+R)/2]

MUTE

[(aL+bR)/2]

MUTE

[(bL+aR)/2]

MUTE

[(aL+bR)/2]

MUTE

[(aL+bR)/2]

[(bL+aR)/2]

[(aL+bR)/2]

Table 3. ATAPI Decode

CS4383

PIN DESCRIPTION

Pin Name

Pin Description

Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operat-
ing Conditions for appropriate voltages.

GND

Ground (Input) - Ground reference. Should be connected to analog ground.

MCLK

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 5 illustrates
several standard audio sample rates and the required master clock frequency.

LRCK

Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio
data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

SDIN1
SDIN2
SDIN3
SDIN4

11
12
13

Serial Audio Data Input (Input) - Input for two's complement serial audio data.

SCLK

Serial Clock (Input) - Serial clock for the serial audio interface.

VLC

Control Port Power (Input) - Determines the required signal level for the control port. Refer to the Rec-
ommended Operating Conditions for appropriate voltages.

RST

Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.

FILT+

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram.

Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively
coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is
specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source
impedance and any current drawn from this pin will alter device performance. However, VQ can be
used to bias the analog circuitry assuming there is no AC signal component and the DC current is less
than the maximum specified in the Analog Characteristics and Specifications section.

S D IN 3

G ND

A OU TB2-

A OU TA3+

A OUT B3-

AO UTB 2+

V A

AO UTA 3-

AO UTB 3+

1 0

1 1

1 2

1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4

3 1

3 5

3 3

2 9

2 7

3 6

3 4

3 2

3 0

2 8

2 6

2 5

4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7

M CLK

DSD B1

V D

S DIN1

DS DA 2

DS DA 1

GND

S CLK

SDIN2

LRCK (DSD _EN)

(
D

C S4383

I
N

(
S

/
CCL

)

(
S

/
CDI

(
A

/
C

)

AO UTA 2+

A O UTA 2-

A OU TA4-

A O UTA 4+

T ST

CS4383

MUTEC1
MUTEC2
MUTEC3

41
22
19

Mute Control (Output) - The Mute Control pins go low during power-up initialization, reset, muting,
power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are intended
to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any sin-
gle supply system. The use of external mute circuits are not mandatory but may be desired for designs
requiring the absolute minimum in extraneous clicks and pops.

AOUTA1 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-
AOUTA4 +,-
AOUTB4 +,-

39, 40
38, 37
35, 36
34, 33
29, 30
28, 27
25, 26
24, 23

Differential Analog Output (Output) - The full scale differential analog output level is specified in the
Analog Characteristics specification table.

Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Oper-
ating Conditions for appropriate voltages.

VLS

Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-
face. Refer to the Recommended Operating Conditions for appropriate voltages.

Control Port Definitions

SCL/CCLK

Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage in I

C mode as shown in the Typical Connection Diagram.

SDA/CDIN

Serial Control Data (Input/Output) - SDA is a data I/O line in I

C mode and requires an external pull-up

resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the input
data line for the control port interface in SPI mode.

AD0/CS

Address Bit 0 (I

C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I

C mode;

CS is the chip select signal for SPI format.

Stand-Alone Definitions

M0
M1
M2
M3

16
15
14
42

Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables 6 and 7.

DSD Definitions

DSD_SCLK

DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface.

DSD_EN

DSD-Enable (Input) - When held at logic `1' the device will enter DSD mode (Stand-Alone mode only).

DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
DSDA4
DSDB4

3
2
1

48
47
46
45
44

Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.

TST

Test - This pin needs to be tied to analog ground.

Pin Name

Pin Description

CS4383

*Note: These modes are only available in control port mode by setting the MCLKDIV bit = 1.

Mode

(sample-rate range)

Sample

Rate

(kHz)

MCLK (MHz)

Control port

only modes

MCLK Ratio

256x

384x

512x

768x

1024x*

Single Speed

(4 to 50 kHz)

8.1920

12.2880

16.3840

24.5760

32.7680

44.1

11.2896

16.9344

22.5792

33.8688

45.1584

12.2880

18.4320

24.5760

36.8640

49.1520

MCLK Ratio

128x

192x

256x

384x

512x*

Double Speed

(50 to 100 kHz)

8.1920

12.2880

16.3840

24.5760

32.7680

88.2

11.2896

16.9344

22.5792

33.8688

45.1584

12.2880

18.4320

24.5760

36.8640

49.1520

MCLK Ratio

64x

96x

128x

192x

256x*

Quad Speed

(100 to 200 kHz)

176.4

11.2896

16.9344

22.5792

33.8688

45.1584

192

12.2880

18.4320

24.5760

36.8640

49.1520

Table 5. Common Clock Frequencies

(DIF1)

(DIF0)

DESCRIPTION

FORMAT

FIGURE

Left Justified, up to 24-bit data

S, up to 24-bit data

Right Justified, 16-bit Data

Right Justified, 24-bit Data

Table 6. Digital Interface Format, Stand-Alone Mode Options

(DEM)

DESCRIPTION

Single-Speed without De-Emphasis (4 to 50 kHz sample rates)

Single-Speed with 44.1kHz De-Emphasis; see Figure 39

Double-Speed (50 to 100 kHz sample rates)

Quad-Speed (100 to 200 kHz sample rates)

Table 7. Mode Selection, Stand-Alone Mode Options

DSD_Mode

(LRCK1)

DESCRIPTION

64x oversampled DSD data with a 4x MCLK to DSD data rate

64x oversampled DSD data with a 6x MCLK to DSD data rate

64x oversampled DSD data with a 8x MCLK to DSD data rate

64x oversampled DSD data with a 12x MCLK to DSD data rate

128x oversampled DSD data with a 2x MCLK to DSD data rate

128x oversampled DSD data with a 3x MCLK to DSD data rate

128x oversampled DSD data with a 4x MCLK to DSD data rate

128x oversampled DSD data with a 6x MCLK to DSD data rate

Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options

CS4383

5. APPLICATIONS

5.1

Grounding and Power Supply
Decoupling

As with any high resolution converter, the CS4383
requires careful attention to power supply and
grounding arrangements to optimize performance.
Figures 5 & 6 show the recommended power ar-
rangement with VA, VD, VLS and VLC connected
to clean supplies. Decoupling capacitors should be
located as close to the device package as possible.
If desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be placed on each supply pin (see Section 1 for rec-
ommended voltages).

5.2

Oversampling Modes

The CS4383 operates in one of three oversampling
modes based on the input sample rate. Mode selec-
tion is determined by the M3 and M2 pins in Stand-
Alone mode or the FM bits in Control Port mode.
Single-Speed mode supports input sample rates up
to 50 kHz and uses a 128x oversampling ratio.
Double-Speed mode supports input sample rates up
to 100 kHz and uses an oversampling ratio of 64x.
Quad-Speed mode supports input sample rates up
to 200 kHz and uses an oversampling ratio of 32x.

5.3

Recommended Power-up Sequence

1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and VQ
will remain low.

2. Bring RST high. The device will remain in a low
power state with VQ low and will initiate the
Stand-Alone power-up sequence. The control port
will be accessible at this time. If Control Port oper-
ation is desired, write the CPEN bit prior to the
completion of the Stand-Alone power-up se-
quence, approximately 512 LRCK cycles in Sin-

gle-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode). Writing this bit will halt the Stand-
Alone power-up sequence and initialize the control
port to its default settings. The desired register set-
tings can be loaded while keeping the PDN bit set
to 1.

3. If Control Port Mode is selected via the CPEN
bit, set the PDN bit to 0 which will initiate the pow-
er-up sequence.

5.4

Analog Output and Filtering

The application note "Design Notes for a 2-Pole
Filter with Differential Input" discusses the sec-
ond-order Butterworth filter and differential to sin-
gle-ended converter which was implemented on the
CS4383 evaluation board, CDB4383, as seen in
Figure 42. The CS4383 does not include phase or
amplitude compensation for an external filter.
Therefore, the DAC system phase and amplitude
response will be dependent on the external analog
circuitry.

5.5

Interpolation Filter

To accommodate the increasingly complex re-
quirements of digital audio systems, the CS4383
incorporates selectable interpolation filters for each
mode of operation. A "fast" and a "slow" roll-off
filter is available in each of Single, Double, and
Quad Speed modes. These filters have been de-
signed to accommodate a variety of musical tastes
and styles. The FILT_SEL bit is used to select
which filter is used (see the control port section for
more details).

When in stand-alone mode, only the "fast" roll-off
filter is available.

Filter specifications can be found in Section 1, and
filter response plots can be found in Figures 9 to 32.

CS4383

5.6

Using DSD mode

In stand-alone mode, DSD operation is selected by
holding DSD_EN(LRCK) high and applying the
DSD data and clocks to the appropriate pins. The
M2:0 pins set the expected DSD rate and MCLK
ratio.

In control-port mode the FM bits set the device into
DSD mode (DSD_EN pin is not required to be held
high). The DIF register then controls the expected
DSD rate and MCLK ratio.

During DSD operation, the PCM related pins
should either be tied low or remain active with
clocks (except LRCK in Stand-Alone mode).
When the DSD related pins are not being used they
should either be tied static low, or remain active
with clocks (except M3 in Stand-Alone mode).

6. CONTROL PORT INTERFACE

The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.

The CS4383 has MAP auto increment capability,
enabled by the INCR bit in the MAP register,
which is the MSB. If INCR is 0, then the MAP will
stay constant for successive writes. If INCR is set
to 1, then MAP will auto increment after each byte
is written from register 01h to 08h and then from
09h and 11h, allowing block reads or writes of suc-
cessive registers in two separate sections (the
counter will not auto-increment to register 09h
from register 08h).

6.1

Enabling the Control Port

On the CS4383 the control port pins are shared
with stand-alone configuration pins. To enable the
control port, the user must set the CPEN bit. This
is done by performing a I

C or SPI write. Once the

control port is enabled, these pins are dedicated to
control port functionality.

To prevent audible artifacts the CPEN bit (see Sec-
tion 3.1.1) should be set prior to the completion of
the Stand-Alone power-up sequence, approximate-
ly 1024 LRCK cycles. Writing this bit will halt the
Stand-Alone power-up sequence and initialize the
control port to its default settings. Note, the CP_EN
bit can be set any time after RST goes high; how-
ever, setting this bit after the Stand-Alone power-
up sequence has completed can cause audible arti-
facts.

6.2

Format Selection

The control port has 2 formats: SPI and I

C, with

the CS4383 operating as a slave device.

If I

C operation is desired, AD0/CS should be tied

to VLC or GND. If the CS4383 ever detects a high
to low transition on AD0/CS after power-up and af-
ter the control port is activated , SPI format will be
selected.

6.3

C Format

In I

C Format, SDA is a bidirectional data line.

Data is clocked into and out of the part by the clock,
SCL, with a clock to data relationship as shown in
Figure 7. The receiving device should send an ac-
knowledge (ACK) after each byte received. There
is no CS pin. Pin AD0 forms the partial chip ad-
dress and should be tied to VLC or GND as re-
quired. The upper 6 bits of the 7 bit address field
must be 001100.

Note: MCLK is required during all I

C transac-

tions. Please see reference 4 for further details.

6.3.1

Writing in I

C Format

To communicate with the CS4383, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (low for a write). The next byte is the
Memory Address Pointer, MAP, which selects the
register to be read or written. The MAP is then fol-

CS4383

lowed by the data to be written. To write multiple
registers, continue providing a clock and data,
waiting for the CS4383 to acknowledge between
each byte. To end the transaction, send a STOP
condition.

6.3.2

Reading in I

C Format

To communicate with the CS4383, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (high for a read). The contents of the reg-
ister pointed to by the MAP will be output after the
chip address. To read multiple registers, continue
providing a clock and issue an ACK after each
byte. To end the transaction, send a STOP condi-
tion.

6.4

SPI Format

In SPI format, CS is the CS4383 chip select signal,
CCLK is the control port bit clock, CDIN is the in-
put data line from the microcontroller and the chip

address is 0011000. CS, CCLK and CDIN are all
inputs and data is clocked in on the rising edge of
CCLK.

Note that the CS4383 is write-only when in SPI
format.

6.4.1

Writing in SPI

Figure 8 shows the operation of the control port in
SPI format. To write to a register, bring CS low.
The first 7 bits on CDIN form the chip address and
must be 0011000. The eighth bit is a read/write in-
dicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into register designated by the
MAP. To write multiple registers, keep CS low and
continue providing clocks on CCLK. End the read
transaction by setting CS high.

S D A

S C L

0 0 1 1 0 0

A D D R
A D 0

R /W

S ta rt

A C K

D A T A
1 -8

A C K

D A T A
1 -8

A C K

S to p

N o te : If o p e r a tio n i s a w rite , th is b y te c o n ta in s t h e M e m o ry A d d re s s P o in te r, M A P .

N o te 1

Figure 7. Control Port Timing, I

C Format

M A P

M S B

L S B

D A T A

b y te 1

b y te n

R / W

M A P = M e m o ry A d d r e s s P o in te r

A D D R E S S

C H IP

C D I N

C C L K

C S

0 0 1 1 0 0 0

Figure 8. Control Port Timing, SPI Format

CS4383

7. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering So-
ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

8. REFERENCES

1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.

Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

2. CDB4383 Evaluation Board Datasheet
3. "Design Notes for a 2-Pole Filter with Differential Input" by Steven Green. Cirrus Logic Application Note

AN48

4. "The I

C-Bus Specification: Version 2.0" Philips Semiconductors, December 1998.

http://www.semiconductors.philips.com

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