Preliminary Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc. 2000

P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com

CS4228A

24-Bit, 96 kHz Surround Sound Codec

Features

Six 24-bit D/A Converters

- 100 dB dynamic range
- -90 dB THD+N

Two 24-bit A/D Converters

- 97 dB dynamic range
- -95 dB THD+N

Sample rates up to 100 kHz

Pop-free Digital Output Volume Controls

- 90.5 dB range, 0.5 dB resolution (182 levels)
- Variable smooth ramp rate, 0.125 dB steps

Mute Control pin for off-chip muting circuits

On-chip Anti-alias and Output Filters

De-emphasis filters for 32, 44.1 and 48 kHz

Description

The CS4228A codec provides two analog-to-digital and
six digital-to-analog delta-sigma converters, along with
volume controls, in a compact 28-pin SSOP device.
Combined with an IEC958 (SPDIF) receiver (like the
CS8414) and surround sound decoder (such as one of
the CS492x or CS493xx families), it is ideal for use in
DVD player, A/V receiver and car audio systems sup-
porting multiple standards such as Dolby Digital AC-3,
AAC, DTS, Dolby ProLogic, THX, and MPEG.

A flexible serial audio interface allows operation in Left
Justified, Right Justified, I

S, or One Line Data modes.

ORDERING INFORMATION

CS4228A-KS -10° to +70° C 28-pin SSOP
CDB4228A

Evaluation Board

SCL/CCLK

SDA/CDIN

LRCK

SCLK

SDIN1

SDOUT

IAL

AUDIO

CONTROL PORT

I
G

I
T

ANAL

OUT

AGE

AINL+

AINL-

SDIN2

MCLK

DGND

AINR+

AINR-

LEFT ADC

SDIN3

MUTEC

AD0/CS

RST

FILT

CENTER

SUB

I
GIT

I
L

DAT

A INT

ACE

RIGHT ADC

AGND

WIT

-
E

HASIS

DAC #1

CLOCK MANAGER

MUTE CONTROL

DAC #2

DAC #3

DAC #4

DAC #5

DAC #6

DIGITAL VOLUME

DGND

AGND

OCT `00

DS511PP1

CS4228A

DS511PP1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4

ANALOG CHARACTERISTICS ................................................................................................ 4
DIGITAL CHARACTERISTICS ................................................................................................. 6
SWITCHING CHARACTERISTICS .......................................................................................... 6
SWITCHING CHARACTERISTICS - CONTROL PORT........................................................... 8
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10
RECOMMENDED OPERATING CONDITIONS ..................................................................... 10

2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 11
3. FUNCTIONAL DESCRIPTION ............................................................................................... 12

3.1 Overview .......................................................................................................................... 12
3.2 Analog Inputs ................................................................................................................... 12

3.2.1 Line Level Inputs ................................................................................................. 12
3.2.2 High Pass Filter ................................................................................................... 12

3.3 Analog Outputs ................................................................................................................ 13

3.3.1 Line Level Outputs .............................................................................................. 13
3.3.2 Digital Volume Control ........................................................................................ 13

3.4 Mute Control .................................................................................................................... 14
3.5 Clock Generation ............................................................................................................. 14

3.5.1 Clock Source ....................................................................................................... 14
3.5.2 Synchronization ................................................................................................... 14

3.6 Digital Interfaces .............................................................................................................. 14

3.6.1 Serial Audio Interface Signals ............................................................................. 14
3.6.2 Serial Audio Interface Formats ............................................................................ 15

3.7 Control Port Signals ......................................................................................................... 17

3.7.1 SPI Mode ............................................................................................................ 17
3.7.2 Two Wire Mode ................................................................................................... 17

3.8 Control Port Bit Definitions ............................................................................................... 18
3.9 Power-up/Reset/Power Down Mode ................................................................................ 18
3.10 Power Supply, Layout, and Grounding .......................................................................... 19

4. REGISTER QUICK REFERENCE .......................................................................................... 20
5. REGISTER DESCRIPTIONS .................................................................................................. 21

5.1 Memory Address Pointer (MAP) ..................................................................................... 21
5.2 CODEC Clock Mode ........................................................................................................ 21
5.3 Chip Control ..................................................................................................................... 22
5.4 ADC Control ..................................................................................................................... 22
5.5 DAC Mute1 Control .......................................................................................................... 23
5.6 DAC Mute2 Control .......................................................................................................... 23

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/

Dolby, Pro Logic, and AC-3 are trademarks of Dolby Laboratories Licensing Corporation.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.

CS4228A

DS511PP1

5.7 DAC De-emphasis Control .............................................................................................. 24
5.8 Digital Volume Control ..................................................................................................... 24
5.9 Serial Port Mode .............................................................................................................. 25
5.10 Chip Status .................................................................................................................... 25

6. PIN DESCRIPTION ................................................................................................................. 26
7. PARAMETER DEFINITIONS .................................................................................................. 29
8. PACKAGE DIMENSIONS ...................................................................................................... 31

LIST OF FIGURES

Figure 1. Serial Audio Port Master Mode Timing .......................................................................... 7
Figure 2. Serial Audio Port Slave Mode Timing ............................................................................ 7
Figure 3. SPI Control Port Timing ................................................................................................. 8
Figure 4. Two Wire Control Port Timing ........................................................................................ 9
Figure 5. Recommended Connection Diagram ........................................................................... 11
Figure 6. Optional Line Input Buffer ............................................................................................ 12
Figure 7. Passive Output Filter with Mute ................................................................................... 13
Figure 8. Butterworth Output Filter with Mute ............................................................................. 13
Figure 9. I

S Serial Audio Formats ............................................................................................. 15

Figure 10.Left Justified Serial Audio Formats .............................................................................. 16
Figure 11.Right Justified Serial Audio Formats ............................................................................ 16
Figure 12.One Line Data Serial Audio Format ............................................................................. 16
Figure 13.Control Port Timing, SPI Slave Mode Write ................................................................. 17
Figure 14.Control Port Timing, Two Wire Slave Mode Write ....................................................... 18
Figure 15.Control Port Timing, Two Wire Slave Mode Read ....................................................... 18

LIST OF TABLES

Table 1. Serial Audio Port Input Channel Allocations ................................................................... 15
Table 2. Common Master Clock Frequencies.............................................................................. 27

CS4228A

DS511PP1

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS

(Unless otherwise specified T

= 25° C; VA = VD = VL = +5 V; Full

Scale Input Sine wave, 984.375 Hz; Fs = 48 kHz BRM, 96 kHz HRM; Measurement Bandwidth is 20 Hz to 20 kHz;
Local components as shown in Figure 5; SPI control mode, Left Justified serial format, MCLK = 256 x Fs for BRM,
128 x Fs for HRM, SCLK = 64 x Fs)

Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms), Tested with -1 dBFS input.

2. Filter response is not tested but is guaranteed by design.

3. Filter characteristics scale with output sample rate.

4. The analog modulator samples the input at 128 times Fs. For example, input the sample rate is

6.144 MHz for an output sample rate of 48 kHz. There is no rejection of input signals which are multiples
of the sampling frequency (n × 6.144 MHz ±20.0 kHz where n = 0,1,2,3...).

5. High Pass Filter characteristics are specified for Fs=44.1 KHz.

Specifications are subject to change without notice

Base Rate Mode

High Rate Mode

Parameter

Symbol

Min

Typ

Max

Min

Typ

Max

Units

Analog Input Characteristics

- Minimum gain setting (0 dB) Differential Input; unless otherwise specified.

Dynamic Range, -60 dBFS input

(A weighted)

(unweighted)

97
94

-
-

97
94

-
-

dB
dB

Total Harmonic Distortion + Noise

(Note 1) THD+N

-95

-88

-95

-88

Interchannel Isolation

100

Interchannel Gain Mismatch

0.1

Offset Error (with high pass filter)

LSB

Full Scale Input Voltage (Differential):

5.24

5.66

6.09

5.24

5.66

6.09

Vp-p

Gain Drift

100

ppm/°C

Input Resistance

Input Capacitance

A/D Decimation Filter Characteristics

(Note 2)

Passband

(Note 3)

0.022

21.77 0.022

43.54

kHz

Passband Ripple

0.01

0.05

Stopband

(Note 3)

30.0

6114

72.41

6071

kHz

Stopband Attenuation

(Note 4)

Group Delay

TBD

Group Delay Variation vs. Frequency

High Pass Filter Characteristics

(Note 2)

Frequency Response: -3 dB

(Note 5)

-0.13 dB

-
-

3.4

-
-

3.4

-
-

Hz
Hz

Phase Deviation

@ 20 Hz

(Note 5)

Degree

Passband Ripple

CS4228A

DS511PP1

ANALOG CHARACTERISTICS

(Continued)

Notes: 6. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz,

the 0.01 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.

7. Digital filter characteristics.

8. Measurement bandwidth is 10 Hz to 3 Fs.

Specifications are subject to change without notice

Base Rate Mode

High Rate Mode

Parameter

Symbol

Min

Typ

Max

Min

Typ

Max

Units

Analog Output Characteristics

- Minimum Attenuation, 10 k

, 10 pF load; unless otherwise specified.

Dynamic Range, -60 dBFS input

(A weighted)

(unweighted)

100

-
-

100

-
-

dB
dB

Total Harmonic Distortion + Noise

THD+N

-90

-83

-90

-83

Interchannel Isolation

Interchannel Gain Mismatch

0.1

Offset Voltage

Full Scale Output Voltage

3.42

3.7

3.98

3.42

3.7

3.98

Vp-p

Gain Drift

100

ppm/°C

Analog Output Load

Minimum Load Resistance:

Maximum Load Capacitance:

-
-

100

-
-

100

-
-

Combined Digital and Analog Filter Characteristics

(Note 2)

Frequency Response

10 Hz to 20 kHz

±0.1

Deviation from Linear Phase

±0.5

Degrees

Passband: to 0.01 dB corner

(Notes 6, 7)

21.77

43.54

kHz

Passband Ripple

(Note 7)

±0.01

Stopband

(Notes 6, 7)

26.2

62.5

kHz

Stopband Attenuation

(Notes 5, 8)

Group Delay (Fs = Input Word Rate)

tgd

27/Fs

TBD

Analog Loopback Performance

Signal-to-noise Ratio
(CCIR-2K weighted, -20 dB FS input)

CCIR-2K

CS4228A

DS511PP1

ANALOG CHARACTERISTICS

(Continued)

DIGITAL CHARACTERISTICS

Unless otherwise specified (T

= 25 °C; VA = VD + 5V,VL = 2.375 to

5.25V)

SWITCHING CHARACTERISTICS

= 25°C; VA = VD + 5V,VL = 2.375 to 5.25V, C

30 pF)

Base Rate Mode

High Rate Mode

Power Supply

Symbol

Min

Typ

Max

Min

Typ

Max

Units

Power Supply Current

Operating

VA = VD = VL = 5 V

Power Down: RST low, Clocks running

-
-
-

0.5

0.5
0.2
0.5

0.5

-
-
-

0.5

0.5
0.2
0.5

0.5

mA
mA
mA

Power Supply Rejection

(1 kHz, 10 mV

rms

)

Parameter

Symbol

Min

Max

Units

High-level Input Voltage

0.7xVL

Low-level Input Voltage

0.3xVL

High-level Output Voltage at

VL = 5 V

= -2.0 mA

= -100 uA

VL = 2.5 V

= -2.0 mA

VL - 1.0
VL - 0.7

0.9 X VL

-
-

V
V

Low-level Output Voltage at

VL = 5 V

= 2.0 mA

= 100 uA

VL = 2.5 V

= -2.0 mA

-
-

0.4
0.2

0.4

V
V

Input Leakage Current

(Digital Inputs)

Output Leakage Current

(High-Impedance Digital Outputs)

Parameter

Symbol

Min

Typ

Max

Units

Audio ADC's and DAC's Sample Rate

BRM

HRM

30
60

-
-

100

kHz
kHz

MCLK Frequency

3.84

25.6

MHz

MCLK Duty Cycle

BRM

MCLK =128, 384 Fs

MCLK = 256, 512 Fs

HRM

MCLK = 64, 192 Fs

MCLK = 128, 256 Fs

TBD

50
50

TBD

%
%

CS4228A

DS511PP1

3. FUNCTIONAL DESCRIPTION

3.1 Overview

The CS4228A is a 24-bit audio codec comprised of
2 analog-to-digital converters (ADC) and 6 digital-
to-analog converters (DAC), all implemented us-
ing single-bit delta-sigma techniques. Other func-
tions integrated with the codec include independent
digital volume controls for each DAC, digital DAC
de-emphasis filters, ADC high-pass filters, an on-
chip voltage reference, and a flexible serial audio
interface. All functions are configured through a
serial control port operable in SPI mode and in two
wire mode. Figure 5 shows the recommended con-
nections for the CS4228A.

3.2 Analog Inputs

3.2.1 Line Level Inputs

AINR+, AINR-, AINL+, and AINL- are the line
level analog inputs (See Figure 5). These pins are
internally biased to a DC operating voltage of ap-
proximately 2.3 VDC. AC coupling the inputs pre-
serves this bias and minimizes signal distortion.
Figure 5 shows operation with a single-ended input
source. This source may be supplied to either the

positive or negative input as long as the unused in-
put is connected to ground through capacitors as
shown. When operated with single-ended inputs,
distortion will increase at input levels higher than
-1 dBFS. Figure 6 shows an example of a differen-
tial input circuit.

Muting of the stereo ADC is possible through the
ADC Control Byte.

The ADC output data is in 2's complement binary
format. For inputs above positive full scale or be-
low negative full scale, the ADC will output
7FFFFFH or 800000H, respectively.

3.2.2 High Pass Filter

Digital high pass filters in the signal path after the
ADCs remove any DC offsts present on the analog
inputs. The high pass filter helps prevent audible
"clicks" when switching between audio sources
downstream from the ADCs. The high pass filter
response, given in "High Pass Filter Characteristics
(Note 2)", scales linearly with sample rate. Thus,
for High Rate Mode, the -3 dB frequency at a 96
kHz sample rate will be equal to 96/44.1 times that
at a sample rate of 44.1 kHz.

0.1

10 k

4.7 k

10 k

AIN -

AIN +

2.2 nf

150

10 k

~ 8.5 k

signal

Figure 6. Optional Line Input Buffer

CS4228A

DS511PP1

The high pass filters can be disabled by setting the
HPF bit in the ADC Control register. When assert-
ed, any DC present at the analog inputs will be rep-
resented in the ADC outputs. The high pass filter
may also be "frozen" using the HPFZ bit in the
ADC Control register. In this condition, it will re-
member the DC offset present at the ADC inputs at
the moment the HPFZ bit was asserted, and will
continue to remove this DC level from the ADC
outputs. This is useful in cases where it is desirable
to eliminate a fixed DC offset while still maintain-
ing full frequency response down to DC.

3.3 Analog Outputs

3.3.1 Line Level Outputs

The CS4228A contains on-chip buffer amplifiers
capable of producing line level outputs. These am-
plifiers are biased to a quiescent DC level of ap-
proximately 2.3 V. This bias, as well as variations
in offset voltage, are removed using off-chip AC
load coupling.

The delta-sigma conversion process produces high
frequency noise beyond the audio passband, most
of which is removed by the on-chip analog filters.
The remaining out-of-band noise can be attenuated
using an off-chip low pass filter. For most applica-
tions, a simple passive filter as show in Figure 7 can
be used. Note that this circuit also serves to block
the DC present at the outputs. Figure 8 gives an ex-
ample of a filter which can be used in applications
where greater out of band attenuation is desired.
The 2-pole Butterworth filter has a -3 dB frequency
of 50 kHz, a passband attenuation of 0.1 dB at
20 kHz providing optimal out-of-band filtering for
sample rates from 44.1 kHz to 96 kHz. The filter
has and a gain of 1.56 providing a 2 Vrms output
signal.

3.3.2 Digital Volume Control

Each DAC's output level is controlled via the Dig-
ital Volume Control register operating over the
range of 0 to 90.5 dB attenuation with 0.5 dB reso-
lution. Volume control changes do not occur in-
stantaneously. Instead they ramp in increments of
0.125 dB at a variable rate controlled by the
RMP1:0 bits in the Digital Volume Control regis-
ter.

560

2SC2878

2.2 k

MUN2IIIT1

10 k

MUTEC

Line Out

MUTEDRV

10 k

100 k

AOUT

2SC3326

Figure 7. Passive Output Filter with Mute

C=142

3.57 k

2-Pole Butterworth Filter

OUT

3.57 k

MC33078

100 pf

1 nf

GND

1 nf

3.57 k

2 k

MUTE DRV

Line
Out

MUTE

2 VRMS

Figure 8. Butterworth Output Filter with Mute

CS4228A

DS511PP1

Each output can be independently muted via mute
control bits MUT6-1 in the DAC Mute1 Control
register. When asserted, MUT attenuates the corre-
sponding DAC to its maximum value (90.5 dB).
When MUT is deasserted, the corresponding DAC
returns to the attenuation level set in the Digital
Volume Control register. The attenuation is
ramped up and down at the rate specified by the
RMP1:0 bits.

To achieve complete digital attenuation of an in-
coming signal, Hard Mute controls are provided.
When asserted, Hard Mute will send zero data to a
corresponding pair of DACs. Hard Mute is not
ramped, so it should only be asserted after setting
the two corresponding MUT bits to prevent high
frequency transients from appearing on the DAC
outputs. Hard Mute is controlled by the
HMUTE56/34/12 bits in the DAC Mute2 Control
register.

3.4 Mute Control

The Mute Control pin is typically connected to an
external mute control circuit as shown in Figure 7
and Figure 8. The Mute Control pin is asserted dur-
ing power up, power down, and when serial port
clock errors are present. The pin can also be con-
trolled by the user via the control port, or automat-
ically asserted when zero data is present on all six
DAC inputs. To prevent large transients on the out-
put, it is desirable to mute the DAC outputs before
the Mute Control pin is asserted. Please see the
MUTEC pin in the Pin Descriptions section for
more information.

3.5 Clock Generation

The master clock, MCLK, is supplied to the
CS4228A from an external clock source. If MCLK
stops for 10 µs, the CS4228A will enter Power
Down Mode in which the supply current is reduced
as specified under "Power Supply". In all modes it
is required that the number of MCLK periods per
SCLK and LRCK period be constant.

3.5.1 Clock Source

The CS4228A internal logic requires an external
master clock, MCLK, that operates at multiples of
the sample rate frequency, Fs. The MCLK/Fs ratio
is determined by the CI1:0 bits in the CODEC
Clock Mode register.

3.5.2 Synchronization

The serial port is internally synchronized with
MCLK. If from one LRCK cycle to the next, the
number of MCLK cycles per LRCK cycle changes
by more than 32, the CS4228A will undergo an in-
ternal reset of its data paths in an attempt to resyn-
chronize. Consequently, it is advisable to mute the
DACs and clear the DIGPDN bit when changing
from one clock source to another to avoid the out-
put of undesirable audio signals as the device re-
synchronizes. It is adviseable to ensure that MCLK
complies with the Switching Characteristics at all
times when switching clock sources without reset-
ting the part.

3.6 Digital Interfaces

3.6.1 Serial Audio Interface Signals

The serial audio data is presented in 2's comple-
ment binary form with the MSB first in all formats.
The serial interface clock, SCLK, is used for both
transmitting and receiving audio data. SCLK can
be generated by the CS4228A (master mode) or it
can be input from an external source (slave mode).
Mode selection is made with the DMS1:0 bits in
the Serial Port Mode register. The number of
SCLK cycles in one sample period can be set using
the DCK1:0 bits as detailed in the Serial Port Mode
register.

The Left/Right clock (LRCK) is used to indicate
left and right data frames and the start of a new
sample period. It may be an output of the CS4228A
(master mode), or it may be generated by an exter-
nal source (slave mode). The frequency of LRCK is
the same as the system sample rate, Fs.

CS4228A

DS511PP1

SDIN1, SDIN2, and SDIN3 are the data input pins.
SDOUT, the data output pin, carries data from the
two 24-bit ADC's. The serial audio port may also
be operated in One Line Data Mode in which all 6
channels of DAC data is input on SDIN1 and the
stereo ADC data is output on SDOUT. Table 1 out-
lines the serial port input to DAC channel alloca-
tions.

3.6.2 Serial Audio Interface Formats

The digital audio port supports 6 formats, shown in
Figures 9, 10, 11 and 12. These formats are selected
using the DDF2:0 bits in the Serial Port Mode reg-
ister.

In One Line Data Mode, all 6 DAC channels are in-
put on SDIN1. One Line Data Mode is only avail-
able in BRM. See Figure 12 for channel
allocations.

DAC Inputs

SDIN1

left channel

right channel

single line

DAC #1
DAC #2
All 6 DAC channels (BRM)

SDIN2

left channel

right channel

DAC #3
DAC #4

SDIN3

left channel

right channel

DAC #5
DAC #6

Table 1. Serial Audio Port Input Channel Allocations

Figure 9. I

S Serial Audio Formats

I2S Mode, Data Valid on Rising Edge of SCLK

Bits/Sample

SCLK Rate(s)

Notes

32, 48, 64, 128 Fs
32, 64 Fs

BRM, 48 Fs available in slave mode only
HRM

18 to 24

48, 64, 128 Fs
64 Fs

BRM, 48 Fs available in slave mode only
HRM

LRCK

SCLK

Left Channel

Right Channel

SDIN1/2/3
SDOUT

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

CS4228A

DS511PP1

LRCK

SCLK

Left Channel

Right Channel

SDIN1/2/3
SDOUT

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

Figure 10. Left Justified Serial Audio Formats

Left Justified Mode, Data Valid on Rising Edge of SCLK

Bits/Sample

SCLK Rate(s)

Notes

32, 48, 64, 128 Fs
32, 64 Fs

BRM, 48 Fs available in slave mode only
HRM

18 to 24

48, 64, 128 Fs
64 Fs

BRM, 48 Fs available in slave mode only
HRM

LRCK

SCLK

Left Channel

Right Channel

SDIN1/2/3
SDOUT

6 5 4 3 2 1 0

9 8 7

15 14 13 12 11 10

6 5 4 3 2 1 0

9 8 7

15 14 13 12 11 10

Figure 11. Right Justified Serial Audio Formats

Right Justified Mode, Data Valid on Rising Edge of SCLK

Bits/Sample

SCLK Rate(s)

Notes

32, 48, 64, 128 Fs
32, 64 Fs

BRM, 48 Fs available in slave mode only
HRM

48, 64, 128 Fs
64 Fs

BRM, 48 Fs available in slave mode only
HRM

48, 64, 128 Fs
64 Fs

BRM, 48 Fs available in slave mode only
HRM

LRCK

SCLK

SDIN1/2/3

LSB

MSB

20 clks

64 clks

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

DAC1

DAC3

DAC5

DAC2

DAC4

DAC6

20 clks

ADCL

ADCR

20 clks

SDOUT

Left Channel

Right Channel

Figure 12. One Line Data Serial Audio Format

One Line Data Mode, Data Valid on Rising Edge of SCLK

Bits/Sample

SCLK Rate(s)

Notes

128 Fs

6 inputs, 2 outputs, BRM only

CS4228A

DS511PP1

3.7 Control Port Signals

Internal registers are accessed through the control
port. The control port may be operated asynchro-
nously with respect to audio sample rate. However,
to avoid potential interference problems, the con-
trol port pins should remain static if no register ac-
cess is required.

The control port has 2 operating modes: SPI mode
and two wire mode. In both modes the CS4228A
operates as a slave device. Mode selection is deter-
mined by the state of the SDOUT pin when RST
transitions from low to high: high for SPI, low for
two wire mode. SDOUT is internally pulled high to
VL. A resistive load from SDOUT to GND of less
than 47 k

will enable two wire mode after a hard-

ware reset.

3.7.1 SPI Mode

In SPI mode, CS is the CS4228A chip select signal,
CCLK is the control port bit clock input, and CDIN
is the input data line. There is no data output line,
therefore all registers are write-only in SPI mode.
Data is clocked in on the rising edge of CCLK.

Figure 13 shows the operation of the control port in
SPI mode. The first 7 bits on CDIN, after CS goes
low, form the chip address (0010000). The eighth
bit is a read/write indicator (R/W), which should al-
ways be low to write. The next 8 bits set the Mem-
ory Address Pointer (MAP) which is the address of
the register that is to be written. The following

bytes contain the data which will be placed into the
registers designated by the MAP.

The CS4228A has a MAP auto increment capabili-
ty, enabled by the INCR bit in the MAP register. If
INCR is zero, then the MAP will stay constant for
successive writes. If INCR is 1, then the MAP will
increment after each byte is written, allowing block
reads or writes of successive registers.

3.7.2 Two Wire Mode

In two wire mode, SDA is a bidirectional data line.
Data is clocked into and out of the port by the SCL
clock. The signal timing is shown in Figures 14
and 15. A Start condition is defined as a falling
transition of SDA while the clock is high. A Stop
condition is a rising transition while the clock is
high. All other transitions of SDA occur while the
clock is low.

The first byte sent to the CS4228A after a Start con-
dition consists of a 7 bit chip address field and a
R/W bit (high for a read, low for a write). The AD0
pin determines the LSB of the chip address field.
The upper 6 bits of the address field must be 00100
and the seventh bit must match AD0. If the opera-
tion is to be a write, the second byte is the Memory
Address Ponter (MAP), which selects the register
to be written. The succeeding byte(s) are data. If
the operation is to be a read, the second byte is sent
from the chip to the controller and contains the con-
tents of the register pointed to by the current value
of the MAP.

CCLK

12 13 14 15

CDIN

CHIP ADDRESS (WRITE)

MAP BYTE

0 0 1 0 0 0 0 0

MSB

DATA

DATA +n

R/W

6 5 4 3 2 1 0

8 9 10 11

4 5 6 7

0 1 2 3

16 17 18 19 20 21 22

INCR

(input)

7 6 5 4 3 2 1 0

Figure 13. Control Port Timing, SPI Slave Mode Write

CS4228A

DS511PP1

Since the read operation can not set the MAP, an
aborted write operation is used as a preamble. As
shown in Figure 15, the write operation is aborted
after the acknowledge for the MAP byte by sending
a stop condition. The following pseudocode illus-
trates an aborted write operation followed by a read
operation.

Send start condition.

Send 001000x0 chip address & write operation.

Receive acknowledge bit.

Send MAP byte, auto increment off.

Receive acknowledge bit.

Send stop condition, aborting write.

Send start condition.

Send 001000x1 chip address & read operation.

Receive acknowledge bit.

Receive byte, contents of selected register.

Send acknowledge bit.

Send stop condition.

Setting the auto increment bit in the MAP allows
successive reads or writes of consecutive registers.
Each byte is separated by an acknowledge bit.

3.8 Control Port Bit Definitions

All registers are read/write, except the Chip Status
register which is read-only. For more detailed in-
formation, see the bit definition tables.

3.9 Power-up/Reset/Power Down Mode

Upon power up, the user should hold RST = 0 until
the power supplies and clocks stabilize. In this
state, the control registers are reset to their default
settings, and the device remains in a low power
mode in which the control port is inactive. The part
may be held in a low power reset state by clearing
the DIGPDN bit in the Chip Control register. In this
state, the digital portions of the CODEC are in re-
set, but the control port is active and the desired
register settings can be loaded. Normal operation is
achieved by setting the DIGPDN bit to 1, at which
time the CODEC powers up and normal operation
begins.

4 5 6 7

24 25

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

0 0 1 0 0 AD1 AD0 0

SDA

INCR

6 5 4 3 2 1 0

7 6 1 0

0 1 2 3

8 9

16 17 18 19

10 11

13 14 15

27 28

DATA +n

Figure 14. Control Port Timing, Two Wire Slave Mode Write

S C L

CH IP AD D RE SS (W RITE)

M A P BY TE

D A TA

D ATA + 1

ST AR T

A CK

STO P

AC K

A CK

AC K

0 0 1 0 0 A D 1 AD 0 0

S D A

0 0 1 0 0 AD 1 A D 0 1

C HIP A DD R ES S (R EA D)

S TAR T

IN CR

6 5 4 3 2 1 0

7 0

N O

8 9

12 13 14 15

4 5 6 7

0 1

20 21 22

2 3 2 4

26 27 28

2 3

1 0 1 1

1 7 1 8 1 9

A C K

DA TA + n

S TO P

Figure 15. Control Port Timing, Two Wire Slave Mode Read

CS4228A

DS511PP1

The CS4228A will enter a stand-by mode if the
master clock source stops for approximately 10

or if the number of MCLK cycles per LRCK period
varies by more than 32. Should this occur, the con-
trol registers retain their settings.

The CS4228A will mute the analog outputs, assert
the MUTEC pin and enter the Power Down Mode
if the supply drops below approximately 4 volts.

3.10 Power Supply, Layout, and Grounding

The CS4228A requires careful attention to power
supply and grounding details. VA is normally sup-
plied from the system 5 VDC analog supply. VD is
from a 5 VDC digital supply, or for optimum ADC
performance, connect VD through a diode to a
+5 V supply to lower the digital core voltage. VL
should be from the supply used for the devices dig-
itally interfacing with the CS4228A. The power up
sequence of these three supply pins is not impor-
tant.

AGND and DGND pins should both be tied to a
solid ground plane surrounding the CS4228A. The

system analog and digital ground planes should not
be separated under normal circumstances. A solid
ground plane underneath the part is recommended.

Decoupling capacitors should be mounted and
routed in such a way as to minimize the circuit path
length from the CS4228A supply pin or FILT pin,
through the capacitor, and back to the applicable
CS4228A AGND or DGND pin. The small value
ceramic capacitors should be closest to the part. In
some cases, ferrite beads in the VL, VD and VA
supply lines, and low-value resistances (~ 50

)

series with the LRCK, SCLK, SDIN and SDOUT
lines can help reduce coupling of digital signals
into the analog portions of the CS4228A.

The both capacitors on the FILT pin should be as
close to the CS4228A as possible. Any noise that
couples onto the FILT pin will couple directly onto
all of the analog outputs. Please see the CDB4228
evaluation board data sheet for recommended lay-
out of the decoupling components.

CS4228A

DS511PP1

4. REGISTER QUICK REFERENCE

Addr

Function

MAP Memory Address

Pointer

INCR

Reserved

MAP4

MAP3

MAP2

MAP1

MAP0

0x01 CODEC Clock Mode

HRM

Reserved

CI1

CI0

Reserved

default=0x04

0x02 Chip Control

DIGPDN

Reserved

ADCPDN

DACPDN56 DACPDN34 DACPDN12 Reserved

default=0x00

0x03 ADC Control

MUTL

MUTR

HPF

HPFZ

Reserved

default=0x00

0x04 DAC Mute1 Control

MUT6

MUT5

MUT4

MUT3

MUT2

MUT1

RMP1

RMP0

default=0xFC

0x05 DAC Mute2 Control

MUTEC

MUTCZ

Reserved

HMUTE56

HMUTE34

HMUTE12

Reserved

default=0x80

0x06 DAC De-emphasis

Control

DEMS1

DEMS0

DEM6

DEM5

DEM4

DEM3

DEM2

DEM1

default=0x80

0x07 DAC 1 Volume Cntrl

Vol7

Vol6

Vol5

Vol4

Vol3

Vol2

Vol1

Vol0

default=0x00

0x08 DAC 2 Volume Cntrl

Vol7

Vol6

Vol5

Vol4

Vol3

Vol2

Vol1

Vol0

default=0x00

0x09 DAC 3 Volume Cntrl

Vol7

Vol6

Vol5

Vol4

Vol3

Vol2

Vol1

Vol0

default=0x00

0x0A DAC 4 Volume Cntrl

Vol7

Vol6

Vol5

Vol4

Vol3

Vol2

Vol1

Vol0

default=0x00

0x0B DAC 5 Volume Cntrl

Vol7

Vol6

Vol5

Vol4

Vol3

Vol2

Vol1

Vol0

default=0x00

0x0C DAC 6 Volume Cntrl

Vol7

Vol6

Vol5

Vol4

Vol3

Vol2

Vol1

Vol0

default

=0x00

0x0D

Serial Port Mode

DCK1

DCK0

DMS1

DMS0

Reserved

DDF2

DDF1

DDF0

default

=0x84

0x0E

Chip Status

CLKERR

ADCOVL

Reserved

read only

CS4228A

DS511PP1

5.5 DAC Mute1 Control

Address 0x04

MUT6 - MUT1

Mute control for DAC6 - DAC1 respectively. When asserted, the corresponding DAC is digitally
attenuated to its maximum value (90.5 dB). When deasserted, the corresponding DAC atten-
uation value returns to the value stored in the corresponding Digital Volume Control register.
The attenuation value is ramped up and down at the rate specified by RMP1:0.
0 -

Normal output level

*1 -

Selected DAC output fully attenuated.

RMP1:0

Attenuation ramp rate.
*0 -

0.5 dB change per 4 LRCKs

1 -

0.5 dB change per 8 LRCKs

2 -

0.5 dB change per 16 LRCKs

3 -

0.5 dB change per 32 LRCKs

5.6 DAC Mute2 Control

Address 0x05

MUTEC

Controls the MUTEC pin
0 -

Normal operation

*1 -

MUTEC pin asserted low

MUTCZ

Automatically asserts the MUTEC pin on consecutive zeros. When enabled, 512 consecutive
zeros on all six DAC inputs will cause the MUTEC pin to be asserted low. A single non-zero
value on any DAC input will cause the MUTEC pin to deassert.
*0 -

Disabled

1 -

Enabled

HMUTE56/34/12

Hard mute the corresponding DAC pair. When asserted, zero data is sent to the corresponding

DAC pair causing an instantaneous mute. To prevent high frequency transients on the outputs,
a DAC pair should be fully attenuated by asserting the corresponding MUT6-MUT1 bits in the
DAC Mute Control register or by writing 0xFF to the corresponding Digital Volume Control reg-
isters before asserting HMUTE.
*0 -

Normal operation

1 -

DAC pair is muted

MUT6

MUT5

MUT4

MUT3

MUT2

MUT1

RMP1

RMP0

MUTEC

MUTCZ

RESERVED

HMUTE56

HMUTE34

HMUTE12

RESERVED

CS4228A

DS511PP1

6. PIN DESCRIPTION

SDIN1, SDIN2,
SDIN3

1, 2, 3

Serial Audio Data In (

Input) - Two's complement MSB-first serial audio data is input on this

pin. The data is clocked into SDIN1, SDIN2, SDIN3 via the serial clock and the channel is
determined by the Left/Right clock. The required relationship between the Left/Right clock,
serial clock and serial data is defined by the Serial Mode Register. The options are detailed
in Figures 9, 10, 11, and 12.

SDOUT

Serial Audio Data Out (

Output) - Two's complement MSB-first serial data is output on this

pin. The data is clocked out of SDOUT via the serial clock and the channel is determined by
the Left/Right clock. The required relationship between the Left/Right clock, serial clock and
serial data is defined by the Serial Mode Register. The options are detailed in Figures 9, 10,
11 and 12.
The state of the SDOUT pin during reset is used to set the Control Port Mode (two wire or
SPI). When RST is low, SDOUT is configured as an input, and the rising edge of RST
latches the state of the pin. A weak internal pull up is present such that a resistive load less
than 47 k

will pull the pin low, and the control port mode is two wire. When the resistive

load on SDOUT is greater than 47 k

during reset, the control port mode is SPI.

SCLK

Serial Clock (

Bidirectional) - Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins,

and out of the SDOUT pin. The pin is an output in master mode, and an input in slave
mode.
In master mode, SCLK is configured as an output. MCLK is divided internally to generate
SCLK at the desired multiple of the sample rate.
In slave mode, SCLK is configured as an input. The serial clock can be provided externally,
or the pin can be grounded and the serial clock derived internally from MCLK.
The required relationship between the Left/Right clock, serial clock and serial audio data is
defined by the Serial Port Mode register. The options are detailed in Figures 9, 10, 11, and
12.

Serial Audio Data In 3

SDIN3

SUB

Analog Out #6,Subwoofer

Serial Audio Data In 2

SDIN2

CENTER Analog Out #5, Center

Serial Audio Data In 1

SDIN1

Analog Out #4, Surround Right

Serial Audio Data Out

SDOUT

Analog Out #3, Surround Left

Serial Clock

SCLK

Analog Out #2, Front Right

Left/Right Clock

LRCK

Analog Out #1, Front Left

Digital Ground

DGND

AGND

Analog Ground

Digital Power

Analog Power

Digital Interface Power

AINL+

Left Channel Analog Input+

Master Clock

MCLK

AINL-

Left Channel Analog Input-

SCL/CCLK

SCL/CCLK

FILT

Internal Voltage Filter

SDA/CDIN

SDA/CDIN

AINR-

Right Channel Analog Input-

AD0/CS

AD0/CS

AINR+

Right Channel Analog Input+

Reset

RST

MUTEC Mute Control

1
2
3
4
5
6
7
8
9
10
11
12

1
2

24
23
22
21
20
19
18
17
16
15

CS4228A

DS511PP1

LRCK

Left/Right Clock (

Bidirectional) - The Left/Right clock determines which channel is cur-

rently being input or output on the serial audio data output, SDOUT. The frequency of the
Left/Right clock must be at the output sample rate, Fs. In Master mode, LRCK is an output,
in Slave Mode, LRCK is an input whose frequency must be equal to Fs and synchronous to
the Master clock.
Audio samples in Left/Right pairs represent simultaneously sampled analog inputs whereas
Right/Left pairs will exhibit a one sample period difference. The required relationship
between the Left/Right clock, serial clock and serial data is defined by the Serial Port Mode
register. The options are detailed in Figures 9, 10, 11 and 12

DGND

Digital Ground (

Input) - Digital Ground Reference.

Digital Power (

Input) - Digital Power Supply. Typically 5.0 VDC.

Digital Interface Power (

Input) - Digital interface power supply. Typically 2.5, 3.3 or

5.0 VDC. All digital output voltages and input threshholds scale with VL.

MCLK

Master Clock (

Input) - The master clock frequency must be either 128x, 256x, 384x or

512x the input sample rate in Base Rate Mode (BRM) and either 64x, 128x, 192x, or 256x
the input sample rate in High Rate Mode (HRM). Table 2 illustrates several standard audio
sample rates and the required master clock frequencies. The MCLK/Fs ratio is set by the
CI1:0 bits in the CODEC Clock Mode register.

SCL/CCLK

Serial Control Interface Clock (

Input) - Clocks the serial control data into or out of

SDA/CDIN.

SDA/CDIN

Serial Control Data I/O (

Bidirectional/Input) - In two wire mode, SDA is a bidirectional con-

trol port data line. A pull up resistor must be provided for proper open drain output operation.
In SPI mode, CDIN is the control port data input line. The state of the SDOUT pin during
reset is used to set the control port mode.

ADO/CS

Address Bit 0 / Chip Select (Input) - In two wire mode, AD0 is the LSB of the chip
address. In SPI mode, CS is used as a enable for the control port interface.

RST

Reset (Input) - When low, the device enters a low power mode and all internal registers
are reset to the default settings, including the control port. The control port can not be
accessed when reset is low.
When high, the control port and the CODEC become operational.

MUTEC

Mute Control (

Output) - The Mute Control pin goes low during the following conditions: pow-

er-up initialization, power-down, reset, no master clock present, or if the master clock to
left/right clock frequency ratio is incorrect. The Mute Control pin can also be user controlled
by the MUTEC bit in the DAC Mute2 Control register. Mute Control can be automatically as-
serted when 512 consecutive zeros are detected on all six DAC inputs, and automatically
deasserted when a single non-zero value is sent to any of the six DACs. The mute on zero
function is controlled by the MUTCZ bit in the DAC Mute2 Control register. The MUTEC pin
is intended to be used as a control for an external mute circuit to achieve a very low noise
floor during periods when no audio is present on the DAC outputs, and to prevent the clicks
and pops that can occur in any single supply system. Use of the Mute Control pin is not man-
datory but recommended.

Sample

Rate

(kHz)

MCLK (MHz)

HRM

BRM

64x

128x

192x

256x

128x

256x

384x

512x

4.0960

8.1920

12.2880 16.3840

44.1

5.6448

11.2896 16.9344 22.5792

6.1440

12.2880 18.4320 24.5760

4.0960

8.1920

12.2880 16.3840

88.2

5.6448

11.2896

16.9344 22.5792

6.1440

12.2880 18.4320 24.5760

Table 2. Common Master Clock Frequencies

CS4228A

DS511PP1

AINR+, AINR-,
AINL+, AINL-

16, 17, 19, 20

Differential Analog Inputs (

Input) - The analog signal inputs are presented deferentially to

the modulators via the AINR+/- and AINL+/- pins. The + and - input signals are 180° out of
phase resulting in a nominal differential input voltage of twice the input pin voltage. These
pins are biased to the internal reference voltage of approximately 2.3 V. A passive anti-alias-
ing filter is required for best performance, as shown in Figure 5. The inputs can be driven at
-1 dB FS single-ended if the unused input is connected to ground through a large value ca-
pacitor. A single ended to differential converter circuit can also be used for slightly better per-
formance.

FILT

Internal Voltage Filter (

Output) - Filter for internal circuits. An external capacitor is required

from FILT to analog ground, as shown in Figure 5. FILT is not intended to supply external
current. FILT+ has a typical source impedance of 250 k

and any current drawn from this

pin will alter device performance. Care should be taken during board layout to keep dynamic
signal traces away from this pin.

Analog Power (

Input) - Power for the analog and reference circuits. Typically 5.0 VDC.

AGND

Analog Ground (

Input) - Analog ground reference.

FR, FL, SR, SL
SUB, CENTER

23, 24, 25,

26, 27, 28

Analog Outputs (

Output) - Analog outputs from the DACs. The full scale analog output level

is specified in the Analog Characteristics specifications table. The amplitude of the outputs
is controlled by the Digital Volume Control registers 0x07 - 0x0C..

CS4228A

DS511PP1

7. PARAMETER DEFINITIONS

Dynamic Range

The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral
components over the specified bandwidth. Dynamic range is a signal-to-noise measurement
over the specified bandwidth made with a -60 dbFs signal. 60 dB is then added to the resulting
measurement to refer the measurement to full scale. This technique ensures that the distortion
components are below the noise level and do not effect the measurement. This measurement
technique has been accepted by the Audio Engineering Society, AES17-1991, and the
Electronic Industries Association of Japan, EIAJ CP-307.

Total Harmonic Distortion + Noise

The ratio of the RMS value of the signal to the RMS sum of all other spectral components over
the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components.
Expressed in decibels. ADCs are measured at -1dBFs as suggested in AES 17-1991 Annex A.

Idle Channel Noise / Signal-to-Noise-Ratio

The ratio of the RMS analog output level with 1 kHz full scale digital input to the RMS analog
output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz
bandwidth. Units in decibels. This specification has been standardized by the Audio
Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has
also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and
referred to as Signal-to-Noise-Ratio.

Total Harmonic Distortion (THD)

THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of
the test signal. Units in decibels.

Interchannel Isolation

A measure of crosstalk between channels. Measured for each channel at the converter's output
with no signal to the input under test and a full-scale signal applied to the other channel. Units
in decibels.

Frequency Response

A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude
response at 1 kHz. Units in decibels.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units are in decibels.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CDB4228A

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CDB4228A