Central
Semiconductor Corp.
TM
PROCESS
CP317
Small Signal Transistor
NPN - RF Transistor Chip
PRINCIPAL DEVICE TYPES
CMPT918
2N918
2N2857
2N5179
2N5770
BFY90
PN3563
PN3564
Process
EPITAXIAL PLANAR
Die Size
14.5 x 14.5 MILS
Die Thickness
9.0 MILS
Base Bonding Pad Area
2.4 x 2.2 MILS
Emitter Bonding Pad Area
2.4 x 2.2 MILS
Top Side Metalization
Al - 30,000
Back Side Metalization
Au - 18,000
PROCESS DETAILS
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
GEOMETRY
R2 (1-August 2002)
GROSS DIE PER 4 INCH WAFER
53,730
BACKSIDE COLLECTOR
Central
Semiconductor Corp.
TM
PROCESS
CP317
Typical Electrical Characteristics
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R2 (1-August 2002)
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