Central
Semiconductor Corp.
TM
PROCESS
CP147
Power Transistor
NPN - Darlington Chip
PRINCIPAL DEVICE TYPES
MJ11012 2N6282
MJ11014 2N6283
MJ11016 2N6284
Process
EPITAXIAL BASE
Die Size
195 X 195 MILS
Die Thickness
12 MILS
Base Bonding Pad Area
29 X 29 MILS
Emitter Bonding Pad Area
61 X 35 MILS
Top Side Metalization
Al - 30,000
Back Side Metalization
Ti/Ni/Au - Ni-6,000; Au-6,000
PROCESS DETAILS
R3 (1 -August 2002)
GEOMETRY
BACKSIDE COLLECTOR
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
GROSS DIE PER 5 INCH WAFER
280
Central
Semiconductor Corp.
TM
Central
Semiconductor Corp.
TM
PROCESS
CP147
Typical Electrical Characteristics
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R3 (1 -August 2002)
Central
Semiconductor Corp.
TM
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